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enabling outline layer causes bogus drc errors, so leave it off
author
Bdale Garbee
<bdale@gag.com>
Fri, 5 Nov 2010 04:48:36 +0000
(22:48 -0600)
committer
Bdale Garbee
<bdale@gag.com>
Fri, 5 Nov 2010 04:48:36 +0000
(22:48 -0600)
telenano.pcb
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diff --git
a/telenano.pcb
b/telenano.pcb
index badbf272e797bfd456467a54572a61497665bd04..dae41efcf39f6bf7f5f94183ad6b6b19ec5f5f17 100644
(file)
--- a/
telenano.pcb
+++ b/
telenano.pcb
@@
-1,5
+1,5
@@
# release: pcb 20091103
# release: pcb 20091103
-# date: Thu Nov 4
16:46:09
2010
+# date: Thu Nov 4
22:48:21
2010
# user: bdale (Bdale Garbee,KB0G)
# host: rover
# user: bdale (Bdale Garbee,KB0G)
# host: rover
@@
-1510,10
+1510,6
@@
Layer(2 "bottom")
)
Layer(3 "outline")
(
)
Layer(3 "outline")
(
- Line[0 0 100000 0 1000 2000 ""]
- Line[100000 0 100000 50000 1000 2000 ""]
- Line[100000 50000 0 50000 1000 2000 ""]
- Line[0 50000 0 0 1000 2000 ""]
)
Layer(4 "silk")
(
)
Layer(4 "silk")
(