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add outline layer
[hw/telenano]
/
telenano.pcb
diff --git
a/telenano.pcb
b/telenano.pcb
index 757151f5bff5126ed9960cc88eb524c09a1e8af4..7a9a9bcbda0fbb325eff579f17a293dc83bcf690 100644
(file)
--- a/
telenano.pcb
+++ b/
telenano.pcb
@@
-1496,6
+1496,10
@@
Layer(2 "bottom")
)
Layer(3 "outline")
(
+ Line[0 0 0 50000 1000 0 ""]
+ Line[0 50000 100000 50000 1000 0 ""]
+ Line[100000 50000 100000 0 1000 0 ""]
+ Line[100000 0 0 0 1000 0 ""]
)
Layer(4 "silk")
(