PCB["TeleLco" 450000 400000]
Grid[100.0 0 0 0]
-Cursor[0 0 0.000000]
+Cursor[222100 249800 0.000000]
PolyArea[200000000.000000]
Thermal[0.500000]
DRC[500 1000 500 500 1500 650]
-Flags("showdrc,nameonpcb,clearnew,snappin")
+Flags("showdrc,nameonpcb,clearnew")
Groups("1,c:2,s:3")
Styles["Signal,1000,3000,1500,1000:Power,2500,6000,3500,1000:Fat,4000,24000,23600,1000:Skinny,600,2402,1181,600"]
)
Layer(3 "outline")
(
+ Attribute("PCB::skip-drc" "1")
Line[100 0 450000 0 1000 2000 "clearline"]
- Line[450000 0 450000 275000 1000 2000 "clearline"]
- Line[450000 275000 447400 275000 1000 2000 "clearline"]
- Line[447400 275000 447400 325000 1000 2000 "clearline"]
- Line[447400 325000 450000 325000 1000 2000 "clearline"]
- Line[450000 325000 450000 400000 1000 2000 "clearline"]
+ Line[450000 0 450000 272500 1000 2000 "clearline"]
+ Line[447400 272500 447400 322500 1000 2000 "clearline"]
+ Line[447400 322500 450000 322500 1000 2000 "clearline"]
+ Line[450000 322500 450000 400000 1000 2000 "clearline"]
Line[450000 400000 0 400000 1000 2000 "clearline"]
- Line[0 400000 0 0 1000 2000 "found,clearline"]
+ Line[0 400000 0 0 1000 2000 "clearline"]
+ Line[450000 272500 447400 272500 1000 2000 "clearline"]
)
Layer(4 "silk")
(