PCB["TeleLco" 450000 375000]
Grid[100.0 0 0 0]
-Cursor[0 0 0.000000]
+Cursor[82300 124200 0.000000]
PolyArea[200000000.000000]
Thermal[0.500000]
DRC[500 1000 500 500 1500 650]
Via[50055 113788 3000 2000 0 1500 "" "thermal(1S)"]
Via[23355 138688 3000 2000 0 1500 "" "thermal(0X,1S)"]
Via[38555 124888 3000 2000 0 1500 "" "thermal(1S)"]
-Via[81755 147688 3000 2000 0 1500 "" "thermal(0+,1S)"]
Via[48955 136488 3000 2000 0 1500 "" ""]
Via[46855 128688 3000 2000 0 1500 "" ""]
Via[31755 104788 3000 2000 0 1500 "" "thermal(1S)"]
Via[74100 102500 3000 2000 0 1500 "" ""]
Via[71600 100000 3000 2000 0 1500 "" ""]
Via[81100 117400 3000 2000 0 1500 "" ""]
+Via[112300 156100 3000 2000 0 1500 "" "thermal(1S)"]
+Via[81755 147688 3000 2000 0 1500 "" "thermal(0+,1S)"]
+Via[95500 160900 3000 2000 0 1500 "" "thermal(1S)"]
Element["" "TDK_PS12" "U8" "TDK_PS12" 225000 277558 -4600 -3632 0 100 ""]
(
Element["" "lqfp64" "U7" "unknown" 191316 136064 17420 20352 0 100 ""]
(
- Pad[-24408 14763 -20865 14763 1181 787 1811 "PA2/USART2_TX/ADC_IN2/TIM2_CH3/TIM9_CH1" "16" "square"]
- Pad[20866 14763 24409 14763 1181 787 1811 "PB12/SPI2_NSS/I2C2_SMBA/USART3_CKI/ADC_IN18/TIM10_CH1" "33" "square,edge2"]
+ Pad[-24408 14763 -20865 14763 1181 787 1811 "PA2/USART2_TX/ADC_IN2/TIM2_CH3/TIM9_CH1/SEG1" "16" "square"]
+ Pad[20866 14763 24409 14763 1181 787 1811 "PB12/SPI2_NSS/I2C2_SMBA/USART3_CKI/ADC_IN18/TIM10_CH1/SEG12" "33" "square,edge2"]
Pad[-14763 -24409 -14763 -20866 1181 787 1811 "VDD3" "64" "square"]
- Pad[-14763 20865 -14763 24408 1181 787 1811 "PA3/USART2_RX/ADC_IN3/TIM2_CH4/TIM9_CH2" "17" "square,edge2"]
- Pad[-24408 12794 -20865 12794 1181 787 1811 "PA1/USART2_RTS/ADC_IN1/TIM2_CH2" "15" "square"]
- Pad[20866 12794 24409 12794 1181 787 1811 "PB13/SPI2_SCK/USART3_CTS/ADC_IN19/TIM9_CH1" "34" "square,edge2"]
+ Pad[-14763 20865 -14763 24408 1181 787 1811 "PA3/USART2_RX/ADC_IN3/TIM2_CH4/TIM9_CH2/SEG2" "17" "square,edge2"]
+ Pad[-24408 12794 -20865 12794 1181 787 1811 "PA1/USART2_RTS/ADC_IN1/TIM2_CH2/SEG0" "15" "square"]
+ Pad[20866 12794 24409 12794 1181 787 1811 "PB13/SPI2_SCK/USART3_CTS/ADC_IN19/TIM9_CH1/SEG13" "34" "square,edge2"]
Pad[-12794 -24409 -12794 -20866 1181 787 1811 "VSS3" "63" "square"]
Pad[-12794 20865 -12794 24408 1181 787 1811 "VSS4" "18" "square,edge2"]
Pad[-24408 10826 -20865 10826 1181 787 1811 "PA0/WKUP1/USART2_CTS/ADC_IN0/TIM2_CH1_ETR" "14" "square"]
- Pad[20866 10826 24409 10826 1181 787 1811 "PB14/SPI2_MISO/USART3_RTS/ADC_IN20/TIM9_CH2" "35" "square,edge2"]
- Pad[-10826 -24409 -10826 -20866 1181 787 1811 "PB9/TIM4_CH4/I2C1_SDA/TIM11_CH1" "62" "square"]
+ Pad[20866 10826 24409 10826 1181 787 1811 "PB14/SPI2_MISO/USART3_RTS/ADC_IN20/TIM9_CH2/SEG14" "35" "square,edge2"]
+ Pad[-10826 -24409 -10826 -20866 1181 787 1811 "PB9/TIM4_CH4/I2C1_SDA/TIM11_CH1/COM3" "62" "square"]
Pad[-10826 20865 -10826 24408 1181 787 1811 "VDD4" "19" "square,edge2"]
Pad[-24408 8857 -20865 8857 1181 787 1811 "VDDA" "13" "square"]
- Pad[20866 8857 24409 8857 1181 787 1811 "PB15/SPI2_MOSI/ADC_IN21/TIM11_CH1/RTC_50_60HZ" "36" "square,edge2"]
- Pad[-8857 -24409 -8857 -20866 1181 787 1811 "PB8/TIM4_CH3/I2C1_SCL/TIM10_CH1" "61" "square"]
+ Pad[20866 8857 24409 8857 1181 787 1811 "PB15/SPI2_MOSI/ADC_IN21/TIM11_CH1/RTC_50_60HZ/SEG15" "36" "square,edge2"]
+ Pad[-8857 -24409 -8857 -20866 1181 787 1811 "PB8/TIM4_CH3/I2C1_SCL/TIM10_CH1/SEG16" "61" "square"]
Pad[-8857 20865 -8857 24408 1181 787 1811 "PA4/SPI1_NSS/USART2_CK/ADC_IN4/DAC_OUT1" "20" "square,edge2"]
Pad[-24408 6889 -20865 6889 1181 787 1811 "VSSA" "12" "square"]
- Pad[20866 6889 24409 6889 1181 787 1811 "PC6/TIM3_CH1" "37" "square,edge2"]
+ Pad[20866 6889 24409 6889 1181 787 1811 "PC6/TIM3_CH1/SEG24" "37" "square,edge2"]
Pad[-6889 -24409 -6889 -20866 1181 787 1811 "BOOT0" "60" "square"]
Pad[-6889 20865 -6889 24408 1181 787 1811 "PA5/SPI1_SCK/ADC_IN5/DAC_OUT2/TIM2_CH1_ETR" "21" "square,edge2"]
- Pad[-24408 4920 -20865 4920 1181 787 1811 "PC3/ADC_IN13" "11" "square"]
- Pad[20866 4920 24409 4920 1181 787 1811 "PC7/TIM3_CH2" "38" "square,edge2"]
+ Pad[-24408 4920 -20865 4920 1181 787 1811 "PC3/ADC_IN13/SEG21" "11" "square"]
+ Pad[20866 4920 24409 4920 1181 787 1811 "PC7/TIM3_CH2/SEG25" "38" "square,edge2"]
Pad[-4920 -24409 -4920 -20866 1181 787 1811 "PB7/I2C1_SDA/TIM4_CH2/USART1_RX/PVD_IN" "59" "square"]
- Pad[-4920 20865 -4920 24408 1181 787 1811 "PA6/SPI1_MISO_ADC_IN6/TIM3_CH1/TIM10_CH1" "22" "square,edge2"]
- Pad[-24408 2952 -20865 2952 1181 787 1811 "PC2/ADC_IN12" "10" "square"]
- Pad[20866 2952 24409 2952 1181 787 1811 "PC8/TIM3_CH3" "39" "square,edge2"]
+ Pad[-4920 20865 -4920 24408 1181 787 1811 "PA6/SPI1_MISO_ADC_IN6/TIM3_CH1/TIM10_CH1/SEG3" "22" "square,edge2"]
+ Pad[-24408 2952 -20865 2952 1181 787 1811 "PC2/ADC_IN12/SEG20" "10" "square"]
+ Pad[20866 2952 24409 2952 1181 787 1811 "PC8/TIM3_CH3/SEG26" "39" "square,edge2"]
Pad[-2952 -24409 -2952 -20866 1181 787 1811 "PB6/I2C1_SCL/TIM4_CH1/USART1_TX" "58" "square"]
- Pad[-2952 20865 -2952 24408 1181 787 1811 "PA7/SPI1_MOSI/ADC_IN7/TIM3_CH2/TIM11_CH1" "23" "square,edge2"]
- Pad[-24408 983 -20865 983 1181 787 1811 "PC1/ADC_IN11" "9" "square"]
- Pad[20866 983 24409 983 1181 787 1811 "PC9/TIM3_CH4" "40" "square,edge2"]
- Pad[-983 -24409 -983 -20866 1181 787 1811 "PB5/I2C1_SMBA/TIM3_CH2/SPI1_MOSI" "57" "square"]
- Pad[-983 20865 -983 24408 1181 787 1811 "PC4/ADC_IN14" "24" "square,edge2"]
- Pad[-24408 -984 -20865 -984 1181 787 1811 "PC0/ADC_IN10" "8" "square"]
- Pad[20866 -984 24409 -984 1181 787 1811 "PA8/USART1_CK/MCO" "41" "square,edge2"]
- Pad[984 -24409 984 -20866 1181 787 1811 "PB4/JNTRSTSPI1_MISO/TIM3_CH1" "56" "square"]
- Pad[984 20865 984 24408 1181 787 1811 "PC5/ADC_IN15" "25" "square,edge2"]
+ Pad[-2952 20865 -2952 24408 1181 787 1811 "PA7/SPI1_MOSI/ADC_IN7/TIM3_CH2/TIM11_CH1/SEG4" "23" "square,edge2"]
+ Pad[-24408 983 -20865 983 1181 787 1811 "PC1/ADC_IN11/SEG19" "9" "square"]
+ Pad[20866 983 24409 983 1181 787 1811 "PC9/TIM3_CH4/SEG27" "40" "square,edge2"]
+ Pad[-983 -24409 -983 -20866 1181 787 1811 "PB5/I2C1_SMBA/TIM3_CH2/SPI1_MOSI/SEG9" "57" "square"]
+ Pad[-983 20865 -983 24408 1181 787 1811 "PC4/ADC_IN14/SEG22" "24" "square,edge2"]
+ Pad[-24408 -984 -20865 -984 1181 787 1811 "PC0/ADC_IN10/SEG18" "8" "square"]
+ Pad[20866 -984 24409 -984 1181 787 1811 "PA8/USART1_CK/MCO/COM0" "41" "square,edge2"]
+ Pad[984 -24409 984 -20866 1181 787 1811 "PB4/JNTRSTSPI1_MISO/TIM3_CH1/SEG8" "56" "square"]
+ Pad[984 20865 984 24408 1181 787 1811 "PC5/ADC_IN15/SEG23" "25" "square,edge2"]
Pad[-24408 -2953 -20865 -2953 1181 787 1811 "NRST" "7" "square"]
- Pad[20866 -2953 24409 -2953 1181 787 1811 "PA9/USART1_TX" "42" "square,edge2"]
- Pad[2953 -24409 2953 -20866 1181 787 1811 "PB3/JTDO/TIM2_CH2/TRACESWO/SPI1_SCK" "55" "square"]
- Pad[2953 20865 2953 24408 1181 787 1811 "PB0/ADC_IN8/TIM3_CH3/VREF_OUT" "26" "square,edge2"]
+ Pad[20866 -2953 24409 -2953 1181 787 1811 "PA9/USART1_TX/COM1" "42" "square,edge2"]
+ Pad[2953 -24409 2953 -20866 1181 787 1811 "PB3/JTDO/TIM2_CH2/TRACESWO/SPI1_SCK/SEG7" "55" "square"]
+ Pad[2953 20865 2953 24408 1181 787 1811 "PB0/ADC_IN8/TIM3_CH3/VREF_OUT/SEG5" "26" "square,edge2"]
Pad[-24408 -4921 -20865 -4921 1181 787 1811 "PH1/OSC_OUT" "6" "square"]
- Pad[20866 -4921 24409 -4921 1181 787 1811 "PA10/USART1_RX" "43" "square,edge2"]
- Pad[4921 -24409 4921 -20866 1181 787 1811 "PD2/TIM3_ETR" "54" "square"]
- Pad[4921 20865 4921 24408 1181 787 1811 "PB1/ADC_IN9/TIM3_CH4/VREF_OUT" "27" "square,edge2"]
+ Pad[20866 -4921 24409 -4921 1181 787 1811 "PA10/USART1_RX/COM2" "43" "square,edge2"]
+ Pad[4921 -24409 4921 -20866 1181 787 1811 "PD2/TIM3_ETR/COM7/SEG31/SEG43" "54" "square"]
+ Pad[4921 20865 4921 24408 1181 787 1811 "PB1/ADC_IN9/TIM3_CH4/VREF_OUT/SEG6" "27" "square,edge2"]
Pad[-24408 -6890 -20865 -6890 1181 787 1811 "PH0/OSC_IN" "5" "square"]
Pad[20866 -6890 24409 -6890 1181 787 1811 "PA11/USART1_CTS/USBDM/SPI1_MISO" "44" "square,edge2"]
- Pad[6890 -24409 6890 -20866 1181 787 1811 "PC12/USART3_CK" "53" "square"]
+ Pad[6890 -24409 6890 -20866 1181 787 1811 "PC12/USART3_CK/COM6/SEG30/SEG42" "53" "square"]
Pad[6890 20865 6890 24408 1181 787 1811 "PB2/BOOT1" "28" "square,edge2"]
Pad[-24408 -8858 -20865 -8858 1181 787 1811 "PC15/OSC32_OUT" "4" "square"]
Pad[20866 -8858 24409 -8858 1181 787 1811 "PA12/USART1_RTS/USBDP/SPI1_MOSI" "45" "square,edge2"]
- Pad[8858 -24409 8858 -20866 1181 787 1811 "PC11/USART3_RX" "52" "square"]
- Pad[8858 20865 8858 24408 1181 787 1811 "PB10/I2C2_SCL/USART3_TX/TIM2_CH3" "29" "square,edge2"]
+ Pad[8858 -24409 8858 -20866 1181 787 1811 "PC11/USART3_RX/COM5/SEG29/SEG41" "52" "square"]
+ Pad[8858 20865 8858 24408 1181 787 1811 "PB10/I2C2_SCL/USART3_TX/TIM2_CH3/SEG10" "29" "square,edge2"]
Pad[-24408 -10827 -20865 -10827 1181 787 1811 "PC14/OSC32_IN" "3" "square"]
Pad[20866 -10827 24409 -10827 1181 787 1811 "PA13/JTMS/SWDIO" "46" "square,edge2"]
- Pad[10827 -24409 10827 -20866 1181 787 1811 "PC10/USART3_TX" "51" "square"]
- Pad[10827 20865 10827 24408 1181 787 1811 "PB11/I2C2_SDA/USART3_RX/TIM2_CH4" "30" "square,edge2"]
+ Pad[10827 -24409 10827 -20866 1181 787 1811 "PC10/USART3_TX/COM4/SEG28/SEG40" "51" "square"]
+ Pad[10827 20865 10827 24408 1181 787 1811 "PB11/I2C2_SDA/USART3_RX/TIM2_CH4/SEG11" "30" "square,edge2"]
Pad[-24408 -12795 -20865 -12795 1181 787 1811 "PC13/RTC_AF1/WKUP2" "2" "square"]
Pad[20866 -12795 24409 -12795 1181 787 1811 "VSS2" "47" "square,edge2"]
- Pad[12795 -24409 12795 -20866 1181 787 1811 "PA15/JTDI/TIM2_CH1_ETR/SPI1_NSS" "50" "square"]
+ Pad[12795 -24409 12795 -20866 1181 787 1811 "PA15/JTDI/TIM2_CH1_ETR/SPI1_NSS/SEG17" "50" "square"]
Pad[12795 20865 12795 24408 1181 787 1811 "VSS1" "31" "square,edge2"]
Pad[-24408 -14764 -20865 -14764 1181 787 1811 "VLCD" "1" "square"]
Pad[20866 -14764 24409 -14764 1181 787 1811 "VDD2" "48" "square,edge2"]
)
-Element["" "0402" "C12" "0.1uF" 81742 142287 872 6161 1 100 ""]
+Element["" "0402" "C12" "0.1uF" 81742 142287 -2990 -12725 0 100 ""]
(
Pad[-393 1574 393 1574 1968 2000 2568 "1" "1" "square"]
Pad[-393 -1574 393 -1574 1968 2000 2568 "2" "2" "square"]
ElementLine [5000 -25000 5000 5000 1500]
ElementLine [-5000 -25000 5000 -25000 1500]
+ )
+
+Element["" "0402" "R109" "330" 87300 148600 576 1950 0 100 ""]
+(
+ Pad[-1574 -393 -1574 393 1968 2000 2568 "1" "1" "square"]
+ Pad[1574 -393 1574 393 1968 2000 2568 "2" "2" "square"]
+
+ )
+
+Element["" "0402" "C109" "47pF" 87326 144500 -2950 -8850 0 100 ""]
+(
+ Pad[-1574 -393 -1574 393 1968 2000 2568 "1" "1" "square"]
+ Pad[1574 -393 1574 393 1968 2000 2568 "2" "2" "square"]
+
+ )
+
+Element["" "0402" "R105" "330" 123526 154200 -16124 -13950 0 100 ""]
+(
+ Pad[-1574 -393 -1574 393 1968 2000 2568 "1" "1" "square"]
+ Pad[1574 -393 1574 393 1968 2000 2568 "2" "2" "square"]
+
+ )
+
+Element["" "0402" "R106" "330" 123526 158100 -11324 -12250 0 100 ""]
+(
+ Pad[-1574 -393 -1574 393 1968 2000 2568 "1" "1" "square"]
+ Pad[1574 -393 1574 393 1968 2000 2568 "2" "2" "square"]
+
+ )
+
+Element["" "0402" "R107" "330" 84626 160900 -6124 6650 0 100 ""]
+(
+ Pad[-1574 -393 -1574 393 1968 2000 2568 "1" "1" "square"]
+ Pad[1574 -393 1574 393 1968 2000 2568 "2" "2" "square"]
+
+ )
+
+Element["" "0402" "R108" "330" 106426 160900 -224 7150 0 100 ""]
+(
+ Pad[-1574 -393 -1574 393 1968 2000 2568 "1" "1" "square"]
+ Pad[1574 -393 1574 393 1968 2000 2568 "2" "2" "square"]
+
+ )
+
+Element["" "0402" "C105" "47pF" 116926 154200 -22850 -13228 0 100 ""]
+(
+ Pad[-1574 -393 -1574 393 1968 2000 2568 "1" "1" "square"]
+ Pad[1574 -393 1574 393 1968 2000 2568 "2" "2" "square"]
+
+ )
+
+Element["" "0402" "C106" "47pF" 116900 158100 -6924 -9450 0 100 ""]
+(
+ Pad[-1574 -393 -1574 393 1968 2000 2568 "1" "1" "square"]
+ Pad[1574 -393 1574 393 1968 2000 2568 "2" "2" "square"]
+
+ )
+
+Element["" "0402" "C107" "47pF" 90826 160900 -5172 1450 0 100 ""]
+(
+ Pad[1574 -393 1574 393 1968 2000 2568 "1" "1" "square"]
+ Pad[-1574 -393 -1574 393 1968 2000 2568 "2" "2" "square"]
+
+ )
+
+Element["" "0402" "C108" "47pF" 100126 160900 -6050 7250 0 100 ""]
+(
+ Pad[-1574 -393 -1574 393 1968 2000 2568 "1" "1" "square"]
+ Pad[1574 -393 1574 393 1968 2000 2568 "2" "2" "square"]
+
)
Layer(1 "top")
(
Line[192100 95900 188364 99636 1000 2000 "clearline"]
Line[74060 135544 76799 135544 1000 2000 "clearline"]
Line[74060 133576 76467 133576 1000 2000 "clearline"]
- Line[81055 152188 82455 152188 1000 2000 "clearline"]
Line[78455 143876 74060 139481 1000 2000 "clearline"]
Line[78455 143876 78455 154188 1000 2000 "clearline"]
Line[37753 133576 37055 134274 1000 2000 "clearline"]
Line[49141 114702 49141 117388 1000 2000 "clearline"]
Line[45655 136488 48655 136488 1000 2000 "clearline"]
Line[34893 121022 34559 120688 1000 2000 "clearline"]
- Line[84855 130288 84855 149788 1000 2000 "clearline"]
- Line[84855 149788 82455 152188 1000 2000 "clearline"]
Line[43300 17900 53600 7600 1000 2000 "clearline"]
Line[53600 7600 164000 7600 1000 2000 "clearline"]
Line[164000 7600 174200 17800 1000 2000 "clearline"]
Line[84500 53900 78500 59900 1000 2000 "clearline"]
Line[78500 59900 78500 133844 1000 2000 "clearline"]
Line[78500 133844 76800 135544 1000 2000 "clearline"]
- Line[134300 163800 77100 163800 1000 2000 "clearline"]
- Line[77100 163800 61200 147900 1000 2000 "clearline"]
Line[61200 147900 61200 142565 1000 2000 "clearline"]
Line[61200 142565 61167 142532 1000 2000 "clearline"]
- Line[156300 161200 78555 161200 1000 2000 "clearline"]
- Line[156900 159600 79255 159600 1000 2000 "clearline"]
- Line[157600 158000 79955 158000 1000 2000 "clearline"]
- Line[159700 156400 80655 156400 1000 2000 "clearline"]
- Line[80655 156400 78455 154200 1000 2000 "clearline"]
Line[194900 177800 202600 177800 1000 2000 "clearline"]
Line[202350 180350 198450 180350 1000 2000 "clearline"]
Line[198450 180350 194900 183900 1000 2000 "clearline"]
Line[201300 183800 222800 162300 1000 2000 "clearline"]
Line[153700 98200 113243 98200 2500 2000 "clearline"]
Line[136100 100500 114655 100500 1000 2000 "clearline"]
- Line[114655 100500 84855 130300 1000 2000 "clearline"]
Line[58448 155936 58448 157152 1000 2000 "clearline"]
Line[58448 157152 56500 159100 1000 2000 "clearline"]
Line[54455 155962 54455 157055 1000 2000 "clearline"]
Line[67072 142532 67072 145872 1000 2000 "clearline"]
Line[67072 145872 72300 151100 1000 2000 "clearline"]
Line[72300 151100 72300 154900 1000 2000 "clearline"]
- Line[72300 154900 78600 161200 1000 2000 "clearline"]
Line[69041 142532 69041 145541 1000 2000 "clearline"]
Line[69041 145541 73900 150400 1000 2000 "clearline"]
- Line[73900 150400 73900 154245 1000 2000 "clearline"]
- Line[73900 154245 79255 159600 1000 2000 "clearline"]
Line[71009 142532 71009 145009 1000 2000 "clearline"]
Line[71009 145009 75500 149500 1000 2000 "clearline"]
Line[75500 149500 75500 153500 1000 2000 "clearline"]
- Line[75500 153500 80000 158000 1000 2000 "clearline"]
Line[74060 123734 74366 123734 1000 2000 "clearline"]
Line[74366 123734 75100 123000 1000 2000 "clearline"]
Line[75100 123000 75100 107200 1000 2000 "clearline"]
Line[194200 109900 193300 109000 1000 2000 "clearline"]
Line[193300 109000 191700 109000 1000 2000 "clearline"]
Line[202143 109900 202143 113427 1000 2000 "clearline"]
+ Line[121952 154200 118500 154200 1000 2000 "clearline"]
+ Line[118474 158100 121952 158100 1000 2000 "clearline"]
+ Line[159700 156400 130500 156400 1000 2000 "clearline"]
+ Line[130500 156400 128300 154200 1000 2000 "clearline"]
+ Line[128300 154200 125100 154200 1000 2000 "clearline"]
+ Line[157600 158000 125200 158000 1000 2000 "clearline"]
+ Line[125200 158000 125100 158100 1000 2000 "clearline"]
+ Line[115326 158100 114300 158100 1000 2000 "clearline"]
+ Line[114300 158100 112300 156100 1000 2000 "clearline"]
+ Line[115352 154200 114200 154200 1000 2000 "clearline"]
+ Line[114200 154200 112300 156100 1000 2000 "clearline"]
+ Line[118400 154200 118400 152700 1000 2000 "clearline"]
+ Line[118400 152700 117400 151700 1000 2000 "clearline"]
+ Line[117400 151700 85700 151700 1000 2000 "clearline"]
+ Line[85700 151700 82500 154900 1000 2000 "clearline"]
+ Line[82500 154900 79155 154900 1000 2000 "clearline"]
+ Line[79155 154900 78455 154200 1000 2000 "clearline"]
+ Line[118400 158100 118400 159400 1000 2000 "clearline"]
+ Line[118400 159400 117200 160600 1000 2000 "clearline"]
+ Line[117200 160600 112900 160600 1000 2000 "clearline"]
+ Line[112900 160600 105700 153400 1000 2000 "clearline"]
+ Line[105700 153400 86300 153400 1000 2000 "clearline"]
+ Line[86300 153400 83200 156500 1000 2000 "clearline"]
+ Line[83200 156500 78500 156500 1000 2000 "clearline"]
+ Line[78500 156500 75500 153500 1000 2000 "clearline"]
+ Line[85752 144500 84943 144500 1000 2000 "clearline"]
+ Line[84943 144500 81755 147688 1000 2000 "clearline"]
+ Line[81055 152188 82138 152188 1000 2000 "clearline"]
+ Line[82138 152188 85726 148600 1000 2000 "clearline"]
+ Line[88874 148600 88874 144526 1000 2000 "clearline"]
+ Line[88874 144526 88900 144500 1000 2000 "clearline"]
+ Line[88874 144400 88874 126326 1000 2000 "clearline"]
+ Line[88874 126326 114700 100500 1000 2000 "clearline"]
+ Line[92400 160900 98552 160900 1000 2000 "clearline"]
+ Line[101700 160900 104852 160900 1000 2000 "clearline"]
+ Line[86200 160900 89252 160900 1000 2000 "clearline"]
+ Line[73900 150400 73900 154300 1000 2000 "clearline"]
+ Line[73900 154300 77700 158100 1000 2000 "clearline"]
+ Line[77700 158100 101300 158100 1000 2000 "clearline"]
+ Line[101300 158100 101700 158500 1000 2000 "clearline"]
+ Line[101700 158500 101700 160900 1000 2000 "clearline"]
+ Line[83052 160900 78300 160900 1000 2000 "clearline"]
+ Line[78300 160900 72300 154900 1000 2000 "clearline"]
+ Line[156900 159600 128500 159600 1000 2000 "clearline"]
+ Line[128500 159600 125800 162300 1000 2000 "clearline"]
+ Line[125800 162300 111700 162300 1000 2000 "clearline"]
+ Line[111700 162300 110300 160900 1000 2000 "clearline"]
+ Line[110300 160900 108000 160900 1000 2000 "clearline"]
+ Line[156300 161200 129300 161200 1000 2000 "clearline"]
+ Line[129300 161200 126600 163900 1000 2000 "clearline"]
+ Line[126600 163900 89800 163900 1000 2000 "clearline"]
+ Line[89800 163900 89200 163300 1000 2000 "clearline"]
+ Line[89200 163300 89200 160952 1000 2000 "clearline"]
+ Line[89200 160952 89252 160900 1000 2000 "clearline"]
+ Line[134300 163800 129100 163800 1000 2000 "clearline"]
+ Line[129100 163800 127400 165500 1000 2000 "clearline"]
+ Line[127400 165500 78800 165500 1000 2000 "clearline"]
+ Line[61200 147900 78800 165500 1000 2000 "clearline"]
)
Layer(2 "bottom")
(
)
Net("c2" "(unknown)")
(
- Connect("U7-34")
+ Connect("C106-2")
+ Connect("R106-1")
Connect("U9-36")
)
Net("com_0" "(unknown)")
)
Net("cs_radio" "(unknown)")
(
- Connect("U7-33")
+ Connect("C105-2")
+ Connect("R105-1")
Connect("U9-1")
)
Net("debug_clock" "(unknown)")
Connect("C33-2")
Connect("C36-1")
Connect("C37-1")
+ Connect("C105-1")
+ Connect("C106-1")
+ Connect("C107-1")
+ Connect("C108-1")
+ Connect("C109-1")
Connect("C601-2")
Connect("C602-2")
Connect("C603-1")
)
Net("miso2" "(unknown)")
(
- Connect("U7-35")
+ Connect("R107-1")
Connect("U9-34")
)
Net("mosi2" "(unknown)")
(
- Connect("U7-36")
+ Connect("C108-2")
+ Connect("R108-1")
Connect("U9-35")
)
Net("pad_a" "(unknown)")
)
Net("radio_int" "(unknown)")
(
- Connect("U7-3")
+ Connect("R109-1")
Connect("U9-33")
)
Net("reset_n" "(unknown)")
Connect("U7-1")
)
Net("unnamed_net29" "(unknown)")
+ (
+ Connect("C109-2")
+ Connect("R109-2")
+ Connect("U7-3")
+ )
+ Net("unnamed_net30" "(unknown)")
+ (
+ Connect("C107-2")
+ Connect("R107-2")
+ Connect("U7-35")
+ )
+ Net("unnamed_net31" "(unknown)")
+ (
+ Connect("R106-2")
+ Connect("U7-34")
+ )
+ Net("unnamed_net32" "(unknown)")
+ (
+ Connect("R105-2")
+ Connect("U7-33")
+ )
+ Net("unnamed_net33" "(unknown)")
+ (
+ Connect("R108-2")
+ Connect("U7-36")
+ )
+ Net("unnamed_net34" "(unknown)")
(
Connect("C30-1")
Connect("U9-21")
Connect("X1-3")
)
- Net("unnamed_net30" "(unknown)")
+ Net("unnamed_net35" "(unknown)")
(
Connect("C31-1")
Connect("U9-20")
Connect("X1-1")
)
- Net("unnamed_net31" "(unknown)")
+ Net("unnamed_net36" "(unknown)")
(
Connect("R16-1")
Connect("U9-27")
)
- Net("unnamed_net32" "(unknown)")
+ Net("unnamed_net37" "(unknown)")
(
Connect("C22-1")
Connect("L4-1")
Connect("U9-24")
)
- Net("unnamed_net33" "(unknown)")
+ Net("unnamed_net38" "(unknown)")
(
Connect("C25-1")
Connect("L1-2")
Connect("U9-23")
)
- Net("unnamed_net34" "(unknown)")
+ Net("unnamed_net39" "(unknown)")
(
Connect("R12-1")
Connect("U9-3")
)
- Net("unnamed_net35" "(unknown)")
+ Net("unnamed_net40" "(unknown)")
(
Connect("R13-1")
Connect("U9-4")
)
- Net("unnamed_net36" "(unknown)")
+ Net("unnamed_net41" "(unknown)")
(
Connect("C19-2")
Connect("U9-30")
)
- Net("unnamed_net37" "(unknown)")
+ Net("unnamed_net42" "(unknown)")
(
Connect("C25-2")
Connect("L2-1")
Connect("L4-2")
)
- Net("unnamed_net38" "(unknown)")
+ Net("unnamed_net43" "(unknown)")
(
Connect("C23-1")
Connect("L2-2")
Connect("L3-1")
)
- Net("unnamed_net39" "(unknown)")
+ Net("unnamed_net44" "(unknown)")
(
Connect("C26-1")
Connect("L1-1")
)
- Net("unnamed_net40" "(unknown)")
+ Net("unnamed_net45" "(unknown)")
(
Connect("C24-1")
Connect("C27-1")
Connect("L3-2")
)
- Net("unnamed_net41" "(unknown)")
+ Net("unnamed_net46" "(unknown)")
(
Connect("C27-2")
Connect("J8-1")
)
- Net("unnamed_net42" "(unknown)")
+ Net("unnamed_net47" "(unknown)")
(
Connect("D1-1")
Connect("R13-2")
)
- Net("unnamed_net43" "(unknown)")
+ Net("unnamed_net48" "(unknown)")
(
Connect("D8-1")
Connect("R12-2")
T 52300 65600 5 10 1 1 0 0 1
netname=swclk
}
-N 53600 58700 52300 58700 4
-{
-T 52800 58800 5 10 1 1 0 6 1
-netname=mosi2
-}
-N 53600 59500 52300 59500 4
-{
-T 52500 59600 5 10 1 1 0 6 1
-netname=c2
-}
-N 53600 59100 52300 59100 4
-{
-T 52800 59200 5 10 1 1 0 6 1
-netname=miso2
-}
C 59800 78300 1 0 0 capacitor.sym
{
T 60000 79000 5 10 0 0 0 0 1
netname=seg_d
}
N 63100 71100 64400 71100 4
-{
-T 63800 71200 5 10 1 1 0 0 1
-netname=radio_int
-}
C 73000 71500 1 0 0 lcd-digit.sym
{
T 117500 103555 5 10 0 1 0 0 1
T 52300 68000 5 10 1 1 0 0 1
netname=com_0
}
-N 53600 59900 52300 59900 4
-{
-T 53000 60000 5 10 1 1 0 6 1
-netname=cs_radio
-}
N 74300 77500 74300 78500 4
{
T 73800 78000 5 10 1 1 0 0 1
N 85375 67300 85500 67300 4
N 79525 67300 79500 67300 4
N 76450 67300 76500 67300 4
-C 48300 59500 1 0 0 conn-4.sym
+C 44500 62300 1 0 0 conn-4.sym
{
-T 48600 61100 5 10 1 1 0 0 1
+T 44800 63900 5 10 1 1 0 0 1
refdes=J3
-T 48500 59200 5 10 1 1 0 0 1
+T 44700 62000 5 10 1 1 0 0 1
value=Debug
-T 48300 59500 5 10 0 0 0 0 1
+T 44500 62300 5 10 0 0 0 0 1
footprint=0-215079-4
-T 48300 59500 5 10 0 0 0 0 1
+T 44500 62300 5 10 0 0 0 0 1
vendor_part_number=571-215079-4
-T 48300 59500 5 10 0 0 0 0 1
+T 44500 62300 5 10 0 0 0 0 1
vendor=mouser
-T 48300 59500 5 10 0 0 0 0 1
+T 44500 62300 5 10 0 0 0 0 1
loadstatus=throughhole
-T 48300 59500 5 10 0 0 0 0 1
+T 44500 62300 5 10 0 0 0 0 1
device=CONNECTOR
}
-C 48200 60500 1 0 0 gnd.sym
-N 48300 60400 47000 60400 4
+C 44400 63300 1 0 0 gnd.sym
+N 44500 63200 43200 63200 4
{
-T 47000 60500 5 10 1 1 0 0 1
+T 43200 63300 5 10 1 1 0 0 1
netname=reset_n
}
-N 48300 60000 47000 60000 4
+N 44500 62800 43200 62800 4
{
-T 47000 60100 5 10 1 1 0 0 1
+T 43200 62900 5 10 1 1 0 0 1
netname=swdio
}
-N 48300 59600 47000 59600 4
+N 44500 62400 43200 62400 4
{
-T 47000 59700 5 10 1 1 0 0 1
+T 43200 62500 5 10 1 1 0 0 1
netname=swclk
}
N 47800 50300 44700 50300 4
N 63100 74300 65000 74300 4
N 65000 74300 65000 75100 4
N 65000 75100 65800 75100 4
-C 46500 57800 1 0 0 3.3V-plus.sym
-C 46900 56700 1 90 0 capacitor.sym
+C 42700 60600 1 0 0 3.3V-plus.sym
+C 43100 59500 1 90 0 capacitor.sym
{
-T 46200 56900 5 10 0 0 90 0 1
+T 42400 59700 5 10 0 0 90 0 1
device=CAPACITOR
-T 46400 57400 5 10 1 1 180 0 1
+T 42600 60200 5 10 1 1 180 0 1
refdes=C36
-T 46000 56900 5 10 0 0 90 0 1
+T 42200 59700 5 10 0 0 90 0 1
symversion=0.1
-T 46100 56800 5 10 1 1 0 0 1
+T 42300 59600 5 10 1 1 0 0 1
value=0.1uF
-T 46900 56700 5 10 0 0 0 0 1
+T 43100 59500 5 10 0 0 0 0 1
footprint=0402
-T 46900 56700 5 10 0 0 0 0 1
+T 43100 59500 5 10 0 0 0 0 1
vendor_part_number=399-3027-1-ND
-T 46900 56700 5 10 0 0 0 0 1
+T 43100 59500 5 10 0 0 0 0 1
vendor=digikey
-T 46900 56700 5 10 0 1 0 0 1
+T 43100 59500 5 10 0 1 0 0 1
loadstatus=smt
}
-C 48000 56200 1 0 0 gnd.sym
-C 49100 57000 1 0 1 MCP130T.sym
+C 44200 59000 1 0 0 gnd.sym
+C 45300 59800 1 0 1 MCP130T.sym
{
-T 48805 57995 5 10 1 1 0 6 1
+T 45005 60795 5 10 1 1 0 6 1
refdes=U11
-T 48305 57995 5 10 1 1 0 6 1
+T 44505 60795 5 10 1 1 0 6 1
value=MCP130T-300
-T 49105 56995 5 10 0 1 0 6 1
+T 45305 59795 5 10 0 1 0 6 1
device=IC
-T 48205 57995 5 10 0 1 0 6 1
+T 44405 60795 5 10 0 1 0 6 1
footprint=SOT23
-T 49100 57000 5 10 0 1 0 0 1
+T 45300 59800 5 10 0 1 0 0 1
vendor=digikey
-T 49100 57000 5 10 0 1 0 0 1
+T 45300 59800 5 10 0 1 0 0 1
vendor_part_number=MCP130T-300I/TTCT-ND
-T 49100 57000 5 10 0 1 0 0 1
+T 45300 59800 5 10 0 1 0 0 1
loadstatus=smt
}
-N 46700 57800 46700 57600 4
-N 46700 57700 47100 57700 4
-N 46700 56600 48100 56600 4
-N 48100 56500 48100 57000 4
-N 46700 56600 46700 56700 4
-N 49100 57700 50000 57700 4
+N 42900 60600 42900 60400 4
+N 42900 60500 43300 60500 4
+N 42900 59400 44300 59400 4
+N 44300 59300 44300 59800 4
+N 42900 59400 42900 59500 4
+N 45300 60500 46200 60500 4
{
-T 49400 57800 5 10 1 1 0 0 1
+T 45600 60600 5 10 1 1 0 0 1
netname=reset_n
}
C 79400 45100 1 0 0 CC1111.sym
footprint=100mil3pin.fp
}
C 78000 46600 1 0 0 gnd.sym
+C 52900 57800 1 90 0 capacitor.sym
+{
+T 52200 58000 5 10 0 0 90 0 1
+device=CAPACITOR
+T 52600 58500 5 10 1 1 180 0 1
+refdes=C108
+T 52000 58000 5 10 0 0 90 0 1
+symversion=0.1
+T 52900 57800 5 10 0 0 0 0 1
+footprint=0402
+T 52200 57900 5 10 1 1 0 0 1
+value=47pF
+}
+C 52100 58200 1 90 0 capacitor.sym
+{
+T 51400 58400 5 10 0 0 90 0 1
+device=CAPACITOR
+T 51700 58900 5 10 1 1 180 0 1
+refdes=C107
+T 51200 58400 5 10 0 0 90 0 1
+symversion=0.1
+T 52100 58200 5 10 0 0 0 0 1
+footprint=0402
+T 51300 58300 5 10 1 1 0 0 1
+value=47pF
+}
+C 50400 58600 1 90 0 capacitor.sym
+{
+T 49700 58800 5 10 0 0 90 0 1
+device=CAPACITOR
+T 50100 59300 5 10 1 1 180 0 1
+refdes=C106
+T 49500 58800 5 10 0 0 90 0 1
+symversion=0.1
+T 50400 58600 5 10 0 0 0 0 1
+footprint=0402
+T 49700 58800 5 10 1 1 0 0 1
+value=47pF
+}
+C 49600 59000 1 90 0 capacitor.sym
+{
+T 48900 59200 5 10 0 0 90 0 1
+device=CAPACITOR
+T 49300 59700 5 10 1 1 180 0 1
+refdes=C105
+T 48700 59200 5 10 0 0 90 0 1
+symversion=0.1
+T 49600 59000 5 10 0 0 0 0 1
+footprint=0402
+T 48900 59200 5 10 1 1 0 0 1
+value=47pF
+}
+C 49300 58700 1 0 0 gnd.sym
+C 50100 58300 1 0 0 gnd.sym
+C 51800 57900 1 0 0 gnd.sym
+C 52600 57500 1 0 0 gnd.sym
+C 52700 58600 1 0 0 resistor.sym
+{
+T 53000 59000 5 10 0 0 0 0 1
+device=RESISTOR
+T 52800 58800 5 10 1 1 0 0 1
+refdes=R108
+T 52700 58600 5 10 0 0 0 0 1
+footprint=0402
+T 53300 58800 5 10 1 1 0 0 1
+value=330
+}
+N 52700 58700 52200 58700 4
+{
+T 52200 58800 5 10 1 1 0 0 1
+netname=mosi2
+}
+N 53600 59100 51900 59100 4
+C 51000 59000 1 0 0 resistor.sym
+{
+T 51300 59400 5 10 0 0 0 0 1
+device=RESISTOR
+T 51100 59200 5 10 1 1 0 0 1
+refdes=R107
+T 51000 59000 5 10 0 0 0 0 1
+footprint=0402
+T 51600 59200 5 10 1 1 0 0 1
+value=330
+}
+N 51000 59100 50500 59100 4
+{
+T 50500 59200 5 10 1 1 0 0 1
+netname=miso2
+}
+C 52700 59400 1 0 0 resistor.sym
+{
+T 53000 59800 5 10 0 0 0 0 1
+device=RESISTOR
+T 52600 59600 5 10 1 1 0 0 1
+refdes=R106
+T 52700 59400 5 10 0 0 0 0 1
+footprint=0402
+T 53100 59600 5 10 1 1 0 0 1
+value=330
+}
+C 52700 59800 1 0 0 resistor.sym
+{
+T 53000 60200 5 10 0 0 0 0 1
+device=RESISTOR
+T 52600 60000 5 10 1 1 0 0 1
+refdes=R105
+T 52700 59800 5 10 0 0 0 0 1
+footprint=0402
+T 53100 60000 5 10 1 1 0 0 1
+value=330
+}
+N 52700 59500 49700 59500 4
+{
+T 49700 59600 5 10 1 1 0 0 1
+netname=c2
+}
+N 52700 59900 48900 59900 4
+{
+T 48900 60000 5 10 1 1 0 0 1
+netname=cs_radio
+}
+C 64600 70200 1 90 0 capacitor.sym
+{
+T 63900 70400 5 10 0 0 90 0 1
+device=CAPACITOR
+T 64300 70900 5 10 1 1 180 0 1
+refdes=C109
+T 63700 70400 5 10 0 0 90 0 1
+symversion=0.1
+T 64600 70200 5 10 0 0 0 0 1
+footprint=0402
+T 63900 70400 5 10 1 1 0 0 1
+value=47pF
+}
+C 65300 71200 1 180 0 resistor.sym
+{
+T 65000 70800 5 10 0 0 180 0 1
+device=RESISTOR
+T 65100 71400 5 10 1 1 180 0 1
+refdes=R109
+T 65300 71200 5 10 0 0 0 0 1
+footprint=0402
+T 64700 70800 5 10 1 1 0 0 1
+value=330
+}
+C 64300 69900 1 0 0 gnd.sym
+N 65300 71100 65800 71100 4
+{
+T 65300 70900 5 10 1 1 0 0 1
+netname=radio_int
+}
projects / hw / telelco / commitdiff