add_cflag_if_supported("-fPIC")
if(${CMAKE_BUILD_TYPE} MATCHES "Debug")
- include(CTest)
- add_cflag_if_supported("-ggdb")
- add_cflag_if_supported("-O0")
+ include(CTest)
+ add_cflag_if_supported("-ggdb")
+ add_cflag_if_supported("-O0")
elseif()
- add_cflag_if_supported("-O2")
+ add_cflag_if_supported("-O2")
endif()
-set(STLINK_HEADERS include/stlink.h
- include/stlink/usb.h
- include/stlink/sg.h
- include/stlink/logging.h
- include/stlink/mmap.h
+set(STLINK_HEADERS
+ include/stlink.h
+ include/stlink/usb.h
+ include/stlink/sg.h
+ include/stlink/logging.h
+ include/stlink/mmap.h
+ include/stlink/chipid.h
)
-set(STLINK_SOURCE src/common.c
- src/usb.c
- src/sg.c
- src/logging.c
+set(STLINK_SOURCE
+ src/chipid.c
+ src/common.c
+ src/usb.c
+ src/sg.c
+ src/logging.c
)
include_directories(${LIBUSB_INCLUDE_DIR})
st_util_SOURCES = src/gdbserver/gdb-remote.c src/gdbserver/gdb-remote.h src/gdbserver/gdb-server.c src/mingw/mingw.c src/mingw/mingw.h
CFILES = \
+ src/chipid.c \
src/common.c \
src/usb.c \
src/sg.c \
HFILES = \
include/stlink.h \
+ include/stlink/chipid.h \
include/stlink/usb.h \
include/stlink/sg.h \
include/stlink/logging.h \
#define STLINK_H
#include <stdint.h>
+#include <stddef.h>
#ifdef __cplusplus
extern "C" {
#endif
+
+#define STLINK_ARRAY_SIZE(x) (sizeof(x)/sizeof(x[0]))
+
// Max data transfer size.
// 6kB = max mem32_read block, 8kB sram
//#define Q_BUF_LEN 96
#define CORE_M3_R2 0x4BA00477
#define CORE_M4_R0 0x2BA01477
- /*
- * Chip IDs are explained in the appropriate programming manual for the
- * DBGMCU_IDCODE register (0xE0042000)
- */
- // stm32 chipids, only lower 12 bits..
-#define STM32_CHIPID_F1_MEDIUM 0x410
-#define STM32_CHIPID_F2 0x411
-#define STM32_CHIPID_F1_LOW 0x412
-#define STM32_CHIPID_F4 0x413
-#define STM32_CHIPID_F1_HIGH 0x414
-#define STM32_CHIPID_L4 0x415 /* Seen on L4x6 (RM0351) */
-#define STM32_CHIPID_L1_MEDIUM 0x416
-#define STM32_CHIPID_L0 0x417
-#define STM32_CHIPID_F1_CONN 0x418
-#define STM32_CHIPID_F4_HD 0x419
-#define STM32_CHIPID_F1_VL_MEDIUM_LOW 0x420
-
-#define STM32_CHIPID_F446 0x421
-#define STM32_CHIPID_F3 0x422
-#define STM32_CHIPID_F4_LP 0x423
-
-#define STM32_CHIPID_F411RE 0x431
-
-#define STM32_CHIPID_L1_MEDIUM_PLUS 0x427
-#define STM32_CHIPID_F1_VL_HIGH 0x428
-#define STM32_CHIPID_L1_CAT2 0x429
-
-#define STM32_CHIPID_F1_XL 0x430
-
-#define STM32_CHIPID_F37x 0x432
-#define STM32_CHIPID_F4_DE 0x433
-#define STM32_CHIPID_F4_DE 0x433
-
-#define STM32_CHIPID_F4_DSI 0x434
-
-#define STM32_CHIPID_L1_HIGH 0x436
-#define STM32_CHIPID_L152_RE 0x437
-#define STM32_CHIPID_F334 0x438
-
-#define STM32_CHIPID_F3_SMALL 0x439
-#define STM32_CHIPID_F0 0x440
-#define STM32_CHIPID_F09X 0x442
-#define STM32_CHIPID_F0_SMALL 0x444
-
-#define STM32_CHIPID_F04 0x445
-
-#define STM32_CHIPID_F303_HIGH 0x446
-#define STM32_CHIPID_L0_CAT5 0x447
-#define STM32_CHIPID_L0_CAT2 0x425
-
-#define STM32_CHIPID_F0_CAN 0x448
-
-#define STM32_CHIPID_F7 0x449
-
- /*
- * 0x436 is actually assigned to some L1 chips that are called "Medium-Plus"
- * and some that are called "High". 0x427 is assigned to the other "Medium-
- * plus" chips. To make it a bit simpler we just call 427 MEDIUM_PLUS and
- * 0x436 HIGH.
- */
-
// Constant STM32 memory map figures
#define STM32_FLASH_BASE 0x08000000
#define STM32_SRAM_BASE 0x20000000
FLASH_TYPE_L4,
};
- typedef struct chip_params_ {
- uint32_t chip_id;
- char* description;
- enum flash_type flash_type;
- uint32_t flash_size_reg;
- uint32_t flash_pagesize;
- uint32_t sram_size;
- uint32_t bootrom_base, bootrom_size;
- } chip_params_t;
-
-
- // These maps are from a combination of the Programming Manuals, and
- // also the Reference manuals. (flash size reg is normally in ref man)
- static const chip_params_t devices[] = {
- {
- //RM0385 and DS10916 document was used to find these paramaters
- .chip_id = STM32_CHIPID_F7,
- .description = "F7 device",
- .flash_type = FLASH_TYPE_F4,
- .flash_size_reg = 0x1ff0f442, // section 41.2
- .flash_pagesize = 0x800, // No flash pages
- .sram_size = 0x50000, // "SRAM" byte size in hex from DS Fig 18
- .bootrom_base = 0x00100000, // "System memory" starting address from DS Fig 18
- .bootrom_size = 0xEDC0 // "System memory" byte size in hex from DS Fig 18
- },
- { // table 2, PM0063
- .chip_id = STM32_CHIPID_F1_MEDIUM,
- .description = "F1 Medium-density device",
- .flash_type = FLASH_TYPE_F0,
- .flash_size_reg = 0x1ffff7e0,
- .flash_pagesize = 0x400,
- .sram_size = 0x5000,
- .bootrom_base = 0x1ffff000,
- .bootrom_size = 0x800
- },
- { // table 1, PM0059
- .chip_id = STM32_CHIPID_F2,
- .description = "F2 device",
- .flash_type = FLASH_TYPE_F4,
- .flash_size_reg = 0x1fff7a22, /* As in RM0033 Rev 5*/
- .flash_pagesize = 0x20000,
- .sram_size = 0x20000,
- .bootrom_base = 0x1fff0000,
- .bootrom_size = 0x7800
- },
- { // PM0063
- .chip_id = STM32_CHIPID_F1_LOW,
- .description = "F1 Low-density device",
- .flash_type = FLASH_TYPE_F0,
- .flash_size_reg = 0x1ffff7e0,
- .flash_pagesize = 0x400,
- .sram_size = 0x2800,
- .bootrom_base = 0x1ffff000,
- .bootrom_size = 0x800
- },
- {
- .chip_id = STM32_CHIPID_F4,
- .description = "F4 device",
- .flash_type = FLASH_TYPE_F4,
- .flash_size_reg = 0x1FFF7A22, /* As in rm0090 since Rev 2*/
- .flash_pagesize = 0x4000,
- .sram_size = 0x30000,
- .bootrom_base = 0x1fff0000,
- .bootrom_size = 0x7800
- },
- {
- .chip_id = STM32_CHIPID_F4_DSI,
- .description = "F46x and F47x device",
- .flash_type = FLASH_TYPE_F4,
- .flash_size_reg = 0x1FFF7A22, /* As in rm0090 since Rev 2*/
- .flash_pagesize = 0x4000,
- .sram_size = 0x40000,
- .bootrom_base = 0x1fff0000,
- .bootrom_size = 0x7800
- },
- {
- .chip_id = STM32_CHIPID_F4_HD,
- .description = "F42x and F43x device",
- .flash_type = FLASH_TYPE_F4,
- .flash_size_reg = 0x1FFF7A22, /* As in rm0090 since Rev 2*/
- .flash_pagesize = 0x4000,
- .sram_size = 0x40000,
- .bootrom_base = 0x1fff0000,
- .bootrom_size = 0x7800
- },
- {
- .chip_id = STM32_CHIPID_F4_LP,
- .description = "F4 device (low power)",
- .flash_type = FLASH_TYPE_F4,
- .flash_size_reg = 0x1FFF7A22,
- .flash_pagesize = 0x4000,
- .sram_size = 0x10000,
- .bootrom_base = 0x1fff0000,
- .bootrom_size = 0x7800
- },
- {
- .chip_id = STM32_CHIPID_F411RE,
- .description = "F4 device (low power) - stm32f411re",
- .flash_type = FLASH_TYPE_F4,
- .flash_size_reg = 0x1FFF7A22,
- .flash_pagesize = 0x4000,
- .sram_size = 0x20000,
- .bootrom_base = 0x1fff0000,
- .bootrom_size = 0x7800
- },
- {
- .chip_id = STM32_CHIPID_F4_DE,
- .description = "F4 device (Dynamic Efficency)",
- .flash_type = FLASH_TYPE_F4,
- .flash_size_reg = 0x1FFF7A22,
- .flash_pagesize = 0x4000,
- .sram_size = 0x18000,
- .bootrom_base = 0x1fff0000,
- .bootrom_size = 0x7800
- },
- {
- .chip_id = STM32_CHIPID_F1_HIGH,
- .description = "F1 High-density device",
- .flash_type = FLASH_TYPE_F0,
- .flash_size_reg = 0x1ffff7e0,
- .flash_pagesize = 0x800,
- .sram_size = 0x10000,
- .bootrom_base = 0x1ffff000,
- .bootrom_size = 0x800
- },
- {
- // This ignores the EEPROM! (and uses the page erase size,
- // not the sector write protection...)
- .chip_id = STM32_CHIPID_L1_MEDIUM,
- .description = "L1 Med-density device",
- .flash_type = FLASH_TYPE_L0,
- .flash_size_reg = 0x1ff8004c,
- .flash_pagesize = 0x100,
- .sram_size = 0x4000,
- .bootrom_base = 0x1ff00000,
- .bootrom_size = 0x1000
- },
- {
- .chip_id = STM32_CHIPID_L1_CAT2,
- .description = "L1 Cat.2 device",
- .flash_type = FLASH_TYPE_L0,
- .flash_size_reg = 0x1ff8004c,
- .flash_pagesize = 0x100,
- .sram_size = 0x8000,
- .bootrom_base = 0x1ff00000,
- .bootrom_size = 0x1000
- },
- {
- .chip_id = STM32_CHIPID_L1_MEDIUM_PLUS,
- .description = "L1 Medium-Plus-density device",
- .flash_type = FLASH_TYPE_L0,
- .flash_size_reg = 0x1ff800cc,
- .flash_pagesize = 0x100,
- .sram_size = 0x8000,/*Not completely clear if there are some with 48K*/
- .bootrom_base = 0x1ff00000,
- .bootrom_size = 0x1000
- },
- {
- .chip_id = STM32_CHIPID_L1_HIGH,
- .description = "L1 High-density device",
- .flash_type = FLASH_TYPE_L0,
- .flash_size_reg = 0x1ff800cc,
- .flash_pagesize = 0x100,
- .sram_size = 0xC000, /*Not completely clear if there are some with 32K*/
- .bootrom_base = 0x1ff00000,
- .bootrom_size = 0x1000
- },
- {
- .chip_id = STM32_CHIPID_L152_RE,
- .description = "L152RE",
- .flash_type = FLASH_TYPE_L0,
- .flash_size_reg = 0x1ff800cc,
- .flash_pagesize = 0x100,
- .sram_size = 0x14000, /*Not completely clear if there are some with 32K*/
- .bootrom_base = 0x1ff00000,
- .bootrom_size = 0x1000
- },
- {
- .chip_id = STM32_CHIPID_F1_CONN,
- .description = "F1 Connectivity line device",
- .flash_type = FLASH_TYPE_F0,
- .flash_size_reg = 0x1ffff7e0,
- .flash_pagesize = 0x800,
- .sram_size = 0x10000,
- .bootrom_base = 0x1fffb000,
- .bootrom_size = 0x4800
- },
- {//Low and Medium density VL have same chipid. RM0041 25.6.1
- .chip_id = STM32_CHIPID_F1_VL_MEDIUM_LOW,
- .description = "F1 Medium/Low-density Value Line device",
- .flash_type = FLASH_TYPE_F0,
- .flash_size_reg = 0x1ffff7e0,
- .flash_pagesize = 0x400,
- .sram_size = 0x2000,//0x1000 for low density devices
- .bootrom_base = 0x1ffff000,
- .bootrom_size = 0x800
- },
- {
- // STM32F446x family. Support based on DM00135183.pdf (RM0390) document.
- .chip_id = STM32_CHIPID_F446,
- .description = "F446 device",
- .flash_type = FLASH_TYPE_F4,
- .flash_size_reg = 0x1fff7a22,
- .flash_pagesize = 0x20000,
- .sram_size = 0x20000,
- .bootrom_base = 0x1fff0000,
- .bootrom_size = 0x7800
- },
- {
- // This is STK32F303VCT6 device from STM32 F3 Discovery board.
- // Support based on DM00043574.pdf (RM0316) document.
- .chip_id = STM32_CHIPID_F3,
- .description = "F3 device",
- .flash_type = FLASH_TYPE_F0,
- .flash_size_reg = 0x1ffff7cc,
- .flash_pagesize = 0x800,
- .sram_size = 0xa000,
- .bootrom_base = 0x1ffff000,
- .bootrom_size = 0x800
- },
- {
- // This is STK32F373VCT6 device from STM32 F373 eval board
- // Support based on 303 above (37x and 30x have same memory map)
- .chip_id = STM32_CHIPID_F37x,
- .description = "F3 device",
- .flash_type = FLASH_TYPE_F0,
- .flash_size_reg = 0x1ffff7cc,
- .flash_pagesize = 0x800,
- .sram_size = 0xa000,
- .bootrom_base = 0x1ffff000,
- .bootrom_size = 0x800
- },
- {
- .chip_id = STM32_CHIPID_F1_VL_HIGH,
- .description = "F1 High-density value line device",
- .flash_type = FLASH_TYPE_F0,
- .flash_size_reg = 0x1ffff7e0,
- .flash_pagesize = 0x800,
- .sram_size = 0x8000,
- .bootrom_base = 0x1ffff000,
- .bootrom_size = 0x800
- },
- {
- .chip_id = STM32_CHIPID_F1_XL,
- .description = "F1 XL-density device",
- .flash_type = FLASH_TYPE_F0,
- .flash_size_reg = 0x1ffff7e0,
- .flash_pagesize = 0x800,
- .sram_size = 0x18000,
- .bootrom_base = 0x1fffe000,
- .bootrom_size = 0x1800
- },
- {
- //Use this as an example for mapping future chips:
- //RM0091 document was used to find these paramaters
- .chip_id = STM32_CHIPID_F0_CAN,
- .description = "F07x device",
- .flash_type = FLASH_TYPE_F0,
- .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735)
- .flash_pagesize = 0x800, // Page sizes listed in Table 4
- .sram_size = 0x4000, // "SRAM" byte size in hex from Table 2
- .bootrom_base = 0x1fffC800, // "System memory" starting address from Table 2
- .bootrom_size = 0x3000 // "System memory" byte size in hex from Table 2
- },
- {
- //Use this as an example for mapping future chips:
- //RM0091 document was used to find these paramaters
- .chip_id = STM32_CHIPID_F0,
- .description = "F0 device",
- .flash_type = FLASH_TYPE_F0,
- .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735)
- .flash_pagesize = 0x400, // Page sizes listed in Table 4
- .sram_size = 0x2000, // "SRAM" byte size in hex from Table 2
- .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2
- .bootrom_size = 0xC00 // "System memory" byte size in hex from Table 2
- },
- {
- .chip_id = STM32_CHIPID_F09X,
- .description = "F09X device",
- .flash_type = FLASH_TYPE_F0,
- .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735)
- .flash_pagesize = 0x800, // Page sizes listed in Table 4 (pg 56)
- .sram_size = 0x8000, // "SRAM" byte size in hex from Table 2 (pg 50)
- .bootrom_base = 0x1fffd800, // "System memory" starting address from Table 2
- .bootrom_size = 0x2000 // "System memory" byte size in hex from Table 2
- },
- {
- //Use this as an example for mapping future chips:
- //RM0091 document was used to find these paramaters
- .chip_id = STM32_CHIPID_F04,
- .description = "F04x device",
- .flash_type = FLASH_TYPE_F0,
- .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735)
- .flash_pagesize = 0x400, // Page sizes listed in Table 4
- .sram_size = 0x1800, // "SRAM" byte size in hex from Table 2
- .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2
- .bootrom_size = 0xC00 // "System memory" byte size in hex from Table 2
- },
- {
- //Use this as an example for mapping future chips:
- //RM0091 document was used to find these paramaters
- .chip_id = STM32_CHIPID_F0_SMALL,
- .description = "F0 small device",
- .flash_type = FLASH_TYPE_F0,
- .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735)
- .flash_pagesize = 0x400, // Page sizes listed in Table 4
- .sram_size = 0x1000, // "SRAM" byte size in hex from Table 2
- .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2
- .bootrom_size = 0xC00 // "System memory" byte size in hex from Table 2
- },
- {
- // STM32F30x
- .chip_id = STM32_CHIPID_F3_SMALL,
- .description = "F3 small device",
- .flash_type = FLASH_TYPE_F0,
- .flash_size_reg = 0x1ffff7cc,
- .flash_pagesize = 0x800,
- .sram_size = 0xa000,
- .bootrom_base = 0x1fffd800,
- .bootrom_size = 0x2000
- },
- {
- // STM32L0x
- // RM0367,RM0377 documents was used to find these parameters
- .chip_id = STM32_CHIPID_L0,
- .description = "L0x3 device",
- .flash_type = FLASH_TYPE_L0,
- .flash_size_reg = 0x1ff8007c,
- .flash_pagesize = 0x80,
- .sram_size = 0x2000,
- .bootrom_base = 0x1ff0000,
- .bootrom_size = 0x1000
- },
- {
- // STM32L0x Category 5
- // RM0367,RM0377 documents was used to find these parameters
- .chip_id = STM32_CHIPID_L0_CAT5,
- .description = "L0x Category 5 device",
- .flash_type = FLASH_TYPE_L0,
- .flash_size_reg = 0x1ff8007c,
- .flash_pagesize = 0x80,
- .sram_size = 0x5000,
- .bootrom_base = 0x1ff0000,
- .bootrom_size = 0x2000
- },
- {
- // STM32L0x Category 2
- // RM0367,RM0377 documents was used to find these parameters
- .chip_id = STM32_CHIPID_L0_CAT2,
- .description = "L0x Category 2 device",
- .flash_type = FLASH_TYPE_L0,
- .flash_size_reg = 0x1ff8007c,
- .flash_pagesize = 0x80,
- .sram_size = 0x2000,
- .bootrom_base = 0x1ff0000,
- .bootrom_size = 0x1000
- },
- {
- // STM32F334
- // RM0364 document was used to find these parameters
- .chip_id = STM32_CHIPID_F334,
- .description = "F334 device",
- .flash_type = FLASH_TYPE_F0,
- .flash_size_reg = 0x1ffff7cc,
- .flash_pagesize = 0x800,
- .sram_size = 0x3000,
- .bootrom_base = 0x1fffd800,
- .bootrom_size = 0x2000
- },
- {
- // This is STK32F303RET6 device from STM32 F3 Nucelo board.
- // Support based on DM00043574.pdf (RM0316) document rev 5.
- .chip_id = STM32_CHIPID_F303_HIGH,
- .description = "F303 high density device",
- .flash_type = FLASH_TYPE_F0,
- .flash_size_reg = 0x1ffff7cc, // 34.2.1 Flash size data register
- .flash_pagesize = 0x800, // 4.2.1 Flash memory organization
- .sram_size = 0x10000, // 3.3 Embedded SRAM
- .bootrom_base = 0x1fffd800, // 3.3.2 / Table 4 System Memory
- .bootrom_size = 0x2000
- },
- {
- // STM32L4x6
- // From RM0351.
- .chip_id = STM32_CHIPID_L4,
- .description = "L4 device",
- .flash_type = FLASH_TYPE_L4,
- .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 45.2, page 1671)
- .flash_pagesize = 0x800, // 2K (sec 3.2, page 78; also appears in sec 3.3.1 and tables 4-6 on pages 79-81)
- // SRAM1 is "up to" 96k in the standard Cortex-M memory map;
- // SRAM2 is 32k mapped at at 0x10000000 (sec 2.3, page 73 for
- // sizes; table 2, page 74 for SRAM2 location)
- .sram_size = 0x18000,
- .bootrom_base = 0x1fff0000, // Tables 4-6, pages 80-81 (Bank 1 system memory)
- .bootrom_size = 0x7000 // 28k (per bank), same source as base
- },
-
- };
-
+#include "stlink/chipid.h"
typedef struct {
uint32_t r[16];
--- /dev/null
+#ifndef STLINK_CHIPID_H_
+#define STLINK_CHIPID_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * Chip IDs are explained in the appropriate programming manual for the
+ * DBGMCU_IDCODE register (0xE0042000)
+ * stm32 chipids, only lower 12 bits..
+ */
+enum stlink_stm32_chipids {
+ STLINK_CHIPID_STM32_F1_MEDIUM = 0x410,
+ STLINK_CHIPID_STM32_F2 = 0x411,
+ STLINK_CHIPID_STM32_F1_LOW = 0x412,
+ STLINK_CHIPID_STM32_F4 = 0x413,
+ STLINK_CHIPID_STM32_F1_HIGH = 0x414,
+ STLINK_CHIPID_STM32_L4 = 0x415,
+ STLINK_CHIPID_STM32_L1_MEDIUM = 0x416,
+ STLINK_CHIPID_STM32_L0 = 0x417,
+ STLINK_CHIPID_STM32_F1_CONN = 0x418,
+ STLINK_CHIPID_STM32_F4_HD = 0x419,
+ STLINK_CHIPID_STM32_F1_VL_MEDIUM_LOW = 0x420,
+ STLINK_CHIPID_STM32_F446 = 0x421,
+ STLINK_CHIPID_STM32_F3 = 0x422,
+ STLINK_CHIPID_STM32_F4_LP = 0x423,
+ STLINK_CHIPID_STM32_L0_CAT2 = 0x425,
+ STLINK_CHIPID_STM32_L1_MEDIUM_PLUS = 0x427,
+ STLINK_CHIPID_STM32_F1_VL_HIGH = 0x428,
+ STLINK_CHIPID_STM32_L1_CAT2 = 0x429,
+ STLINK_CHIPID_STM32_F1_XL = 0x430,
+ STLINK_CHIPID_STM32_F411RE = 0x431,
+ STLINK_CHIPID_STM32_F37x = 0x432,
+ STLINK_CHIPID_STM32_F4_DE = 0x433,
+ STLINK_CHIPID_STM32_F4_DSI = 0x434,
+ /*
+ * 0x436 is actually assigned to some L1 chips that are called "Medium-Plus"
+ * and some that are called "High". 0x427 is assigned to the other "Medium-
+ * plus" chips. To make it a bit simpler we just call 427 MEDIUM_PLUS and
+ * 0x436 HIGH.
+ */
+ STLINK_CHIPID_STM32_L1_HIGH = 0x436,
+ STLINK_CHIPID_STM32_L152_RE = 0x437,
+ STLINK_CHIPID_STM32_F334 = 0x438,
+ STLINK_CHIPID_STM32_F3_SMALL = 0x439,
+ STLINK_CHIPID_STM32_F0 = 0x440,
+ STLINK_CHIPID_STM32_F09X = 0x442,
+ STLINK_CHIPID_STM32_F0_SMALL = 0x444,
+ STLINK_CHIPID_STM32_F04 = 0x445,
+ STLINK_CHIPID_STM32_F303_HIGH = 0x446,
+ STLINK_CHIPID_STM32_L0_CAT5 = 0x447,
+ STLINK_CHIPID_STM32_F0_CAN = 0x448,
+ STLINK_CHIPID_STM32_F7 = 0x449
+};
+
+/**
+ * Chipid parameters
+ */
+struct stlink_chipid_params {
+ uint32_t chip_id;
+ char *description;
+ enum flash_type flash_type;
+ uint32_t flash_size_reg;
+ uint32_t flash_pagesize;
+ uint32_t sram_size;
+ uint32_t bootrom_base;
+ uint32_t bootrom_size;
+};
+
+const struct stlink_chipid_params *stlink_chipid_get_params(uint32_t chipid);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STLINK_CHIPID_H_ */
--- /dev/null
+#include "stlink.h"
+#include "stlink/chipid.h"
+
+static const struct stlink_chipid_params devices[] = {
+ {
+ //RM0385 and DS10916 document was used to find these paramaters
+ .chip_id = STLINK_CHIPID_STM32_F7,
+ .description = "F7 device",
+ .flash_type = FLASH_TYPE_F4,
+ .flash_size_reg = 0x1ff0f442, // section 41.2
+ .flash_pagesize = 0x800, // No flash pages
+ .sram_size = 0x50000, // "SRAM" byte size in hex from DS Fig 18
+ .bootrom_base = 0x00100000, // "System memory" starting address from DS Fig 18
+ .bootrom_size = 0xEDC0 // "System memory" byte size in hex from DS Fig 18
+ },
+ { // table 2, PM0063
+ .chip_id = STLINK_CHIPID_STM32_F1_MEDIUM,
+ .description = "F1 Medium-density device",
+ .flash_type = FLASH_TYPE_F0,
+ .flash_size_reg = 0x1ffff7e0,
+ .flash_pagesize = 0x400,
+ .sram_size = 0x5000,
+ .bootrom_base = 0x1ffff000,
+ .bootrom_size = 0x800
+ },
+ { // table 1, PM0059
+ .chip_id = STLINK_CHIPID_STM32_F2,
+ .description = "F2 device",
+ .flash_type = FLASH_TYPE_F4,
+ .flash_size_reg = 0x1fff7a22, /* As in RM0033 Rev 5*/
+ .flash_pagesize = 0x20000,
+ .sram_size = 0x20000,
+ .bootrom_base = 0x1fff0000,
+ .bootrom_size = 0x7800
+ },
+ { // PM0063
+ .chip_id = STLINK_CHIPID_STM32_F1_LOW,
+ .description = "F1 Low-density device",
+ .flash_type = FLASH_TYPE_F0,
+ .flash_size_reg = 0x1ffff7e0,
+ .flash_pagesize = 0x400,
+ .sram_size = 0x2800,
+ .bootrom_base = 0x1ffff000,
+ .bootrom_size = 0x800
+ },
+ {
+ .chip_id = STLINK_CHIPID_STM32_F4,
+ .description = "F4 device",
+ .flash_type = FLASH_TYPE_F4,
+ .flash_size_reg = 0x1FFF7A22, /* As in rm0090 since Rev 2*/
+ .flash_pagesize = 0x4000,
+ .sram_size = 0x30000,
+ .bootrom_base = 0x1fff0000,
+ .bootrom_size = 0x7800
+ },
+ {
+ .chip_id = STLINK_CHIPID_STM32_F4_DSI,
+ .description = "F46x and F47x device",
+ .flash_type = FLASH_TYPE_F4,
+ .flash_size_reg = 0x1FFF7A22, /* As in rm0090 since Rev 2*/
+ .flash_pagesize = 0x4000,
+ .sram_size = 0x40000,
+ .bootrom_base = 0x1fff0000,
+ .bootrom_size = 0x7800
+ },
+ {
+ .chip_id = STLINK_CHIPID_STM32_F4_HD,
+ .description = "F42x and F43x device",
+ .flash_type = FLASH_TYPE_F4,
+ .flash_size_reg = 0x1FFF7A22, /* As in rm0090 since Rev 2*/
+ .flash_pagesize = 0x4000,
+ .sram_size = 0x40000,
+ .bootrom_base = 0x1fff0000,
+ .bootrom_size = 0x7800
+ },
+ {
+ .chip_id = STLINK_CHIPID_STM32_F4_LP,
+ .description = "F4 device (low power)",
+ .flash_type = FLASH_TYPE_F4,
+ .flash_size_reg = 0x1FFF7A22,
+ .flash_pagesize = 0x4000,
+ .sram_size = 0x10000,
+ .bootrom_base = 0x1fff0000,
+ .bootrom_size = 0x7800
+ },
+ {
+ .chip_id = STLINK_CHIPID_STM32_F411RE,
+ .description = "F4 device (low power) - stm32f411re",
+ .flash_type = FLASH_TYPE_F4,
+ .flash_size_reg = 0x1FFF7A22,
+ .flash_pagesize = 0x4000,
+ .sram_size = 0x20000,
+ .bootrom_base = 0x1fff0000,
+ .bootrom_size = 0x7800
+ },
+ {
+ .chip_id = STLINK_CHIPID_STM32_F4_DE,
+ .description = "F4 device (Dynamic Efficency)",
+ .flash_type = FLASH_TYPE_F4,
+ .flash_size_reg = 0x1FFF7A22,
+ .flash_pagesize = 0x4000,
+ .sram_size = 0x18000,
+ .bootrom_base = 0x1fff0000,
+ .bootrom_size = 0x7800
+ },
+ {
+ .chip_id = STLINK_CHIPID_STM32_F1_HIGH,
+ .description = "F1 High-density device",
+ .flash_type = FLASH_TYPE_F0,
+ .flash_size_reg = 0x1ffff7e0,
+ .flash_pagesize = 0x800,
+ .sram_size = 0x10000,
+ .bootrom_base = 0x1ffff000,
+ .bootrom_size = 0x800
+ },
+ {
+ // This ignores the EEPROM! (and uses the page erase size,
+ // not the sector write protection...)
+ .chip_id = STLINK_CHIPID_STM32_L1_MEDIUM,
+ .description = "L1 Med-density device",
+ .flash_type = FLASH_TYPE_L0,
+ .flash_size_reg = 0x1ff8004c,
+ .flash_pagesize = 0x100,
+ .sram_size = 0x4000,
+ .bootrom_base = 0x1ff00000,
+ .bootrom_size = 0x1000
+ },
+ {
+ .chip_id = STLINK_CHIPID_STM32_L1_CAT2,
+ .description = "L1 Cat.2 device",
+ .flash_type = FLASH_TYPE_L0,
+ .flash_size_reg = 0x1ff8004c,
+ .flash_pagesize = 0x100,
+ .sram_size = 0x8000,
+ .bootrom_base = 0x1ff00000,
+ .bootrom_size = 0x1000
+ },
+ {
+ .chip_id = STLINK_CHIPID_STM32_L1_MEDIUM_PLUS,
+ .description = "L1 Medium-Plus-density device",
+ .flash_type = FLASH_TYPE_L0,
+ .flash_size_reg = 0x1ff800cc,
+ .flash_pagesize = 0x100,
+ .sram_size = 0x8000,/*Not completely clear if there are some with 48K*/
+ .bootrom_base = 0x1ff00000,
+ .bootrom_size = 0x1000
+ },
+ {
+ .chip_id = STLINK_CHIPID_STM32_L1_HIGH,
+ .description = "L1 High-density device",
+ .flash_type = FLASH_TYPE_L0,
+ .flash_size_reg = 0x1ff800cc,
+ .flash_pagesize = 0x100,
+ .sram_size = 0xC000, /*Not completely clear if there are some with 32K*/
+ .bootrom_base = 0x1ff00000,
+ .bootrom_size = 0x1000
+ },
+ {
+ .chip_id = STLINK_CHIPID_STM32_L152_RE,
+ .description = "L152RE",
+ .flash_type = FLASH_TYPE_L0,
+ .flash_size_reg = 0x1ff800cc,
+ .flash_pagesize = 0x100,
+ .sram_size = 0x14000, /*Not completely clear if there are some with 32K*/
+ .bootrom_base = 0x1ff00000,
+ .bootrom_size = 0x1000
+ },
+ {
+ .chip_id = STLINK_CHIPID_STM32_F1_CONN,
+ .description = "F1 Connectivity line device",
+ .flash_type = FLASH_TYPE_F0,
+ .flash_size_reg = 0x1ffff7e0,
+ .flash_pagesize = 0x800,
+ .sram_size = 0x10000,
+ .bootrom_base = 0x1fffb000,
+ .bootrom_size = 0x4800
+ },
+ {//Low and Medium density VL have same chipid. RM0041 25.6.1
+ .chip_id = STLINK_CHIPID_STM32_F1_VL_MEDIUM_LOW,
+ .description = "F1 Medium/Low-density Value Line device",
+ .flash_type = FLASH_TYPE_F0,
+ .flash_size_reg = 0x1ffff7e0,
+ .flash_pagesize = 0x400,
+ .sram_size = 0x2000,//0x1000 for low density devices
+ .bootrom_base = 0x1ffff000,
+ .bootrom_size = 0x800
+ },
+ {
+ // STM32F446x family. Support based on DM00135183.pdf (RM0390) document.
+ .chip_id = STLINK_CHIPID_STM32_F446,
+ .description = "F446 device",
+ .flash_type = FLASH_TYPE_F4,
+ .flash_size_reg = 0x1fff7a22,
+ .flash_pagesize = 0x20000,
+ .sram_size = 0x20000,
+ .bootrom_base = 0x1fff0000,
+ .bootrom_size = 0x7800
+ },
+ {
+ // This is STK32F303VCT6 device from STM32 F3 Discovery board.
+ // Support based on DM00043574.pdf (RM0316) document.
+ .chip_id = STLINK_CHIPID_STM32_F3,
+ .description = "F3 device",
+ .flash_type = FLASH_TYPE_F0,
+ .flash_size_reg = 0x1ffff7cc,
+ .flash_pagesize = 0x800,
+ .sram_size = 0xa000,
+ .bootrom_base = 0x1ffff000,
+ .bootrom_size = 0x800
+ },
+ {
+ // This is STK32F373VCT6 device from STM32 F373 eval board
+ // Support based on 303 above (37x and 30x have same memory map)
+ .chip_id = STLINK_CHIPID_STM32_F37x,
+ .description = "F3 device",
+ .flash_type = FLASH_TYPE_F0,
+ .flash_size_reg = 0x1ffff7cc,
+ .flash_pagesize = 0x800,
+ .sram_size = 0xa000,
+ .bootrom_base = 0x1ffff000,
+ .bootrom_size = 0x800
+ },
+ {
+ .chip_id = STLINK_CHIPID_STM32_F1_VL_HIGH,
+ .description = "F1 High-density value line device",
+ .flash_type = FLASH_TYPE_F0,
+ .flash_size_reg = 0x1ffff7e0,
+ .flash_pagesize = 0x800,
+ .sram_size = 0x8000,
+ .bootrom_base = 0x1ffff000,
+ .bootrom_size = 0x800
+ },
+ {
+ .chip_id = STLINK_CHIPID_STM32_F1_XL,
+ .description = "F1 XL-density device",
+ .flash_type = FLASH_TYPE_F0,
+ .flash_size_reg = 0x1ffff7e0,
+ .flash_pagesize = 0x800,
+ .sram_size = 0x18000,
+ .bootrom_base = 0x1fffe000,
+ .bootrom_size = 0x1800
+ },
+ {
+ //Use this as an example for mapping future chips:
+ //RM0091 document was used to find these paramaters
+ .chip_id = STLINK_CHIPID_STM32_F0_CAN,
+ .description = "F07x device",
+ .flash_type = FLASH_TYPE_F0,
+ .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735)
+ .flash_pagesize = 0x800, // Page sizes listed in Table 4
+ .sram_size = 0x4000, // "SRAM" byte size in hex from Table 2
+ .bootrom_base = 0x1fffC800, // "System memory" starting address from Table 2
+ .bootrom_size = 0x3000 // "System memory" byte size in hex from Table 2
+ },
+ {
+ //Use this as an example for mapping future chips:
+ //RM0091 document was used to find these paramaters
+ .chip_id = STLINK_CHIPID_STM32_F0,
+ .description = "F0 device",
+ .flash_type = FLASH_TYPE_F0,
+ .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735)
+ .flash_pagesize = 0x400, // Page sizes listed in Table 4
+ .sram_size = 0x2000, // "SRAM" byte size in hex from Table 2
+ .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2
+ .bootrom_size = 0xC00 // "System memory" byte size in hex from Table 2
+ },
+ {
+ .chip_id = STLINK_CHIPID_STM32_F09X,
+ .description = "F09X device",
+ .flash_type = FLASH_TYPE_F0,
+ .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735)
+ .flash_pagesize = 0x800, // Page sizes listed in Table 4 (pg 56)
+ .sram_size = 0x8000, // "SRAM" byte size in hex from Table 2 (pg 50)
+ .bootrom_base = 0x1fffd800, // "System memory" starting address from Table 2
+ .bootrom_size = 0x2000 // "System memory" byte size in hex from Table 2
+ },
+ {
+ //Use this as an example for mapping future chips:
+ //RM0091 document was used to find these paramaters
+ .chip_id = STLINK_CHIPID_STM32_F04,
+ .description = "F04x device",
+ .flash_type = FLASH_TYPE_F0,
+ .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735)
+ .flash_pagesize = 0x400, // Page sizes listed in Table 4
+ .sram_size = 0x1800, // "SRAM" byte size in hex from Table 2
+ .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2
+ .bootrom_size = 0xC00 // "System memory" byte size in hex from Table 2
+ },
+ {
+ //Use this as an example for mapping future chips:
+ //RM0091 document was used to find these paramaters
+ .chip_id = STLINK_CHIPID_STM32_F0_SMALL,
+ .description = "F0 small device",
+ .flash_type = FLASH_TYPE_F0,
+ .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735)
+ .flash_pagesize = 0x400, // Page sizes listed in Table 4
+ .sram_size = 0x1000, // "SRAM" byte size in hex from Table 2
+ .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2
+ .bootrom_size = 0xC00 // "System memory" byte size in hex from Table 2
+ },
+ {
+ // STM32F30x
+ .chip_id = STLINK_CHIPID_STM32_F3_SMALL,
+ .description = "F3 small device",
+ .flash_type = FLASH_TYPE_F0,
+ .flash_size_reg = 0x1ffff7cc,
+ .flash_pagesize = 0x800,
+ .sram_size = 0xa000,
+ .bootrom_base = 0x1fffd800,
+ .bootrom_size = 0x2000
+ },
+ {
+ // STM32L0x
+ // RM0367,RM0377 documents was used to find these parameters
+ .chip_id = STLINK_CHIPID_STM32_L0,
+ .description = "L0x3 device",
+ .flash_type = FLASH_TYPE_L0,
+ .flash_size_reg = 0x1ff8007c,
+ .flash_pagesize = 0x80,
+ .sram_size = 0x2000,
+ .bootrom_base = 0x1ff0000,
+ .bootrom_size = 0x1000
+ },
+ {
+ // STM32L0x Category 5
+ // RM0367,RM0377 documents was used to find these parameters
+ .chip_id = STLINK_CHIPID_STM32_L0_CAT5,
+ .description = "L0x Category 5 device",
+ .flash_type = FLASH_TYPE_L0,
+ .flash_size_reg = 0x1ff8007c,
+ .flash_pagesize = 0x80,
+ .sram_size = 0x5000,
+ .bootrom_base = 0x1ff0000,
+ .bootrom_size = 0x2000
+ },
+ {
+ // STM32L0x Category 2
+ // RM0367,RM0377 documents was used to find these parameters
+ .chip_id = STLINK_CHIPID_STM32_L0_CAT2,
+ .description = "L0x Category 2 device",
+ .flash_type = FLASH_TYPE_L0,
+ .flash_size_reg = 0x1ff8007c,
+ .flash_pagesize = 0x80,
+ .sram_size = 0x2000,
+ .bootrom_base = 0x1ff0000,
+ .bootrom_size = 0x1000
+ },
+ {
+ // STM32F334
+ // RM0364 document was used to find these parameters
+ .chip_id = STLINK_CHIPID_STM32_F334,
+ .description = "F334 device",
+ .flash_type = FLASH_TYPE_F0,
+ .flash_size_reg = 0x1ffff7cc,
+ .flash_pagesize = 0x800,
+ .sram_size = 0x3000,
+ .bootrom_base = 0x1fffd800,
+ .bootrom_size = 0x2000
+ },
+ {
+ // This is STK32F303RET6 device from STM32 F3 Nucelo board.
+ // Support based on DM00043574.pdf (RM0316) document rev 5.
+ .chip_id = STLINK_CHIPID_STM32_F303_HIGH,
+ .description = "F303 high density device",
+ .flash_type = FLASH_TYPE_F0,
+ .flash_size_reg = 0x1ffff7cc, // 34.2.1 Flash size data register
+ .flash_pagesize = 0x800, // 4.2.1 Flash memory organization
+ .sram_size = 0x10000, // 3.3 Embedded SRAM
+ .bootrom_base = 0x1fffd800, // 3.3.2 / Table 4 System Memory
+ .bootrom_size = 0x2000
+ },
+ {
+ // STM32L4x6
+ // From RM0351.
+ .chip_id = STLINK_CHIPID_STM32_L4,
+ .description = "L4 device",
+ .flash_type = FLASH_TYPE_L4,
+ .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 45.2, page 1671)
+ .flash_pagesize = 0x800, // 2K (sec 3.2, page 78; also appears in sec 3.3.1 and tables 4-6 on pages 79-81)
+ // SRAM1 is "up to" 96k in the standard Cortex-M memory map;
+ // SRAM2 is 32k mapped at at 0x10000000 (sec 2.3, page 73 for
+ // sizes; table 2, page 74 for SRAM2 location)
+ .sram_size = 0x18000,
+ .bootrom_base = 0x1fff0000, // Tables 4-6, pages 80-81 (Bank 1 system memory)
+ .bootrom_size = 0x7000 // 28k (per bank), same source as base
+ },
+
+ };
+
+const struct stlink_chipid_params *stlink_chipid_get_params(uint32_t chipid)
+{
+ struct stlink_chipid_params *params = NULL;
+
+ for (size_t n = 0; n < STLINK_ARRAY_SIZE(devices); n++) {
+ if (devices[n].chip_id == chipid) {
+ params = &devices[n];
+ break;
+ }
+ }
+
+ return params;
+}
*/
int stlink_load_device_params(stlink_t *sl) {
ILOG("Loading device parameters....\n");
- const chip_params_t *params = NULL;
+ struct stlink_chipid_params *params = NULL;
stlink_core_id(sl);
uint32_t chip_id;
uint32_t flash_size;
sl->chip_id = 0x413;
}
- for (size_t i = 0; i < sizeof(devices) / sizeof(devices[0]); i++) {
- if(devices[i].chip_id == sl->chip_id) {
- params = &devices[i];
- break;
- }
- }
+ params = stlink_chipid_get_params(sl->chip_id);
if (params == NULL) {
WLOG("unknown chip id! %#x\n", chip_id);
return -1;
return -1;
}
-
// These are fixed...
sl->flash_base = STM32_FLASH_BASE;
sl->sram_base = STM32_SRAM_BASE;
flash_size = flash_size >>16;
flash_size = flash_size & 0xffff;
- if ((sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS) && ( flash_size == 0 )) {
+ if ((sl->chip_id == STLINK_CHIPID_STM32_L1_MEDIUM || sl->chip_id == STLINK_CHIPID_STM32_L1_MEDIUM_PLUS) && ( flash_size == 0 )) {
sl->flash_size = 128 * 1024;
- } else if (sl->chip_id == STM32_CHIPID_L1_CAT2) {
+ } else if (sl->chip_id == STLINK_CHIPID_STM32_L1_CAT2) {
sl->flash_size = (flash_size & 0xff) * 1024;
- } else if ((sl->chip_id & 0xFFF) == STM32_CHIPID_L1_HIGH) {
+ } else if ((sl->chip_id & 0xFFF) == STLINK_CHIPID_STM32_L1_HIGH) {
// 0 is 384k and 1 is 256k
if ( flash_size == 0 ) {
sl->flash_size = 384 * 1024;
//medium and low devices have the same chipid. ram size depends on flash size.
//STM32F100xx datasheet Doc ID 16455 Table 2
- if(sl->chip_id == STM32_CHIPID_F1_VL_MEDIUM_LOW && sl->flash_size < 64 * 1024){
+ if(sl->chip_id == STLINK_CHIPID_STM32_F1_VL_MEDIUM_LOW && sl->flash_size < 64 * 1024){
sl->sram_size = 0x1000;
}
}
uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr){
- if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) ||
- (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) ||
- (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F4_DSI)) {
+ if ((sl->chip_id == STLINK_CHIPID_STM32_F2) || (sl->chip_id == STLINK_CHIPID_STM32_F4) || (sl->chip_id == STLINK_CHIPID_STM32_F4_DE) ||
+ (sl->chip_id == STLINK_CHIPID_STM32_F4_LP) || (sl->chip_id == STLINK_CHIPID_STM32_F4_HD) || (sl->chip_id == STLINK_CHIPID_STM32_F411RE) ||
+ (sl->chip_id == STLINK_CHIPID_STM32_F446) || (sl->chip_id == STLINK_CHIPID_STM32_F4_DSI)) {
uint32_t sector=calculate_F4_sectornum(flashaddr);
if (sector>= 12) {
sector -= 12;
else if(sector<5) sl->flash_pgsz=0x10000;
else sl->flash_pgsz=0x20000;
}
- else if (sl->chip_id == STM32_CHIPID_F7) {
+ else if (sl->chip_id == STLINK_CHIPID_STM32_F7) {
uint32_t sector=calculate_F7_sectornum(flashaddr);
if (sector<4) sl->flash_pgsz=0x8000;
else if(sector<5) sl->flash_pgsz=0x20000;
unlock_flash_if(sl);
/* select the page to erase */
- if (sl->chip_id == STM32_CHIPID_L4) {
+ if (sl->chip_id == STLINK_CHIPID_STM32_L4) {
// calculate the actual bank+page from the address
uint32_t page = calculate_L4_page(sl, flashaddr);
fprintf(stderr, "EraseFlash - Page:0x%x Size:0x%x ", page, stlink_calculate_pagesize(sl, flashaddr));
write_flash_cr_bker_pnb(sl, page);
- } else if (sl->chip_id == STM32_CHIPID_F7) {
+ } else if (sl->chip_id == STLINK_CHIPID_STM32_F7) {
// calculate the actual page from the address
uint32_t sector=calculate_F7_sectornum(flashaddr);
uint32_t val;
uint32_t flash_regs_base;
- if (sl->chip_id == STM32_CHIPID_L0 || sl->chip_id == STM32_CHIPID_L0_CAT5 || sl->chip_id == STM32_CHIPID_L0_CAT2) {
+ if (sl->chip_id == STLINK_CHIPID_STM32_L0 || sl->chip_id == STLINK_CHIPID_STM32_L0_CAT5 || sl->chip_id == STLINK_CHIPID_STM32_L0_CAT2) {
flash_regs_base = STM32L0_FLASH_REGS_ADDR;
} else {
flash_regs_base = STM32L_FLASH_REGS_ADDR;
const uint8_t* loader_code;
size_t loader_size;
- if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_CAT2
- || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS || sl->chip_id == STM32_CHIPID_L1_HIGH
- || sl->chip_id == STM32_CHIPID_L152_RE
- || sl->chip_id == STM32_CHIPID_L0 || sl->chip_id == STM32_CHIPID_L0_CAT5 || sl->chip_id == STM32_CHIPID_L0_CAT2) { /* stm32l */
+ if (sl->chip_id == STLINK_CHIPID_STM32_L1_MEDIUM || sl->chip_id == STLINK_CHIPID_STM32_L1_CAT2
+ || sl->chip_id == STLINK_CHIPID_STM32_L1_MEDIUM_PLUS || sl->chip_id == STLINK_CHIPID_STM32_L1_HIGH
+ || sl->chip_id == STLINK_CHIPID_STM32_L152_RE
+ || sl->chip_id == STLINK_CHIPID_STM32_L0 || sl->chip_id == STLINK_CHIPID_STM32_L0_CAT5 || sl->chip_id == STLINK_CHIPID_STM32_L0_CAT2) { /* stm32l */
loader_code = loader_code_stm32l;
loader_size = sizeof(loader_code_stm32l);
} else if (sl->core_id == STM32VL_CORE_ID
- || sl->chip_id == STM32_CHIPID_F3
- || sl->chip_id == STM32_CHIPID_F3_SMALL
- || sl->chip_id == STM32_CHIPID_F303_HIGH
- || sl->chip_id == STM32_CHIPID_F37x
- || sl->chip_id == STM32_CHIPID_F334) {
+ || sl->chip_id == STLINK_CHIPID_STM32_F3
+ || sl->chip_id == STLINK_CHIPID_STM32_F3_SMALL
+ || sl->chip_id == STLINK_CHIPID_STM32_F303_HIGH
+ || sl->chip_id == STLINK_CHIPID_STM32_F37x
+ || sl->chip_id == STLINK_CHIPID_STM32_F334) {
loader_code = loader_code_stm32vl;
loader_size = sizeof(loader_code_stm32vl);
- } else if (sl->chip_id == STM32_CHIPID_F2 || sl->chip_id == STM32_CHIPID_F4 || (sl->chip_id == STM32_CHIPID_F4_DE) ||
- sl->chip_id == STM32_CHIPID_F4_LP || sl->chip_id == STM32_CHIPID_F4_HD || (sl->chip_id == STM32_CHIPID_F411RE) ||
- (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F4_DSI)){
+ } else if (sl->chip_id == STLINK_CHIPID_STM32_F2 || sl->chip_id == STLINK_CHIPID_STM32_F4 || (sl->chip_id == STLINK_CHIPID_STM32_F4_DE) ||
+ sl->chip_id == STLINK_CHIPID_STM32_F4_LP || sl->chip_id == STLINK_CHIPID_STM32_F4_HD || (sl->chip_id == STLINK_CHIPID_STM32_F411RE) ||
+ (sl->chip_id == STLINK_CHIPID_STM32_F446) || (sl->chip_id == STLINK_CHIPID_STM32_F4_DSI)){
int voltage = stlink_target_voltage(sl);
if (voltage == -1) {
printf("Failed to read Target voltage\n");
loader_code = loader_code_stm32f4_lv;
loader_size = sizeof(loader_code_stm32f4_lv);
}
- } else if (sl->chip_id == STM32_CHIPID_F7){
+ } else if (sl->chip_id == STLINK_CHIPID_STM32_F7){
loader_code = loader_code_stm32f7;
loader_size = sizeof(loader_code_stm32f7);
- } else if (sl->chip_id == STM32_CHIPID_F0 || sl->chip_id == STM32_CHIPID_F04 || sl->chip_id == STM32_CHIPID_F0_CAN || sl->chip_id == STM32_CHIPID_F0_SMALL || sl->chip_id == STM32_CHIPID_F09X) {
+ } else if (sl->chip_id == STLINK_CHIPID_STM32_F0 || sl->chip_id == STLINK_CHIPID_STM32_F04 || sl->chip_id == STLINK_CHIPID_STM32_F0_CAN || sl->chip_id == STLINK_CHIPID_STM32_F0_SMALL || sl->chip_id == STLINK_CHIPID_STM32_F09X) {
loader_code = loader_code_stm32f0;
loader_size = sizeof(loader_code_stm32f0);
- } else if (sl->chip_id == STM32_CHIPID_L4) {
+ } else if (sl->chip_id == STLINK_CHIPID_STM32_L4) {
loader_code = loader_code_stm32l4;
loader_size = sizeof(loader_code_stm32l4);
} else {
uint32_t flash_regs_base;
flash_loader_t fl;
- if (sl->chip_id == STM32_CHIPID_L0 || sl->chip_id == STM32_CHIPID_L0_CAT5 || sl->chip_id == STM32_CHIPID_L0_CAT2) {
+ if (sl->chip_id == STLINK_CHIPID_STM32_L0 || sl->chip_id == STLINK_CHIPID_STM32_L0_CAT5 || sl->chip_id == STLINK_CHIPID_STM32_L0_CAT2) {
flash_regs_base = STM32L0_FLASH_REGS_ADDR;
} else {
flash_regs_base = STM32L_FLASH_REGS_ADDR;
unlock_flash_if(sl);
/* TODO: Check that Voltage range is 2.7 - 3.6 V */
- if (sl->chip_id != STM32_CHIPID_L4) {
+ if (sl->chip_id != STLINK_CHIPID_STM32_L4) {
/* set parallelisim to 32 bit*/
int voltage = stlink_target_voltage(sl);
if (voltage == -1) {
uint32_t flash_regs_base;
uint32_t pagesize;
- if (sl->chip_id == STM32_CHIPID_L0 || sl->chip_id == STM32_CHIPID_L0_CAT5 || sl->chip_id == STM32_CHIPID_L0_CAT2) {
+ if (sl->chip_id == STLINK_CHIPID_STM32_L0 || sl->chip_id == STLINK_CHIPID_STM32_L0_CAT5 || sl->chip_id == STLINK_CHIPID_STM32_L0_CAT2) {
flash_regs_base = STM32L0_FLASH_REGS_ADDR;
pagesize = L0_WRITE_BLOCK_SIZE;
} else {
char* map = malloc(4096);
map[0] = '\0';
- if(sl->chip_id==STM32_CHIPID_F4 || sl->chip_id==STM32_CHIPID_F446) {
+ if(sl->chip_id==STLINK_CHIPID_STM32_F4 || sl->chip_id==STLINK_CHIPID_STM32_F446) {
strcpy(map, memory_map_template_F4);
- } else if(sl->chip_id==STM32_CHIPID_F4 || sl->chip_id==STM32_CHIPID_F7) {
+ } else if(sl->chip_id==STLINK_CHIPID_STM32_F4 || sl->chip_id==STLINK_CHIPID_STM32_F7) {
strcpy(map, memory_map_template_F7);
- } else if(sl->chip_id==STM32_CHIPID_F4_HD) {
+ } else if(sl->chip_id==STLINK_CHIPID_STM32_F4_HD) {
strcpy(map, memory_map_template_F4_HD);
- } else if(sl->chip_id==STM32_CHIPID_F2) {
+ } else if(sl->chip_id==STLINK_CHIPID_STM32_F2) {
snprintf(map, 4096, memory_map_template_F2,
sl->flash_size,
sl->sram_size,
sl->flash_size - 0x20000,
sl->sys_base, sl->sys_size);
- } else if(sl->chip_id==STM32_CHIPID_L4) {
+ } else if(sl->chip_id==STLINK_CHIPID_STM32_L4) {
snprintf(map, 4096, memory_map_template_L4,
sl->flash_size, sl->flash_size);
} else {
return -1;
}
- if (sl->chip_id==STM32_CHIPID_F7) {
+ if (sl->chip_id==STLINK_CHIPID_STM32_F7) {
fpb_addr = addr;
} else {
fpb_addr = addr & ~0x3;
brk->addr = fpb_addr;
- if (sl->chip_id==STM32_CHIPID_F7) {
+ if (sl->chip_id==STLINK_CHIPID_STM32_F7) {
if(set) brk->type = type;
else brk->type = 0;
int i;
/* Assume only F7 has a cache. */
- if(sl->chip_id!=STM32_CHIPID_F7)
+ if(sl->chip_id!=STLINK_CHIPID_STM32_F7)
return;
stlink_read_debug32(sl, CLIDR, &clidr);
{
unsigned ccr;
- if(sl->chip_id!=STM32_CHIPID_F7)
+ if(sl->chip_id!=STLINK_CHIPID_STM32_F7)
return;
if (!cache_modified)
return;
DLOG("query: %s;%s\n", queryName, params);
if(!strcmp(queryName, "Supported")) {
- if(sl->chip_id==STM32_CHIPID_F4
- || sl->chip_id==STM32_CHIPID_F4_HD
- || sl->chip_id==STM32_CHIPID_F7) {
+ if(sl->chip_id==STLINK_CHIPID_STM32_F4
+ || sl->chip_id==STLINK_CHIPID_STM32_F4_HD
+ || sl->chip_id==STLINK_CHIPID_STM32_F7) {
reply = strdup("PacketSize=3fff;qXfer:memory-map:read+;qXfer:features:read+");
}
else {
}
// Disable DMA - Set All DMA CCR Registers to zero. - AKS 1/7/2013
- if (sl->chip_id == STM32_CHIPID_F4)
+ if (sl->chip_id == STLINK_CHIPID_STM32_F4)
{
memset(sl->q_buf,0,4);
for (int i=0;i<8;i++) {
static gchar *
dev_format_chip_id (guint32 chip_id)
{
+ const struct stlink_chipid_params *params;
gint i;
- for (i = 0; i < sizeof (devices) / sizeof (devices[0]); i++) {
- if (chip_id == devices[i].chip_id) {
- return g_strdup (devices[i].description);
- }
- }
- return g_strdup_printf ("0x%x", chip_id);
+ params = stlink_chipid_get_params(chip_id);
+ if (!params)
+ return g_strdup_printf ("0x%x", chip_id);
+
+ return g_strdup (params->description);
}
static gchar *
stlink_enter_swd_mode(gui->sl);
/* Disable DMA - Set All DMA CCR Registers to zero. - AKS 1/7/2013 */
- if (gui->sl->chip_id == STM32_CHIPID_F4) {
+ if (gui->sl->chip_id == STLINK_CHIPID_STM32_F4) {
memset(gui->sl->q_buf, 0, 4);
for (i = 0; i < 8; i++) {
stlink_write_mem32(gui->sl, 0x40026000 + 0x10 + 0x18 * i, 4);
static void stlink_print_info(stlink_t *sl)
{
- const chip_params_t *params = NULL;
+ const struct stlink_chipid_params *params = NULL;
if (!sl)
return;
printf(" sram: %zu\n", sl->sram_size);
printf(" chipid: 0x%.4x\n", sl->chip_id);
- for (size_t i = 0; i < sizeof(devices) / sizeof(devices[0]); i++) {
- if (devices[i].chip_id == sl->chip_id) {
- params = &devices[i];
- break;
- }
- }
-
- if (params)
- printf(" descr: %s\n", params->description);
+ params = stlink_chipid_get_params(sl->chip_id);
+ if (params)
+ printf(" descr: %s\n", params->description);
}
static void stlink_probe(void)
else if (strcmp(av[1], "--hla-serial") == 0)
stlink_print_serial(sl, true);
else if (strcmp(av[1], "--descr") == 0) {
- const chip_params_t *params = NULL;
- for (size_t i = 0; i < sizeof(devices) / sizeof(devices[0]); i++) {
- if(devices[i].chip_id == sl->chip_id) {
- params = &devices[i];
- break;
- }
- }
- if (params == NULL) {
+ const struct stlink_chipid_params *params = stlink_chipid_get_params(sl->chip_id);
+ if (params == NULL)
return -1;
- }
printf("%s\n", params->description);
}
projects / fw / stlink / commitdiff