read_debug32: Use a pointer instead of returning the value

This rework is done in order to prepare for propagating errors returned by
libusb.

Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com>

diff --git a/gdbserver/gdb-server.c b/gdbserver/gdb-server.c
index ef289f282a8789579cbeaa543330d36077284d1e..eca6597b470d0fae819500d6f1fface020afde30 100644 (file)
--- a/gdbserver/gdb-server.c
+++ b/gdbserver/gdb-server.c
@@ -488,11 +488,13 @@ struct code_hw_watchpoint {
 struct code_hw_watchpoint data_watches[DATA_WATCH_NUM];
 
 static void init_data_watchpoints(stlink_t *sl) {
+    uint32_t data;
     DLOG("init watchpoints\n");
 
+    stlink_read_debug32(sl, 0xE000EDFC, &data);
+    data |= 1<<24;
     // set trcena in debug command to turn on dwt unit
-    stlink_write_debug32(sl, 0xE000EDFC,
-            stlink_read_debug32(sl, 0xE000EDFC) | (1<<24));
+    stlink_write_debug32(sl, 0xE000EDFC, data);
 
     // make sure all watchpoints are cleared
     for(int i = 0; i < DATA_WATCH_NUM; i++) {
@@ -504,7 +506,7 @@ static void init_data_watchpoints(stlink_t *sl) {
 static int add_data_watchpoint(stlink_t *sl, enum watchfun wf,
                                stm32_addr_t addr, unsigned int len) {
     int i = 0;
-    uint32_t mask;
+    uint32_t mask, dummy;
 
     // computer mask
     // find a free watchpoint
@@ -537,7 +539,7 @@ static int add_data_watchpoint(stlink_t *sl, enum watchfun wf,
                 stlink_write_debug32(sl, 0xE0001028 + i * 16, wf);
 
                 // just to make sure the matched bit is clear !
-                stlink_read_debug32(sl,  0xE0001028 + i * 16);
+                stlink_read_debug32(sl,  0xE0001028 + i * 16, &dummy);
                 return 0;
             }
         }
@@ -581,9 +583,10 @@ struct code_hw_breakpoint {
 struct code_hw_breakpoint code_breaks[CODE_BREAK_NUM_MAX];
 
 static void init_code_breakpoints(stlink_t *sl) {
+    unsigned int val;
     memset(sl->q_buf, 0, 4);
     stlink_write_debug32(sl, CM3_REG_FP_CTRL, 0x03 /*KEY | ENABLE4*/);
-    unsigned int val = stlink_read_debug32(sl, CM3_REG_FP_CTRL);
+    stlink_read_debug32(sl, CM3_REG_FP_CTRL, &val);
     code_break_num = ((val >> 4) & 0xf);
     code_lit_num = ((val >> 8) & 0xf);
 
@@ -821,7 +824,8 @@ static void read_cache_level_desc(stlink_t *sl, struct cache_level_desc *desc)
 {
   unsigned int ccsidr;
   unsigned int log2_nsets;
-  ccsidr = stlink_read_debug32(sl, CCSIDR);
+
+  stlink_read_debug32(sl, CCSIDR, &ccsidr);
   desc->nsets = ((ccsidr >> 13) & 0x3fff) + 1;
   desc->nways = ((ccsidr >> 3) & 0x1ff) + 1;
   desc->log2_nways = ceil_log2 (desc->nways);
@@ -841,9 +845,9 @@ static void init_cache (stlink_t *sl) {
   if(sl->chip_id!=STM32_CHIPID_F7)
     return;
 
-  clidr = stlink_read_debug32(sl, CLIDR);
-  ccr = stlink_read_debug32(sl, CCR);
-  ctr = stlink_read_debug32(sl, CTR);
+  stlink_read_debug32(sl, CLIDR, &clidr);
+  stlink_read_debug32(sl, CCR, &ccr);
+  stlink_read_debug32(sl, CTR, &ctr);
   cache_desc.dminline = 4 << ((ctr >> 16) & 0x0f);
   cache_desc.iminline = 4 << (ctr & 0x0f);
   cache_desc.louu = (clidr >> 27) & 7;
@@ -925,7 +929,7 @@ static void cache_sync(stlink_t *sl)
     return;
   cache_modified = 0;
 
-  ccr = stlink_read_debug32(sl, CCR);
+  stlink_read_debug32(sl, CCR, &ccr);
   if (ccr & (CCR_IC | CCR_DC))
     cache_flush(sl, ccr);
 }

diff --git a/src/stlink-common.c b/src/stlink-common.c
index 51efae43fcf99282371b13bd4a2657b6b9a24c04..a20f3fa4f917a53ec5b5a75864501d0ee1f76ae3 100644 (file)
--- a/src/stlink-common.c
+++ b/src/stlink-common.c
@@ -165,15 +165,21 @@ uint32_t read_uint32(const unsigned char *c, const int pt) {
 }
 
 static uint32_t __attribute__((unused)) read_flash_rdp(stlink_t *sl) {
-    return stlink_read_debug32(sl, FLASH_WRPR) & 0xff;
+    uint32_t rdp;
+    stlink_read_debug32(sl, FLASH_WRPR, &rdp);
+    return rdp & 0xff;
 }
 
 static inline uint32_t read_flash_wrpr(stlink_t *sl) {
-    return stlink_read_debug32(sl, FLASH_WRPR);
+    uint32_t wrpr;
+    stlink_read_debug32(sl, FLASH_WRPR, &wrpr);
+    return wrpr;
 }
 
 static inline uint32_t read_flash_obr(stlink_t *sl) {
-    return stlink_read_debug32(sl, FLASH_OBR);
+    uint32_t obr;
+    stlink_read_debug32(sl, FLASH_OBR, &obr);
+    return obr;
 }
 
 static inline uint32_t read_flash_cr(stlink_t *sl) {
@@ -181,11 +187,11 @@ static inline uint32_t read_flash_cr(stlink_t *sl) {
     if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) ||(sl->chip_id == STM32_CHIPID_F4_DE) ||
             (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) ||
             (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7) || (sl->chip_id == STM32_CHIPID_F4_DSI))
-        res = stlink_read_debug32(sl, FLASH_F4_CR);
+        stlink_read_debug32(sl, FLASH_F4_CR, &res);
     else if (sl->chip_id == STM32_CHIPID_L4)
-        res = stlink_read_debug32(sl, STM32L4_FLASH_CR);
+        stlink_read_debug32(sl, STM32L4_FLASH_CR, &res);
     else
-        res = stlink_read_debug32(sl, FLASH_CR);
+        stlink_read_debug32(sl, FLASH_CR, &res);
 #if DEBUG_FLASH
     fprintf(stdout, "CR:0x%x\n", res);
 #endif
@@ -297,51 +303,63 @@ static void __attribute__((unused)) clear_flash_cr_per(stlink_t *sl) {
 }
 
 static void set_flash_cr_mer(stlink_t *sl) {
+    uint32_t val;
     if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) ||
             (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) ||
-            (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7) || (sl->chip_id == STM32_CHIPID_F4_DSI))
-        stlink_write_debug32(sl, FLASH_F4_CR,
-                stlink_read_debug32(sl, FLASH_F4_CR) | (1 << FLASH_CR_MER));
-    else if (sl->chip_id == STM32_CHIPID_L4) {
-        uint32_t x = stlink_read_debug32(sl, STM32L4_FLASH_CR);
-        x &=~ STM32L4_FLASH_CR_OPBITS;
-        x |= (1lu << STM32L4_FLASH_CR_MER1) | (1lu << STM32L4_FLASH_CR_MER2);
-        stlink_write_debug32(sl, STM32L4_FLASH_CR, x);
-    } else
-        stlink_write_debug32(sl, FLASH_CR,
-                stlink_read_debug32(sl, FLASH_CR) | (1 << FLASH_CR_MER));
+            (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7) || (sl->chip_id == STM32_CHIPID_F4_DSI)) {
+        stlink_read_debug32(sl, FLASH_F4_CR, &val);
+        val |= 1 << FLASH_CR_MER;
+        stlink_write_debug32(sl, FLASH_F4_CR, val);
+    } else if (sl->chip_id == STM32_CHIPID_L4) {
+        stlink_read_debug32(sl, STM32L4_FLASH_CR, &val);
+        val &=~ STM32L4_FLASH_CR_OPBITS;
+        val |= (1lu << STM32L4_FLASH_CR_MER1) | (1lu << STM32L4_FLASH_CR_MER2);
+        stlink_write_debug32(sl, STM32L4_FLASH_CR, val);
+    } else {
+        stlink_read_debug32(sl, FLASH_CR, &val);
+        val |= 1 << FLASH_CR_MER;
+        stlink_write_debug32(sl, FLASH_CR, val);
+    }
 }
 
 static void __attribute__((unused)) clear_flash_cr_mer(stlink_t *sl) {
+    uint32_t val;
     if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) ||
             (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) ||
-            (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7) || (sl->chip_id == STM32_CHIPID_F4_DSI))
-        stlink_write_debug32(sl, FLASH_F4_CR,
-                stlink_read_debug32(sl, FLASH_F4_CR) & ~(1 << FLASH_CR_MER));
-    else
-        stlink_write_debug32(sl, FLASH_CR,
-                stlink_read_debug32(sl, FLASH_CR) & ~(1 << FLASH_CR_MER));
+            (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7) || (sl->chip_id == STM32_CHIPID_F4_DSI)) {
+        stlink_read_debug32(sl, FLASH_F4_CR, &val);
+        val &= ~(1 << FLASH_CR_MER);
+        stlink_write_debug32(sl, FLASH_F4_CR, val);
+    } else {
+        stlink_read_debug32(sl, FLASH_CR, &val);
+        val &= ~(1 << FLASH_CR_MER);
+        stlink_write_debug32(sl, FLASH_CR, val);
+    }
 }
 
 static void set_flash_cr_strt(stlink_t *sl) {
+    uint32_t val;
     if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) ||
             (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) ||
             (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7) || (sl->chip_id == STM32_CHIPID_F4_DSI)) {
-        uint32_t x = read_flash_cr(sl);
-        x |= (1 << FLASH_F4_CR_STRT);
-        stlink_write_debug32(sl, FLASH_F4_CR, x);
+        val = read_flash_cr(sl);
+        val |= (1 << FLASH_F4_CR_STRT);
+        stlink_write_debug32(sl, FLASH_F4_CR, val);
     } else if (sl->chip_id == STM32_CHIPID_L4) {
-        uint32_t x = read_flash_cr(sl);
-        x |= (1lu << STM32L4_FLASH_CR_STRT);
-        stlink_write_debug32(sl, STM32L4_FLASH_CR, x);
+        val = read_flash_cr(sl);
+        val |= (1lu << STM32L4_FLASH_CR_STRT);
+        stlink_write_debug32(sl, STM32L4_FLASH_CR, val);
     } else {
-        stlink_write_debug32(sl, FLASH_CR,
-                stlink_read_debug32(sl, FLASH_CR) | (1 << FLASH_CR_STRT) );
+        stlink_read_debug32(sl, FLASH_CR, &val);
+        val |= 1 << FLASH_CR_STRT;
+        stlink_write_debug32(sl, FLASH_CR, val);
     }
 }
 
 static inline uint32_t read_flash_acr(stlink_t *sl) {
-    return stlink_read_debug32(sl, FLASH_ACR);
+    uint32_t acr;
+    stlink_read_debug32(sl, FLASH_ACR, &acr);
+    return acr;
 }
 
 static inline uint32_t read_flash_sr(stlink_t *sl) {
@@ -349,11 +367,11 @@ static inline uint32_t read_flash_sr(stlink_t *sl) {
     if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) ||
             (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) ||
             (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7) || (sl->chip_id == STM32_CHIPID_F4_DSI))
-        res = stlink_read_debug32(sl, FLASH_F4_SR);
+        stlink_read_debug32(sl, FLASH_F4_SR, &res);
     else if (sl->chip_id == STM32_CHIPID_L4)
-        res = stlink_read_debug32(sl, STM32L4_FLASH_SR);
+        stlink_read_debug32(sl, STM32L4_FLASH_SR, &res);
     else
-        res = stlink_read_debug32(sl, FLASH_SR);
+        stlink_read_debug32(sl, FLASH_SR, &res);
     //fprintf(stdout, "SR:0x%x\n", *(uint32_t*) sl->q_buf);
     return res;
 }
@@ -486,8 +504,10 @@ uint32_t stlink_core_id(stlink_t *sl) {
 }
 
 uint32_t stlink_chip_id(stlink_t *sl) {
-    uint32_t chip_id = stlink_read_debug32(sl, 0xE0042000);
-    if (chip_id == 0) chip_id = stlink_read_debug32(sl, 0x40015800);   //Try Corex M0 DBGMCU_IDCODE register address
+    uint32_t chip_id;
+    stlink_read_debug32(sl, 0xE0042000, &chip_id);
+    if (chip_id == 0)
+        stlink_read_debug32(sl, 0x40015800, &chip_id);    //Try Corex M0 DBGMCU_IDCODE register address
     return chip_id;
 }
 
@@ -497,7 +517,8 @@ uint32_t stlink_chip_id(stlink_t *sl) {
  * @param cpuid pointer to the result object
  */
 void stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid) {
-    uint32_t raw = stlink_read_debug32(sl, CM3_REG_CPUID);
+    uint32_t raw;
+    stlink_read_debug32(sl, CM3_REG_CPUID, &raw);
     cpuid->implementer_id = (raw >> 24) & 0x7f;
     cpuid->variant = (raw >> 20) & 0xf;
     cpuid->part = (raw >> 4) & 0xfff;
@@ -520,7 +541,8 @@ int stlink_load_device_params(stlink_t *sl) {
     sl->chip_id = chip_id & 0xfff;
     /* Fix chip_id for F4 rev A errata , Read CPU ID, as CoreID is the same for F2/F4*/
     if (sl->chip_id == 0x411) {
-        uint32_t cpuid = stlink_read_debug32(sl, 0xE000ED00);
+        uint32_t cpuid;
+        stlink_read_debug32(sl, 0xE000ED00, &cpuid);
         if ((cpuid  & 0xfff0) == 0xc240)
             sl->chip_id = 0x413;
     }
@@ -539,7 +561,7 @@ int stlink_load_device_params(stlink_t *sl) {
     // These are fixed...
     sl->flash_base = STM32_FLASH_BASE;
     sl->sram_base = STM32_SRAM_BASE;
-    flash_size = stlink_read_debug32(sl,(params->flash_size_reg) & ~3);
+    stlink_read_debug32(sl,(params->flash_size_reg) & ~3, &flash_size);
     if (params->flash_size_reg & 2)
         flash_size = flash_size >>16;
     flash_size = flash_size & 0xffff;
@@ -657,10 +679,10 @@ int stlink_target_voltage(stlink_t *sl) {
     return voltage;
 }
 
-uint32_t stlink_read_debug32(stlink_t *sl, uint32_t addr) {
-    uint32_t data = sl->backend->read_debug32(sl, addr);
+void stlink_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data) {
+    sl->backend->read_debug32(sl, addr, data);
     DLOG("*** stlink_read_debug32 %x is %#x\n", data, addr);
-    return data;
+    return;
 }
 
 void stlink_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data) {
@@ -958,6 +980,7 @@ int stlink_fwrite_sram
     size_t off;
     size_t len;
     mapped_file_t mf = MAPPED_FILE_INITIALIZER;
+    uint32_t val;
 
 
     if (map_file(&mf, path) == -1) {
@@ -1016,9 +1039,11 @@ int stlink_fwrite_sram
     /* success */
     error = 0;
     /* set stack*/
-    stlink_write_reg(sl, stlink_read_debug32(sl, addr    ),13);
+    stlink_read_debug32(sl, addr, &val);
+    stlink_write_reg(sl, val, 13);
     /* Set PC to the reset routine*/
-    stlink_write_reg(sl, stlink_read_debug32(sl, addr + 4),15);
+    stlink_read_debug32(sl, addr + 4, &val);
+    stlink_write_reg(sl, val, 15);
     stlink_run(sl);
 
 on_error:
@@ -1115,7 +1140,8 @@ uint32_t calculate_F7_sectornum(uint32_t flashaddr){
 // Returns BKER:PNB for the given page address
 uint32_t calculate_L4_page(stlink_t *sl, uint32_t flashaddr) {
     uint32_t bker = 0;
-    uint32_t flashopt = stlink_read_debug32(sl, STM32L4_FLASH_OPTR);
+    uint32_t flashopt;
+    stlink_read_debug32(sl, STM32L4_FLASH_OPTR, &flashopt);
     flashaddr -= STM32_FLASH_BASE;
     if (flashopt & (1lu << STM32L4_FLASH_OPTR_DUALBANK)) {
         uint32_t banksize = sl->flash_size / 2;
@@ -1217,14 +1243,14 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr)
         }
 
         /* check if the locks are set */
-        val = stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF);
+        stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val);
         if((val & (1<<0))||(val & (1<<1))) {
             /* disable pecr protection */
             stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, 0x89abcdef);
             stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, 0x02030405);
 
             /* check pecr.pelock is cleared */
-            val = stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF);
+            stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val);
             if (val & (1 << 0)) {
                 WLOG("pecr.pelock not clear (%#x)\n", val);
                 return -1;
@@ -1235,7 +1261,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr)
             stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, 0x13141516);
 
             /* check pecr.prglock is cleared */
-            val = stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF);
+            stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val);
             if (val & (1 << 1)) {
                 WLOG("pecr.prglock not clear (%#x)\n", val);
                 return -1;
@@ -1253,8 +1279,9 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr)
          * TEXANE: ok, if experience says so and it works for you, we comment
          * it. If someone has a problem, please drop an email.
          */
-        while ((stlink_read_debug32(sl, STM32L_FLASH_SR) & (1 << 0)) != 0)
-            ;
+        do {
+            stlink_read_debug32(sl, STM32L_FLASH_SR, &val)
+        } while((val & (1 << 0)) != 0);
 
 #endif /* fix_to_be_confirmed */
 
@@ -1265,12 +1292,13 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr)
            page erase command, even though PM0062 recommends to wait before it.
            Test shows that a few iterations is performed in the following loop
            before busy bit is cleared.*/
-        while ((stlink_read_debug32(sl, flash_regs_base + FLASH_SR_OFF) & (1 << 0)) != 0)
-            ;
+        do {
+            stlink_read_debug32(sl, flash_regs_base + FLASH_SR_OFF, &val);
+        } while ((val & (1 << 0)) != 0);
 
         /* reset lock bits */
-        val = stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF)
-            | (1 << 0) | (1 << 1) | (1 << 2);
+        stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val);
+        val |= (1 << 0) | (1 << 1) | (1 << 2);
         stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val);
     } else if (sl->core_id == STM32VL_CORE_ID 
             || sl->core_id == STM32F0_CORE_ID 
@@ -1687,18 +1715,20 @@ int stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uin
         return -1;
     }
     /* Unlock already done */
-    val = stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF);
+    stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val);
     val |= (1 << FLASH_L1_FPRG);
     stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val);
 
     val |= (1 << FLASH_L1_PROG);
     stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val);
-    while ((stlink_read_debug32(sl, flash_regs_base + FLASH_SR_OFF) & (1 << 0)) != 0) {}
+    do {
+        stlink_read_debug32(sl, flash_regs_base + FLASH_SR_OFF, &val);
+    } while ((val & (1 << 0)) != 0);
 
     for (count = 0; count  < num_half_pages; count ++) {
         if (run_flash_loader(sl, &fl, addr + count * pagesize, base + count * pagesize, pagesize) == -1) {
             WLOG("l1_run_flash_loader(%#zx) failed! == -1\n", addr + count * pagesize);
-            val = stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF);
+            stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val);
             val &= ~((1 << FLASH_L1_FPRG) |(1 << FLASH_L1_PROG));
             stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val);
             return -1;
@@ -1710,13 +1740,14 @@ int stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uin
             fprintf(stdout, "\r%3u/%u halfpages written", count + 1, num_half_pages);
             fflush(stdout);
         }
-        while ((stlink_read_debug32(sl, flash_regs_base + FLASH_SR_OFF) & (1 << 0)) != 0) {
-        }
+        do {
+            stlink_read_debug32(sl, flash_regs_base + FLASH_SR_OFF, &val);
+        } while ((val & (1 << 0)) != 0);
     }
-    val = stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF);
+    stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val);
     val &= ~(1 << FLASH_L1_PROG);
     stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val);
-    val = stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF);
+    stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val);
     val &= ~(1 << FLASH_L1_FPRG);
     stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val);
 
@@ -1858,7 +1889,7 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t
         stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, 0x02030405);
 
         /* check pecr.pelock is cleared */
-        val = stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF);
+        stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val);
         if (val & (1 << 0)) {
             fprintf(stderr, "pecr.pelock not clear\n");
             return -1;
@@ -1869,7 +1900,7 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t
         stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, 0x13141516);
 
         /* check pecr.prglock is cleared */
-        val = stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF);
+        stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val);
         if (val & (1 << 1)) {
             fprintf(stderr, "pecr.prglock not clear\n");
             return -1;
@@ -1900,16 +1931,17 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t
             stlink_write_debug32(sl, addr + off, data);
 
             /* wait for sr.busy to be cleared */
-            while ((stlink_read_debug32(sl, flash_regs_base + FLASH_SR_OFF) & (1 << 0)) != 0)
-                ;
+            do {
+                stlink_read_debug32(sl, flash_regs_base + FLASH_SR_OFF, &val);
+            } while ((val & (1 << 0)) != 0);
 
             /* todo: check redo write operation */
 
         }
         fprintf(stdout, "\n");
         /* reset lock bits */
-        val = stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF)
-            | (1 << 0) | (1 << 1) | (1 << 2);
+        stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val);
+        val |= (1 << 0) | (1 << 1) | (1 << 2);
         stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val);
     } else if (sl->core_id == STM32VL_CORE_ID ||
                 sl->core_id == STM32F0_CORE_ID ||
@@ -1966,7 +1998,7 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t
 int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr) {
     /* write the file in flash at addr */
     int err;
-    unsigned int num_empty, index;
+    unsigned int num_empty, index, val;
     unsigned char erased_pattern = (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_CAT2
             || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS || sl->chip_id == STM32_CHIPID_L1_HIGH
             || sl->chip_id == STM32_CHIPID_L152_RE) ? 0:0xff;
@@ -1988,9 +2020,11 @@ int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr) {
     }
     err = stlink_write_flash(sl, addr, mf.base, num_empty == mf.len? mf.len : mf.len - num_empty, num_empty == mf.len);
     /* set stack*/
-    stlink_write_reg(sl, stlink_read_debug32(sl, addr    ),13);
+    stlink_read_debug32(sl, addr, &val);
+    stlink_write_reg(sl, val, 13);
     /* Set PC to the reset routine*/
-    stlink_write_reg(sl, stlink_read_debug32(sl, addr + 4),15);
+    stlink_read_debug32(sl, addr + 4, &val);
+    stlink_write_reg(sl, val, 15);
     stlink_run(sl);
     unmap_file(&mf);
     return err;

diff --git a/src/stlink-common.h b/src/stlink-common.h
index 2751ac8392f1014f8c3daf9fbc2398f4c249682e..b3f86768cd221f83c935ec1a17b9c904efb1a070 100644 (file)
--- a/src/stlink-common.h
+++ b/src/stlink-common.h
@@ -566,7 +566,7 @@ extern "C" {
         void (*run) (stlink_t * stl);
         void (*status) (stlink_t * stl);
         void (*version) (stlink_t *sl);
-        uint32_t (*read_debug32) (stlink_t *sl, uint32_t addr);
+        void (*read_debug32) (stlink_t *sl, uint32_t addr, uint32_t *data);
         void (*read_mem32) (stlink_t *sl, uint32_t addr, uint16_t len);
         void (*write_debug32) (stlink_t *sl, uint32_t addr, uint32_t data);
         void (*write_mem32) (stlink_t *sl, uint32_t addr, uint16_t len);
@@ -636,7 +636,7 @@ extern "C" {
     void stlink_run(stlink_t *sl);
     void stlink_status(stlink_t *sl);
     void stlink_version(stlink_t *sl);
-    uint32_t stlink_read_debug32(stlink_t *sl, uint32_t addr);
+    void stlink_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data);
     void stlink_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len);
     void stlink_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data);
     void stlink_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len);

diff --git a/src/stlink-sg.c b/src/stlink-sg.c
index b16a2edfc8c8ee2aff173d791e80b7d505d140b3..3fdc0bde5b85b23949c8ed0b57f5e83b295bcdde 100644 (file)
--- a/src/stlink-sg.c
+++ b/src/stlink-sg.c
@@ -811,7 +811,7 @@ void _stlink_sg_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data) {
 
 // Read one DWORD data from memory
 
-uint32_t _stlink_sg_read_debug32(stlink_t *sl, uint32_t addr) {
+void _stlink_sg_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data) {
     struct stlink_libsg *sg = sl->backend_data;
     clear_cdb(sg);
     sg->cdb_cmd_blk[1] = STLINK_JTAG_READDEBUG_32BIT;
@@ -820,7 +820,8 @@ uint32_t _stlink_sg_read_debug32(stlink_t *sl, uint32_t addr) {
     sl->q_len = 8;
     stlink_q(sl);
 
-    return read_uint32(sl->q_buf, 4);
+    *data = read_uint32(sl->q_buf, 4);
+    return;
 }
 
 // Exit the jtag or swd mode and enter the mass mode.

diff --git a/src/stlink-usb.c b/src/stlink-usb.c
index c4c693d2b4514de39d7992aae46b32ed83e80641..927e44e9681649372c505fb580a330b0544bbde1 100644 (file)
--- a/src/stlink-usb.c
+++ b/src/stlink-usb.c
@@ -138,7 +138,7 @@ int32_t _stlink_usb_target_voltage(stlink_t *sl) {
     return voltage;
 }
 
-uint32_t _stlink_usb_read_debug32(stlink_t *sl, uint32_t addr) {
+void _stlink_usb_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data) {
     struct stlink_libusb * const slu = sl->backend_data;
     unsigned char* const rdata = sl->q_buf;
     unsigned char* const cmd  = sl->c_buf;
@@ -152,9 +152,10 @@ uint32_t _stlink_usb_read_debug32(stlink_t *sl, uint32_t addr) {
     size = send_recv(slu, 1, cmd, slu->cmd_len, rdata, rep_len);
     if (size == -1) {
         printf("[!] send_recv\n");
-        return 0;
+        return;
     }
-    return read_uint32(rdata, 4);
+    *data = read_uint32(rdata, 4);
+    return;
 }
 
 void _stlink_usb_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data) {