Adding original source of vl factory demo

It compiles, but I've got bugs preventing me from running this yet :(

diff --git a/example/32vl_factory_demo/Makefile b/example/32vl_factory_demo/Makefile
new file mode 100644 (file)
index 0000000..81cdd56
--- /dev/null
+++ b/example/32vl_factory_demo/Makefile
@@ -0,0 +1,53 @@
+# build an elf from the an3268 demonstration code
+APP=32vl_factory_demo
+
+CC=arm-none-eabi-gcc
+OBJCOPY=arm-none-eabi-objcopy
+
+CFLAGS=-O2 -mlittle-endian -mthumb
+CFLAGS+=-mcpu=cortex-m3 -ffreestanding -nostdlib -nostdinc
+ifeq ($(DEBUG),1)
+       CFLAGS+=-g
+endif
+
+# to run from SRAM
+CFLAGS+=-Wl,-Ttext,0x20000000 -Wl,-e,0x20000000
+
+# to write to flash then run
+# CFLAGS+=-Wl,-Ttext,0x08000000 -Wl,-e,0x08000000
+
+PLATFORM=stm32f10x
+BOARD_SUPPORT=../board_support/discovery_32vl
+LIBS_STM_PATH=../libs_stm
+
+CFLAGS+=-I.
+CFLAGS+=-I$(LIBS_STM_PATH)/inc/base
+CFLAGS+=-I$(LIBS_STM_PATH)/inc/core_support
+CFLAGS+=-I$(LIBS_STM_PATH)/inc/device_support
+CFLAGS+=-I$(LIBS_STM_PATH)/inc/$(PLATFORM)
+CFLAGS+=-I$(BOARD_SUPPORT)
+
+LDFLAGS+=-L$(LIBS_STM_PATH)/build -lstm32_stdperiph_f10x
+
+
+SRCS=$(wildcard *.c)
+SRCS+=$(wildcard $(BOARD_SUPPORT)/*.c)
+
+OBJS=$(SRCS:.c=.o)
+
+all: $(APP).elf
+
+%.bin: %.elf
+       $(OBJCOPY) -O binary $^ $@
+
+$(APP).elf: $(OBJS)
+       $(CC) $(CFLAGS) -o $@ $(OBJS) $(LDFLAGS)
+
+%.o: %.c
+       $(CC) $(CFLAGS) -c -o $@ $^
+
+clean:
+       rm -rf $(OBJS)
+       rm -rf $(APP).*
+
+.PHONY: all clean

diff --git a/example/32vl_factory_demo/README b/example/32vl_factory_demo/README
new file mode 100644 (file)
index 0000000..28c8395
--- /dev/null
+++ b/example/32vl_factory_demo/README
@@ -0,0 +1,5 @@
+This source is copied from AN3268, the STM demo code for the VL discovery board.
+
+It was modified to add includes and things where needed,  but nothing else was touched.
+
+Eventually, this should be usable to restore a board to virgin state.  (but not yet)

diff --git a/example/32vl_factory_demo/main.c b/example/32vl_factory_demo/main.c
new file mode 100644 (file)
index 0000000..0043b65
--- /dev/null
+++ b/example/32vl_factory_demo/main.c
@@ -0,0 +1,234 @@
+/**\r
+  ******************************************************************************\r
+  * @file    Demo/src/main.c \r
+  * @author  MCD Application Team\r
+  * @version V1.0.0\r
+  * @date    09/13/2010\r
+  * @brief   Main program body\r
+  ******************************************************************************\r
+  * @copy\r
+  *\r
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+  *\r
+  * <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+  */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x.h"\r
+#include "stm32f10x_conf.h"\r
+#include "STM32vldiscovery.h"\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+#define  LSE_FAIL_FLAG  0x80\r
+#define  LSE_PASS_FLAG  0x100\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private consts ------------------------------------------------------------*/\r
+\r
+/* Private variables ---------------------------------------------------------*/\r
+u32 LSE_Delay = 0;\r
+u32 count = 0;\r
+u32 BlinkSpeed = 0;\r
+u32 KeyState = 0;\r
+static __IO uint32_t TimingDelay;\r
+/* Private function prototypes -----------------------------------------------*/\r
+void Delay(uint32_t nTime);\r
+void TimingDelay_Decrement(void);\r
+\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/**\r
+  * @brief  Main program.\r
+  * @param  None\r
+  * @retval None\r
+  */\r
+\r
+int main(void)\r
+{\r
+  /* Enable GPIOx Clock */\r
+  RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR, ENABLE);\r
+  \r
+  /* Initialise LEDs LD3&LD4, both off */\r
+  STM32vldiscovery_LEDInit(LED3);\r
+  STM32vldiscovery_LEDInit(LED4);\r
+  \r
+  STM32vldiscovery_LEDOff(LED3);\r
+  STM32vldiscovery_LEDOff(LED4);\r
+  \r
+  /* Initialise USER Button */\r
+  STM32vldiscovery_PBInit(BUTTON_USER, BUTTON_MODE_GPIO); \r
+  \r
+  /* Setup SysTick Timer for 1 msec interrupts  */\r
+  if (SysTick_Config(SystemCoreClock / 1000))\r
+  { \r
+    /* Capture error */ \r
+    while (1);\r
+  }\r
+\r
+  /* Enable access to the backup register => LSE can be enabled */\r
+  PWR_BackupAccessCmd(ENABLE);\r
+  \r
+  /* Enable LSE (Low Speed External Oscillation) */\r
+  RCC_LSEConfig(RCC_LSE_ON);\r
+  \r
+  /* Check the LSE Status */\r
+  while(1)\r
+  {\r
+    if(LSE_Delay < LSE_FAIL_FLAG)\r
+    {\r
+      /* check whether LSE is ready, with 4 seconds timeout */\r
+      Delay (500);\r
+      LSE_Delay += 0x10;\r
+      if(RCC_GetFlagStatus(RCC_FLAG_LSERDY) != RESET)\r
+      {\r
+        /* Set flag: LSE PASS */\r
+        LSE_Delay |= LSE_PASS_FLAG;\r
+        /* Turn Off Led4 */\r
+        STM32vldiscovery_LEDOff(LED4);\r
+        /* Disable LSE */\r
+        RCC_LSEConfig(RCC_LSE_OFF);\r
+        break;\r
+      }        \r
+    }\r
+    \r
+    /* LSE_FAIL_FLAG = 0x80 */  \r
+    else if(LSE_Delay >= LSE_FAIL_FLAG)\r
+    {          \r
+      if(RCC_GetFlagStatus(RCC_FLAG_LSERDY) == RESET)\r
+      {\r
+        /* Set flag: LSE FAIL */\r
+        LSE_Delay |= LSE_FAIL_FLAG;\r
+        /* Turn On Led4 */\r
+        STM32vldiscovery_LEDOn(LED4);\r
+      }        \r
+      /* Disable LSE */\r
+      RCC_LSEConfig(RCC_LSE_OFF);\r
+      break;\r
+    }\r
+  }\r
+  \r
+  /* main while */\r
+  while(1)\r
+  {\r
+    if(0 == STM32vldiscovery_PBGetState(BUTTON_USER))\r
+      {\r
+        if(KeyState == 1)\r
+        {\r
+           if(0 == STM32vldiscovery_PBGetState(BUTTON_USER))\r
+          {\r
+            /* USER Button released */\r
+              KeyState = 0;\r
+            /* Turn Off LED4 */\r
+              STM32vldiscovery_LEDOff(LED4);\r
+          }       \r
+        }\r
+      }\r
+    else if(STM32vldiscovery_PBGetState(BUTTON_USER))\r
+      { \r
+        if(KeyState == 0)\r
+        {\r
+           if(STM32vldiscovery_PBGetState(BUTTON_USER))\r
+          {\r
+            /* USER Button released */\r
+              KeyState = 1;\r
+            /* Turn ON LED4 */\r
+            STM32vldiscovery_LEDOn(LED4);\r
+            Delay(1000);\r
+            /* Turn OFF LED4 */\r
+            STM32vldiscovery_LEDOff(LED4);\r
+            /* BlinkSpeed: 0 -> 1 -> 2, then re-cycle */    \r
+              BlinkSpeed ++ ; \r
+          }\r
+        }\r
+      }\r
+        count++;\r
+        Delay(100);\r
+      /* BlinkSpeed: 0 */ \r
+      if(BlinkSpeed == 0)\r
+          {\r
+            if(4 == (count % 8))\r
+            STM32vldiscovery_LEDOn(LED3);\r
+            if(0 == (count % 8))\r
+            STM32vldiscovery_LEDOff(LED3);\r
+         }\r
+           /* BlinkSpeed: 1 */ \r
+           if(BlinkSpeed == 1)\r
+          {\r
+            if(2 == (count % 4))\r
+            STM32vldiscovery_LEDOn(LED3);\r
+            if(0 == (count % 4))\r
+            STM32vldiscovery_LEDOff(LED3);\r
+          }  \r
+          /* BlinkSpeed: 2 */        \r
+          if(BlinkSpeed == 2)\r
+          {\r
+            if(0 == (count % 2))\r
+            STM32vldiscovery_LEDOn(LED3);\r
+            else\r
+            STM32vldiscovery_LEDOff(LED3);     \r
+          }     \r
+          /* BlinkSpeed: 3 */ \r
+          else if(BlinkSpeed == 3)\r
+        BlinkSpeed = 0;\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  Inserts a delay time.\r
+  * @param  nTime: specifies the delay time length, in milliseconds.\r
+  * @retval None\r
+  */\r
+void Delay(uint32_t nTime)\r
+{ \r
+  TimingDelay = nTime;\r
+\r
+  while(TimingDelay != 0);\r
+}\r
+\r
+/**\r
+  * @brief  Decrements the TimingDelay variable.\r
+  * @param  None\r
+  * @retval None\r
+  */\r
+void TimingDelay_Decrement(void)\r
+{\r
+  if (TimingDelay != 0x00)\r
+  { \r
+    TimingDelay--;\r
+  }\r
+}\r
+\r
+#ifdef  USE_FULL_ASSERT\r
+/**\r
+  * @brief  Reports the name of the source file and the source line number\r
+  *         where the assert_param error has occurred.\r
+  * @param  file: pointer to the source file name\r
+  * @param  line: assert_param error line source number\r
+  * @retval None\r
+  */\r
+void assert_failed(uint8_t* file, uint32_t line)\r
+{ \r
+  /* User can add his own implementation to report the file name and line number,\r
+     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */\r
+\r
+  /* Infinite loop */\r
+  while (1)\r
+  {\r
+  }\r
+}\r
+#endif\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r

diff --git a/example/32vl_factory_demo/stm32f10x_conf.h b/example/32vl_factory_demo/stm32f10x_conf.h
new file mode 100644 (file)
index 0000000..706b92e
--- /dev/null
+++ b/example/32vl_factory_demo/stm32f10x_conf.h
@@ -0,0 +1,76 @@
+/**\r
+  ******************************************************************************\r
+  * @file    Demo/inc/stm32f10x_conf.h \r
+  * @author  MCD Application Team\r
+  * @version V1.0.0\r
+  * @date    09/13/2010\r
+  * @brief   Library configuration file.\r
+  ******************************************************************************\r
+  * @copy\r
+  *\r
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+  *\r
+  * <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+  */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F10x_CONF_H\r
+#define __STM32F10x_CONF_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+/* Uncomment the line below to enable peripheral header file inclusion */\r
+/* #include "stm32f10x_adc.h" */\r
+/* #include "stm32f10x_bkp.h" */\r
+/* #include "stm32f10x_can.h" */\r
+/* #include "stm32f10x_crc.h" */\r
+/* #include "stm32f10x_dac.h" */\r
+/* #include "stm32f10x_dbgmcu.h" */\r
+/* #include "stm32f10x_dma.h" */\r
+#include "stm32f10x_exti.h"\r
+#include "stm32f10x_flash.h"\r
+/* #include "stm32f10x_fsmc.h" */\r
+#include "stm32f10x_gpio.h"\r
+/* #include "stm32f10x_i2c.h" */\r
+/* #include "stm32f10x_iwdg.h" */\r
+#include "stm32f10x_pwr.h"\r
+#include "stm32f10x_rcc.h"\r
+/* #include "stm32f10x_rtc.h" */\r
+/* #include "stm32f10x_sdio.h" */\r
+/* #include "stm32f10x_spi.h" */\r
+/* #include "stm32f10x_tim.h" */\r
+/* #include "stm32f10x_usart.h" */\r
+/* #include "stm32f10x_wwdg.h" */\r
+#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+/* Exported constants --------------------------------------------------------*/\r
+/* Uncomment the line below to expanse the "assert_param" macro in the \r
+   Standard Peripheral Library drivers code */\r
+/* #define USE_FULL_ASSERT    1 */\r
+\r
+/* Exported macro ------------------------------------------------------------*/\r
+#ifdef  USE_FULL_ASSERT\r
+\r
+/**\r
+  * @brief  The assert_param macro is used for function's parameters check.\r
+  * @param  expr: If expr is false, it calls assert_failed function\r
+  *   which reports the name of the source file and the source\r
+  *   line number of the call that failed. \r
+  *   If expr is true, it returns no value.\r
+  * @retval None\r
+  */\r
+  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))\r
+/* Exported functions ------------------------------------------------------- */\r
+  void assert_failed(uint8_t* file, uint32_t line);\r
+#else\r
+  #define assert_param(expr) ((void)0)\r
+#endif /* USE_FULL_ASSERT */\r
+\r
+#endif /* __STM32F10x_CONF_H */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r

diff --git a/example/32vl_factory_demo/stm32f10x_it.c b/example/32vl_factory_demo/stm32f10x_it.c
new file mode 100644 (file)
index 0000000..c103527
--- /dev/null
+++ b/example/32vl_factory_demo/stm32f10x_it.c
@@ -0,0 +1,160 @@
+/**\r
+  ******************************************************************************\r
+  * @file    Demo/src/stm32f10x_it.c \r
+  * @author  MCD Application Team\r
+  * @version V1.0.0\r
+  * @date    09/13/2010\r
+  * @brief   Main Interrupt Service Routines.\r
+  *          This file provides template for all exceptions handler and peripherals\r
+  *          interrupt service routine.\r
+  ******************************************************************************\r
+  * @copy\r
+  *\r
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+  *\r
+  * <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+  */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_it.h"\r
+void TimingDelay_Decrement(void);\r
+/** @addtogroup Demo\r
+  * @{\r
+  */\r
+\r
+/* Private typedef -----------------------------------------------------------*/\r
+/* Private define ------------------------------------------------------------*/\r
+/* Private macro -------------------------------------------------------------*/\r
+/* Private variables ---------------------------------------------------------*/\r
+/* Private function prototypes -----------------------------------------------*/\r
+/* Private functions ---------------------------------------------------------*/\r
+\r
+/******************************************************************************/\r
+/*            Cortex-M3 Processor Exceptions Handlers                         */\r
+/******************************************************************************/\r
+\r
+/**\r
+  * @brief  This function handles NMI exception.\r
+  * @param  None\r
+  * @retval None\r
+  */\r
+void NMI_Handler(void)\r
+{\r
+}\r
+\r
+/**\r
+  * @brief  This function handles Hard Fault exception.\r
+  * @param  None\r
+  * @retval None\r
+  */\r
+void HardFault_Handler(void)\r
+{\r
+  /* Go to infinite loop when Hard Fault exception occurs */\r
+  while (1)\r
+  {\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  This function handles Memory Manage exception.\r
+  * @param  None\r
+  * @retval None\r
+  */\r
+void MemManage_Handler(void)\r
+{\r
+  /* Go to infinite loop when Memory Manage exception occurs */\r
+  while (1)\r
+  {\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  This function handles Bus Fault exception.\r
+  * @param  None\r
+  * @retval None\r
+  */\r
+void BusFault_Handler(void)\r
+{\r
+  /* Go to infinite loop when Bus Fault exception occurs */\r
+  while (1)\r
+  {\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  This function handles Usage Fault exception.\r
+  * @param  None\r
+  * @retval None\r
+  */\r
+void UsageFault_Handler(void)\r
+{\r
+  /* Go to infinite loop when Usage Fault exception occurs */\r
+  while (1)\r
+  {\r
+  }\r
+}\r
+\r
+/**\r
+  * @brief  This function handles SVCall exception.\r
+  * @param  None\r
+  * @retval None\r
+  */\r
+void SVC_Handler(void)\r
+{\r
+}\r
+\r
+/**\r
+  * @brief  This function handles Debug Monitor exception.\r
+  * @param  None\r
+  * @retval None\r
+  */\r
+void DebugMon_Handler(void)\r
+{\r
+}\r
+\r
+/**\r
+  * @brief  This function handles PendSV_Handler exception.\r
+  * @param  None\r
+  * @retval None\r
+  */\r
+void PendSV_Handler(void)\r
+{\r
+}\r
+\r
+/**\r
+  * @brief  This function handles SysTick Handler.\r
+  * @param  None\r
+  * @retval None\r
+  */\r
+void SysTick_Handler(void)\r
+{\r
+  TimingDelay_Decrement();\r
+}\r
+\r
+/******************************************************************************/\r
+/*                 STM32F10x Peripherals Interrupt Handlers                   */\r
+/*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */\r
+/*  available peripheral interrupt handler's name please refer to the startup */\r
+/*  file (startup_stm32f10x_xx.s).                                            */\r
+/******************************************************************************/\r
+\r
+/**\r
+  * @brief  This function handles PPP interrupt request.\r
+  * @param  None\r
+  * @retval None\r
+  */\r
+/*void PPP_IRQHandler(void)\r
+{\r
+}*/\r
+\r
+\r
+/**\r
+  * @}\r
+  */ \r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r

diff --git a/example/32vl_factory_demo/stm32f10x_it.h b/example/32vl_factory_demo/stm32f10x_it.h
new file mode 100644 (file)
index 0000000..e8d2b31
--- /dev/null
+++ b/example/32vl_factory_demo/stm32f10x_it.h
@@ -0,0 +1,46 @@
+/**\r
+  ******************************************************************************\r
+  * @file    Demo/inc/stm32f10x_it.h \r
+  * @author  MCD  Team\r
+  * @version V1.0.0\r
+  * @date    09/13/2010\r
+  * @brief   This file contains the headers of the interrupt handlers.\r
+  ******************************************************************************\r
+  * @copy\r
+  *\r
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+  *\r
+  * <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+  */\r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F10x_IT_H\r
+#define __STM32F10x_IT_H\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x.h"\r
+\r
+/* Exported types ------------------------------------------------------------*/\r
+extern vu32 TickValue;\r
+/* Exported constants --------------------------------------------------------*/\r
+/* Exported macro ------------------------------------------------------------*/\r
+/* Exported functions ------------------------------------------------------- */\r
+\r
+void NMI_Handler(void);\r
+void HardFault_Handler(void);\r
+void MemManage_Handler(void);\r
+void BusFault_Handler(void);\r
+void UsageFault_Handler(void);\r
+void SVC_Handler(void);\r
+void DebugMon_Handler(void);\r
+void PendSV_Handler(void);\r
+void SysTick_Handler(void);\r
+\r
+#endif /* __STM32F10x_IT_H */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r

diff --git a/example/32vl_factory_demo/system_stm32f10x.c b/example/32vl_factory_demo/system_stm32f10x.c
new file mode 100644 (file)
index 0000000..aed930e
--- /dev/null
+++ b/example/32vl_factory_demo/system_stm32f10x.c
@@ -0,0 +1,1019 @@
+/**\r
+  ******************************************************************************\r
+  * @file    system_stm32f10x.c\r
+  * @author  MCD Application Team\r
+  * @version V3.3.0\r
+  * @date    04/16/2010\r
+  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.\r
+  ******************************************************************************  \r
+  *\r
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+  *\r
+  * <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+  ******************************************************************************\r
+  */\r
+\r
+/** @addtogroup CMSIS\r
+  * @{\r
+  */\r
+\r
+/** @addtogroup stm32f10x_system\r
+  * @{\r
+  */  \r
+  \r
+/** @addtogroup STM32F10x_System_Private_Includes\r
+  * @{\r
+  */\r
+\r
+#include "stm32f10x.h"\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @addtogroup STM32F10x_System_Private_TypesDefinitions\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @addtogroup STM32F10x_System_Private_Defines\r
+  * @{\r
+  */\r
+\r
+/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)\r
+   frequency (after reset the HSI is used as SYSCLK source)\r
+   \r
+   IMPORTANT NOTE:\r
+   ============== \r
+   1. After each device reset the HSI is used as System clock source.\r
+\r
+   2. Please make sure that the selected System clock doesn't exceed your device's\r
+      maximum frequency.\r
+      \r
+   3. If none of the define below is enabled, the HSI is used as System clock\r
+    source.\r
+\r
+   4. The System clock configuration functions provided within this file assume that:\r
+        - For Low and Medium density Value line devices an external 8MHz crystal \r
+          is used to drive the System clock.\r
+        - For Low, Medium and High density devices an external 8MHz crystal is\r
+          used to drive the System clock.\r
+        - For Connectivity line devices an external 25MHz crystal is used to drive\r
+          the System clock.\r
+     If you are using different crystal you have to adapt those functions accordingly.\r
+    */\r
+    \r
+#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) \r
+/* #define SYSCLK_FREQ_HSE    HSE_Value */\r
+ #define SYSCLK_FREQ_24MHz  24000000\r
+#else\r
+/* #define SYSCLK_FREQ_HSE    HSE_Value */\r
+/* #define SYSCLK_FREQ_24MHz  24000000 */ \r
+/* #define SYSCLK_FREQ_36MHz  36000000 */\r
+/* #define SYSCLK_FREQ_48MHz  48000000 */\r
+/* #define SYSCLK_FREQ_56MHz  56000000 */\r
+#define SYSCLK_FREQ_72MHz  72000000\r
+#endif\r
+\r
+/*!< Uncomment the following line if you need to use external SRAM mounted\r
+     on STM3210E-EVAL board (STM32 High density and XL-density devices) as data memory  */ \r
+#if defined (STM32F10X_HD) || (defined STM32F10X_XL)\r
+/* #define DATA_IN_ExtSRAM */\r
+#endif\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @addtogroup STM32F10x_System_Private_Macros\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @addtogroup STM32F10x_System_Private_Variables\r
+  * @{\r
+  */\r
+\r
+/*******************************************************************************\r
+*  Clock Definitions\r
+*******************************************************************************/\r
+#ifdef SYSCLK_FREQ_HSE\r
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */\r
+#elif defined SYSCLK_FREQ_24MHz\r
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */\r
+#elif defined SYSCLK_FREQ_36MHz\r
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */\r
+#elif defined SYSCLK_FREQ_48MHz\r
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */\r
+#elif defined SYSCLK_FREQ_56MHz\r
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */\r
+#elif defined SYSCLK_FREQ_72MHz\r
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */\r
+#else /*!< HSI Selected as System Clock source */\r
+  uint32_t SystemCoreClock         = HSI_Value;        /*!< System Clock Frequency (Core Clock) */\r
+#endif\r
+\r
+__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @addtogroup STM32F10x_System_Private_FunctionPrototypes\r
+  * @{\r
+  */\r
+\r
+static void SetSysClock(void);\r
+\r
+#ifdef SYSCLK_FREQ_HSE\r
+  static void SetSysClockToHSE(void);\r
+#elif defined SYSCLK_FREQ_24MHz\r
+  static void SetSysClockTo24(void);\r
+#elif defined SYSCLK_FREQ_36MHz\r
+  static void SetSysClockTo36(void);\r
+#elif defined SYSCLK_FREQ_48MHz\r
+  static void SetSysClockTo48(void);\r
+#elif defined SYSCLK_FREQ_56MHz\r
+  static void SetSysClockTo56(void);  \r
+#elif defined SYSCLK_FREQ_72MHz\r
+  static void SetSysClockTo72(void);\r
+#endif\r
+\r
+#ifdef DATA_IN_ExtSRAM\r
+  static void SystemInit_ExtMemCtl(void); \r
+#endif /* DATA_IN_ExtSRAM */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @addtogroup STM32F10x_System_Private_Functions\r
+  * @{\r
+  */\r
+\r
+/**\r
+  * @brief  Setup the microcontroller system\r
+  *         Initialize the Embedded Flash Interface, the PLL and update the \r
+  *         SystemCoreClock variable.\r
+  * @note   This function should be used only after reset.\r
+  * @param  None\r
+  * @retval None\r
+  */\r
+void SystemInit (void)\r
+{\r
+  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */\r
+  /* Set HSION bit */\r
+  RCC->CR |= (uint32_t)0x00000001;\r
+\r
+  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */\r
+#ifndef STM32F10X_CL\r
+  RCC->CFGR &= (uint32_t)0xF8FF0000;\r
+#else\r
+  RCC->CFGR &= (uint32_t)0xF0FF0000;\r
+#endif /* STM32F10X_CL */   \r
+  \r
+  /* Reset HSEON, CSSON and PLLON bits */\r
+  RCC->CR &= (uint32_t)0xFEF6FFFF;\r
+\r
+  /* Reset HSEBYP bit */\r
+  RCC->CR &= (uint32_t)0xFFFBFFFF;\r
+\r
+  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */\r
+  RCC->CFGR &= (uint32_t)0xFF80FFFF;\r
+\r
+#ifdef STM32F10X_CL\r
+  /* Reset PLL2ON and PLL3ON bits */\r
+  RCC->CR &= (uint32_t)0xEBFFFFFF;\r
+\r
+  /* Disable all interrupts and clear pending bits  */\r
+  RCC->CIR = 0x00FF0000;\r
+\r
+  /* Reset CFGR2 register */\r
+  RCC->CFGR2 = 0x00000000;\r
+#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) \r
+  /* Disable all interrupts and clear pending bits  */\r
+  RCC->CIR = 0x009F0000;\r
+\r
+  /* Reset CFGR2 register */\r
+  RCC->CFGR2 = 0x00000000;      \r
+#else\r
+  /* Disable all interrupts and clear pending bits  */\r
+  RCC->CIR = 0x009F0000;\r
+#endif /* STM32F10X_CL */\r
+    \r
+#if defined (STM32F10X_HD) || (defined STM32F10X_XL)\r
+  #ifdef DATA_IN_ExtSRAM\r
+    SystemInit_ExtMemCtl(); \r
+  #endif /* DATA_IN_ExtSRAM */\r
+#endif \r
+\r
+  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */\r
+  /* Configure the Flash Latency cycles and enable prefetch buffer */\r
+  SetSysClock();\r
+}\r
+\r
+/**\r
+  * @brief  Update SystemCoreClock according to Clock Register Values\r
+  * @note   None\r
+  * @param  None\r
+  * @retval None\r
+  */\r
+void SystemCoreClockUpdate (void)\r
+{\r
+  uint32_t tmp = 0, pllmull = 0, pllsource = 0;\r
+\r
+#ifdef  STM32F10X_CL\r
+  uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;\r
+#endif /* STM32F10X_CL */\r
+\r
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL)\r
+  uint32_t prediv1factor = 0;\r
+#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL */\r
+    \r
+  /* Get SYSCLK source -------------------------------------------------------*/\r
+  tmp = RCC->CFGR & RCC_CFGR_SWS;\r
+  \r
+  switch (tmp)\r
+  {\r
+    case 0x00:  /* HSI used as system clock */\r
+      SystemCoreClock = HSI_Value;\r
+      break;\r
+    case 0x04:  /* HSE used as system clock */\r
+      SystemCoreClock = HSE_Value;\r
+      break;\r
+    case 0x08:  /* PLL used as system clock */\r
+\r
+      /* Get PLL clock source and multiplication factor ----------------------*/\r
+      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;\r
+      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;\r
+      \r
+#ifndef STM32F10X_CL      \r
+      pllmull = ( pllmull >> 18) + 2;\r
+      \r
+      if (pllsource == 0x00)\r
+      {\r
+        /* HSI oscillator clock divided by 2 selected as PLL clock entry */\r
+        SystemCoreClock = (HSI_Value >> 1) * pllmull;\r
+      }\r
+      else\r
+      {\r
+ #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL)\r
+       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;\r
+       /* HSE oscillator clock selected as PREDIV1 clock entry */\r
+       SystemCoreClock = (HSE_Value / prediv1factor) * pllmull; \r
+ #else\r
+        /* HSE selected as PLL clock entry */\r
+        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)\r
+        {/* HSE oscillator clock divided by 2 */\r
+          SystemCoreClock = (HSE_Value >> 1) * pllmull;\r
+        }\r
+        else\r
+        {\r
+          SystemCoreClock = HSE_Value * pllmull;\r
+        }\r
+ #endif\r
+      }\r
+#else\r
+      pllmull = pllmull >> 18;\r
+      \r
+      if (pllmull != 0x0D)\r
+      {\r
+         pllmull += 2;\r
+      }\r
+      else\r
+      { /* PLL multiplication factor = PLL input clock * 6.5 */\r
+        pllmull = 13 / 2; \r
+      }\r
+            \r
+      if (pllsource == 0x00)\r
+      {\r
+        /* HSI oscillator clock divided by 2 selected as PLL clock entry */\r
+        SystemCoreClock = (HSI_Value >> 1) * pllmull;\r
+      }\r
+      else\r
+      {/* PREDIV1 selected as PLL clock entry */\r
+        \r
+        /* Get PREDIV1 clock source and division factor */\r
+        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;\r
+        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;\r
+        \r
+        if (prediv1source == 0)\r
+        { \r
+          /* HSE oscillator clock selected as PREDIV1 clock entry */\r
+          SystemCoreClock = (HSE_Value / prediv1factor) * pllmull;          \r
+        }\r
+        else\r
+        {/* PLL2 clock selected as PREDIV1 clock entry */\r
+          \r
+          /* Get PREDIV2 division factor and PLL2 multiplication factor */\r
+          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;\r
+          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; \r
+          SystemCoreClock = (((HSE_Value / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         \r
+        }\r
+      }\r
+#endif /* STM32F10X_CL */ \r
+      break;\r
+\r
+    default:\r
+      SystemCoreClock = HSI_Value;\r
+      break;\r
+  }\r
+  \r
+  /* Compute HCLK clock frequency ----------------*/\r
+  /* Get HCLK prescaler */\r
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];\r
+  /* HCLK clock frequency */\r
+  SystemCoreClock >>= tmp;  \r
+}\r
+\r
+/**\r
+  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.\r
+  * @param  None\r
+  * @retval None\r
+  */\r
+static void SetSysClock(void)\r
+{\r
+#ifdef SYSCLK_FREQ_HSE\r
+  SetSysClockToHSE();\r
+#elif defined SYSCLK_FREQ_24MHz\r
+  SetSysClockTo24();\r
+#elif defined SYSCLK_FREQ_36MHz\r
+  SetSysClockTo36();\r
+#elif defined SYSCLK_FREQ_48MHz\r
+  SetSysClockTo48();\r
+#elif defined SYSCLK_FREQ_56MHz\r
+  SetSysClockTo56();  \r
+#elif defined SYSCLK_FREQ_72MHz\r
+  SetSysClockTo72();\r
+#endif\r
+ \r
+ /* If none of the define above is enabled, the HSI is used as System clock\r
+    source (default after reset) */ \r
+}\r
+\r
+/**\r
+  * @brief  Setup the external memory controller. Called in startup_stm32f10x.s \r
+  *          before jump to __main\r
+  * @param  None\r
+  * @retval None\r
+  */ \r
+#ifdef DATA_IN_ExtSRAM\r
+/**\r
+  * @brief  Setup the external memory controller. \r
+  *         Called in startup_stm32f10x_xx.s/.c before jump to main.\r
+  *          This function configures the external SRAM mounted on STM3210E-EVAL\r
+  *         board (STM32 High density devices). This SRAM will be used as program\r
+  *         data memory (including heap and stack).\r
+  * @param  None\r
+  * @retval None\r
+  */ \r
+void SystemInit_ExtMemCtl(void) \r
+{\r
+/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is \r
+  required, then adjust the Register Addresses */\r
+\r
+  /* Enable FSMC clock */\r
+  RCC->AHBENR = 0x00000114;\r
+  \r
+  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */  \r
+  RCC->APB2ENR = 0x000001E0;\r
+  \r
+/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/\r
+/*----------------  SRAM Address lines configuration -------------------------*/\r
+/*----------------  NOE and NWE configuration --------------------------------*/  \r
+/*----------------  NE3 configuration ----------------------------------------*/\r
+/*----------------  NBL0, NBL1 configuration ---------------------------------*/\r
+  \r
+  GPIOD->CRL = 0x44BB44BB;  \r
+  GPIOD->CRH = 0xBBBBBBBB;\r
+\r
+  GPIOE->CRL = 0xB44444BB;  \r
+  GPIOE->CRH = 0xBBBBBBBB;\r
+\r
+  GPIOF->CRL = 0x44BBBBBB;  \r
+  GPIOF->CRH = 0xBBBB4444;\r
+\r
+  GPIOG->CRL = 0x44BBBBBB;  \r
+  GPIOG->CRH = 0x44444B44;\r
+   \r
+/*----------------  FSMC Configuration ---------------------------------------*/  \r
+/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/\r
+  \r
+  FSMC_Bank1->BTCR[4] = 0x00001011;\r
+  FSMC_Bank1->BTCR[5] = 0x00000200;\r
+}\r
+#endif /* DATA_IN_ExtSRAM */\r
+\r
+#ifdef SYSCLK_FREQ_HSE\r
+/**\r
+  * @brief  Selects HSE as System clock source and configure HCLK, PCLK2\r
+  *          and PCLK1 prescalers.\r
+  * @note   This function should be used only after reset.\r
+  * @param  None\r
+  * @retval None\r
+  */\r
+static void SetSysClockToHSE(void)\r
+{\r
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;\r
+  \r
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    \r
+  /* Enable HSE */    \r
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);\r
+ \r
+  /* Wait till HSE is ready and if Time out is reached exit */\r
+  do\r
+  {\r
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;\r
+    StartUpCounter++;  \r
+  } while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut));\r
+\r
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)\r
+  {\r
+    HSEStatus = (uint32_t)0x01;\r
+  }\r
+  else\r
+  {\r
+    HSEStatus = (uint32_t)0x00;\r
+  }  \r
+\r
+  if (HSEStatus == (uint32_t)0x01)\r
+  {\r
+\r
+#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL \r
+    /* Enable Prefetch Buffer */\r
+    FLASH->ACR |= FLASH_ACR_PRFTBE;\r
+\r
+    /* Flash 0 wait state */\r
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);\r
+\r
+#ifndef STM32F10X_CL\r
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;\r
+#else\r
+    if (HSE_Value <= 24000000)\r
+       {\r
+      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;\r
+       }\r
+       else\r
+       {\r
+      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;\r
+       }\r
+#endif /* STM32F10X_CL */\r
+#endif\r
+ \r
+    /* HCLK = SYSCLK */\r
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;\r
+      \r
+    /* PCLK2 = HCLK */\r
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;\r
+    \r
+    /* PCLK1 = HCLK */\r
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;\r
+    \r
+    /* Select HSE as system clock source */\r
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));\r
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;    \r
+\r
+    /* Wait till HSE is used as system clock source */\r
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)\r
+    {\r
+    }\r
+  }\r
+  else\r
+  { /* If HSE fails to start-up, the application will have wrong clock \r
+         configuration. User can add here some code to deal with this error */\r
+  }  \r
+}\r
+#elif defined SYSCLK_FREQ_24MHz\r
+/**\r
+  * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2 \r
+  *          and PCLK1 prescalers.\r
+  * @note   This function should be used only after reset.\r
+  * @param  None\r
+  * @retval None\r
+  */\r
+static void SetSysClockTo24(void)\r
+{\r
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;\r
+  \r
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    \r
+  /* Enable HSE */    \r
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);\r
+ \r
+  /* Wait till HSE is ready and if Time out is reached exit */\r
+  do\r
+  {\r
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;\r
+    StartUpCounter++;  \r
+  } while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut));\r
+\r
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)\r
+  {\r
+    HSEStatus = (uint32_t)0x01;\r
+  }\r
+  else\r
+  {\r
+    HSEStatus = (uint32_t)0x00;\r
+  }  \r
+\r
+  if (HSEStatus == (uint32_t)0x01)\r
+  {\r
+#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL \r
+    /* Enable Prefetch Buffer */\r
+    FLASH->ACR |= FLASH_ACR_PRFTBE;\r
+\r
+    /* Flash 0 wait state */\r
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);\r
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    \r
+#endif\r
+ \r
+    /* HCLK = SYSCLK */\r
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;\r
+      \r
+    /* PCLK2 = HCLK */\r
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;\r
+    \r
+    /* PCLK1 = HCLK */\r
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;\r
+    \r
+#ifdef STM32F10X_CL\r
+    /* Configure PLLs ------------------------------------------------------*/\r
+    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ \r
+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);\r
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | \r
+                            RCC_CFGR_PLLMULL6); \r
+\r
+    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */\r
+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */       \r
+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |\r
+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);\r
+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |\r
+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);\r
+  \r
+    /* Enable PLL2 */\r
+    RCC->CR |= RCC_CR_PLL2ON;\r
+    /* Wait till PLL2 is ready */\r
+    while((RCC->CR & RCC_CR_PLL2RDY) == 0)\r
+    {\r
+    }   \r
+#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL)\r
+    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */\r
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));\r
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);\r
+#else    \r
+    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */\r
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));\r
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);\r
+#endif /* STM32F10X_CL */\r
+\r
+    /* Enable PLL */\r
+    RCC->CR |= RCC_CR_PLLON;\r
+\r
+    /* Wait till PLL is ready */\r
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)\r
+    {\r
+    }\r
+\r
+    /* Select PLL as system clock source */\r
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));\r
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    \r
+\r
+    /* Wait till PLL is used as system clock source */\r
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)\r
+    {\r
+    }\r
+  }\r
+  else\r
+  { /* If HSE fails to start-up, the application will have wrong clock \r
+         configuration. User can add here some code to deal with this error */\r
+  } \r
+}\r
+#elif defined SYSCLK_FREQ_36MHz\r
+/**\r
+  * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2 \r
+  *          and PCLK1 prescalers. \r
+  * @note   This function should be used only after reset.\r
+  * @param  None\r
+  * @retval None\r
+  */\r
+static void SetSysClockTo36(void)\r
+{\r
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;\r
+  \r
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    \r
+  /* Enable HSE */    \r
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);\r
+ \r
+  /* Wait till HSE is ready and if Time out is reached exit */\r
+  do\r
+  {\r
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;\r
+    StartUpCounter++;  \r
+  } while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut));\r
+\r
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)\r
+  {\r
+    HSEStatus = (uint32_t)0x01;\r
+  }\r
+  else\r
+  {\r
+    HSEStatus = (uint32_t)0x00;\r
+  }  \r
+\r
+  if (HSEStatus == (uint32_t)0x01)\r
+  {\r
+    /* Enable Prefetch Buffer */\r
+    FLASH->ACR |= FLASH_ACR_PRFTBE;\r
+\r
+    /* Flash 1 wait state */\r
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);\r
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    \r
+ \r
+    /* HCLK = SYSCLK */\r
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;\r
+      \r
+    /* PCLK2 = HCLK */\r
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;\r
+    \r
+    /* PCLK1 = HCLK */\r
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;\r
+    \r
+#ifdef STM32F10X_CL\r
+    /* Configure PLLs ------------------------------------------------------*/\r
+    \r
+    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ \r
+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);\r
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | \r
+                            RCC_CFGR_PLLMULL9); \r
+\r
+       /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */\r
+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */\r
+        \r
+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |\r
+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);\r
+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |\r
+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);\r
+  \r
+    /* Enable PLL2 */\r
+    RCC->CR |= RCC_CR_PLL2ON;\r
+    /* Wait till PLL2 is ready */\r
+    while((RCC->CR & RCC_CR_PLL2RDY) == 0)\r
+    {\r
+    }\r
+    \r
+#else    \r
+    /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */\r
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));\r
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);\r
+#endif /* STM32F10X_CL */\r
+\r
+    /* Enable PLL */\r
+    RCC->CR |= RCC_CR_PLLON;\r
+\r
+    /* Wait till PLL is ready */\r
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)\r
+    {\r
+    }\r
+\r
+    /* Select PLL as system clock source */\r
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));\r
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    \r
+\r
+    /* Wait till PLL is used as system clock source */\r
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)\r
+    {\r
+    }\r
+  }\r
+  else\r
+  { /* If HSE fails to start-up, the application will have wrong clock \r
+         configuration. User can add here some code to deal with this error */\r
+  } \r
+}\r
+#elif defined SYSCLK_FREQ_48MHz\r
+/**\r
+  * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2 \r
+  *          and PCLK1 prescalers. \r
+  * @note   This function should be used only after reset.\r
+  * @param  None\r
+  * @retval None\r
+  */\r
+static void SetSysClockTo48(void)\r
+{\r
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;\r
+  \r
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    \r
+  /* Enable HSE */    \r
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);\r
+ \r
+  /* Wait till HSE is ready and if Time out is reached exit */\r
+  do\r
+  {\r
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;\r
+    StartUpCounter++;  \r
+  } while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut));\r
+\r
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)\r
+  {\r
+    HSEStatus = (uint32_t)0x01;\r
+  }\r
+  else\r
+  {\r
+    HSEStatus = (uint32_t)0x00;\r
+  }  \r
+\r
+  if (HSEStatus == (uint32_t)0x01)\r
+  {\r
+    /* Enable Prefetch Buffer */\r
+    FLASH->ACR |= FLASH_ACR_PRFTBE;\r
+\r
+    /* Flash 1 wait state */\r
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);\r
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    \r
+ \r
+    /* HCLK = SYSCLK */\r
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;\r
+      \r
+    /* PCLK2 = HCLK */\r
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;\r
+    \r
+    /* PCLK1 = HCLK */\r
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;\r
+    \r
+#ifdef STM32F10X_CL\r
+    /* Configure PLLs ------------------------------------------------------*/\r
+    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */\r
+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */\r
+        \r
+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |\r
+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);\r
+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |\r
+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);\r
+  \r
+    /* Enable PLL2 */\r
+    RCC->CR |= RCC_CR_PLL2ON;\r
+    /* Wait till PLL2 is ready */\r
+    while((RCC->CR & RCC_CR_PLL2RDY) == 0)\r
+    {\r
+    }\r
+    \r
+   \r
+    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ \r
+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);\r
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | \r
+                            RCC_CFGR_PLLMULL6); \r
+#else    \r
+    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */\r
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));\r
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);\r
+#endif /* STM32F10X_CL */\r
+\r
+    /* Enable PLL */\r
+    RCC->CR |= RCC_CR_PLLON;\r
+\r
+    /* Wait till PLL is ready */\r
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)\r
+    {\r
+    }\r
+\r
+    /* Select PLL as system clock source */\r
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));\r
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    \r
+\r
+    /* Wait till PLL is used as system clock source */\r
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)\r
+    {\r
+    }\r
+  }\r
+  else\r
+  { /* If HSE fails to start-up, the application will have wrong clock \r
+         configuration. User can add here some code to deal with this error */\r
+  } \r
+}\r
+\r
+#elif defined SYSCLK_FREQ_56MHz\r
+/**\r
+  * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2 \r
+  *          and PCLK1 prescalers. \r
+  * @note   This function should be used only after reset.\r
+  * @param  None\r
+  * @retval None\r
+  */\r
+static void SetSysClockTo56(void)\r
+{\r
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;\r
+  \r
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   \r
+  /* Enable HSE */    \r
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);\r
+ \r
+  /* Wait till HSE is ready and if Time out is reached exit */\r
+  do\r
+  {\r
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;\r
+    StartUpCounter++;  \r
+  } while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut));\r
+\r
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)\r
+  {\r
+    HSEStatus = (uint32_t)0x01;\r
+  }\r
+  else\r
+  {\r
+    HSEStatus = (uint32_t)0x00;\r
+  }  \r
+\r
+  if (HSEStatus == (uint32_t)0x01)\r
+  {\r
+    /* Enable Prefetch Buffer */\r
+    FLASH->ACR |= FLASH_ACR_PRFTBE;\r
+\r
+    /* Flash 2 wait state */\r
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);\r
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    \r
+ \r
+    /* HCLK = SYSCLK */\r
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;\r
+      \r
+    /* PCLK2 = HCLK */\r
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;\r
+    \r
+    /* PCLK1 = HCLK */\r
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;\r
+\r
+#ifdef STM32F10X_CL\r
+    /* Configure PLLs ------------------------------------------------------*/\r
+    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */\r
+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */\r
+        \r
+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |\r
+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);\r
+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |\r
+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);\r
+  \r
+    /* Enable PLL2 */\r
+    RCC->CR |= RCC_CR_PLL2ON;\r
+    /* Wait till PLL2 is ready */\r
+    while((RCC->CR & RCC_CR_PLL2RDY) == 0)\r
+    {\r
+    }\r
+    \r
+   \r
+    /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ \r
+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);\r
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | \r
+                            RCC_CFGR_PLLMULL7); \r
+#else     \r
+    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */\r
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));\r
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);\r
+\r
+#endif /* STM32F10X_CL */\r
+\r
+    /* Enable PLL */\r
+    RCC->CR |= RCC_CR_PLLON;\r
+\r
+    /* Wait till PLL is ready */\r
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)\r
+    {\r
+    }\r
+\r
+    /* Select PLL as system clock source */\r
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));\r
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    \r
+\r
+    /* Wait till PLL is used as system clock source */\r
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)\r
+    {\r
+    }\r
+  }\r
+  else\r
+  { /* If HSE fails to start-up, the application will have wrong clock \r
+         configuration. User can add here some code to deal with this error */\r
+  } \r
+}\r
+\r
+#elif defined SYSCLK_FREQ_72MHz\r
+/**\r
+  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2 \r
+  *          and PCLK1 prescalers. \r
+  * @note   This function should be used only after reset.\r
+  * @param  None\r
+  * @retval None\r
+  */\r
+static void SetSysClockTo72(void)\r
+{\r
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;\r
+  \r
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    \r
+  /* Enable HSE */    \r
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);\r
+ \r
+  /* Wait till HSE is ready and if Time out is reached exit */\r
+  do\r
+  {\r
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;\r
+    StartUpCounter++;  \r
+  } while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut));\r
+\r
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)\r
+  {\r
+    HSEStatus = (uint32_t)0x01;\r
+  }\r
+  else\r
+  {\r
+    HSEStatus = (uint32_t)0x00;\r
+  }  \r
+\r
+  if (HSEStatus == (uint32_t)0x01)\r
+  {\r
+    /* Enable Prefetch Buffer */\r
+    FLASH->ACR |= FLASH_ACR_PRFTBE;\r
+\r
+    /* Flash 2 wait state */\r
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);\r
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    \r
+\r
+ \r
+    /* HCLK = SYSCLK */\r
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;\r
+      \r
+    /* PCLK2 = HCLK */\r
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;\r
+    \r
+    /* PCLK1 = HCLK */\r
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;\r
+\r
+#ifdef STM32F10X_CL\r
+    /* Configure PLLs ------------------------------------------------------*/\r
+    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */\r
+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */\r
+        \r
+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |\r
+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);\r
+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |\r
+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);\r
+  \r
+    /* Enable PLL2 */\r
+    RCC->CR |= RCC_CR_PLL2ON;\r
+    /* Wait till PLL2 is ready */\r
+    while((RCC->CR & RCC_CR_PLL2RDY) == 0)\r
+    {\r
+    }\r
+    \r
+   \r
+    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ \r
+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);\r
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | \r
+                            RCC_CFGR_PLLMULL9); \r
+#else    \r
+    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */\r
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |\r
+                                        RCC_CFGR_PLLMULL));\r
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);\r
+#endif /* STM32F10X_CL */\r
+\r
+    /* Enable PLL */\r
+    RCC->CR |= RCC_CR_PLLON;\r
+\r
+    /* Wait till PLL is ready */\r
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)\r
+    {\r
+    }\r
+    \r
+    /* Select PLL as system clock source */\r
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));\r
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    \r
+\r
+    /* Wait till PLL is used as system clock source */\r
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)\r
+    {\r
+    }\r
+  }\r
+  else\r
+  { /* If HSE fails to start-up, the application will have wrong clock \r
+         configuration. User can add here some code to deal with this error */\r
+  }\r
+}\r
+#endif\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/**\r
+  * @}\r
+  */\r
+  \r
+/**\r
+  * @}\r
+  */    \r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r