static inline uint32_t read_flash_cr(stlink_t *sl) {
uint32_t res;
- if(sl->chip_id==STM32F4_CHIP_ID)
+ if(sl->chip_id==STM32_CHIPID_F4)
res = stlink_read_debug32(sl, FLASH_F4_CR);
else
res = stlink_read_debug32(sl, FLASH_CR);
static inline unsigned int is_flash_locked(stlink_t *sl) {
/* return non zero for true */
- if(sl->chip_id==STM32F4_CHIP_ID)
+ if(sl->chip_id==STM32_CHIPID_F4)
return read_flash_cr(sl) & (1 << FLASH_F4_CR_LOCK);
else
return read_flash_cr(sl) & (1 << FLASH_CR_LOCK);
an invalid sequence results in a definitive lock of
the FPEC block until next reset.
*/
- if(sl->chip_id==STM32F4_CHIP_ID) {
+ if(sl->chip_id==STM32_CHIPID_F4) {
stlink_write_debug32(sl, FLASH_F4_KEYR, FLASH_KEY1);
stlink_write_debug32(sl, FLASH_F4_KEYR, FLASH_KEY2);
}
}
static void lock_flash(stlink_t *sl) {
- if(sl->chip_id==STM32F4_CHIP_ID) {
+ if(sl->chip_id==STM32_CHIPID_F4) {
const uint32_t n = read_flash_cr(sl) | (1 << FLASH_F4_CR_LOCK);
stlink_write_debug32(sl, FLASH_F4_CR, n);
}
static void set_flash_cr_pg(stlink_t *sl) {
- if(sl->chip_id==STM32F4_CHIP_ID) {
+ if(sl->chip_id==STM32_CHIPID_F4) {
uint32_t x = read_flash_cr(sl);
x |= (1 << FLASH_CR_PG);
stlink_write_debug32(sl, FLASH_F4_CR, x);
static void __attribute__((unused)) clear_flash_cr_pg(stlink_t *sl) {
const uint32_t n = read_flash_cr(sl) & ~(1 << FLASH_CR_PG);
- if(sl->chip_id==STM32F4_CHIP_ID)
+ if(sl->chip_id==STM32_CHIPID_F4)
stlink_write_debug32(sl, FLASH_F4_CR, n);
else
stlink_write_debug32(sl, FLASH_CR, n);
}
static void set_flash_cr_mer(stlink_t *sl) {
- if(sl->chip_id == STM32F4_CHIP_ID)
+ if(sl->chip_id == STM32_CHIPID_F4)
stlink_write_debug32(sl, FLASH_F4_CR,
stlink_read_debug32(sl, FLASH_F4_CR) | (1 << FLASH_CR_MER));
else
}
static void __attribute__((unused)) clear_flash_cr_mer(stlink_t *sl) {
- if(sl->chip_id == STM32F4_CHIP_ID)
+ if(sl->chip_id == STM32_CHIPID_F4)
stlink_write_debug32(sl, FLASH_F4_CR,
stlink_read_debug32(sl, FLASH_F4_CR) & ~(1 << FLASH_CR_MER));
else
}
static void set_flash_cr_strt(stlink_t *sl) {
- if(sl->chip_id == STM32F4_CHIP_ID)
+ if(sl->chip_id == STM32_CHIPID_F4)
{
uint32_t x = read_flash_cr(sl);
x |= (1 << FLASH_F4_CR_STRT);
static inline uint32_t read_flash_sr(stlink_t *sl) {
uint32_t res;
- if(sl->chip_id==STM32F4_CHIP_ID)
+ if(sl->chip_id==STM32_CHIPID_F4)
res = stlink_read_debug32(sl, FLASH_F4_SR);
else
res = stlink_read_debug32(sl, FLASH_SR);
}
static inline unsigned int is_flash_busy(stlink_t *sl) {
- if(sl->chip_id==STM32F4_CHIP_ID)
+ if(sl->chip_id==STM32_CHIPID_F4)
return read_flash_sr(sl) & (1 << FLASH_F4_SR_BSY);
else
return read_flash_sr(sl) & (1 << FLASH_SR_BSY);
}
uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr){
- if(sl->chip_id == STM32F4_CHIP_ID) {
+ if(sl->chip_id == STM32_CHIPID_F4) {
uint32_t sector=calculate_F4_sectornum(flashaddr);
if (sector<4) sl->flash_pgsz=0x4000;
else if(sector<5) sl->flash_pgsz=0x10000;
*/
int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr)
{
- if (sl->chip_id == STM32F4_CHIP_ID)
+ if (sl->chip_id == STM32_CHIPID_F4)
{
/* wait for ongoing op to finish */
wait_flash_busy(sl);
ILOG("Finished erasing %d pages of %d (%#x) bytes\n",
page_count, sl->flash_pgsz, sl->flash_pgsz);
- if (sl->chip_id == STM32F4_CHIP_ID) {
+ if (sl->chip_id == STM32_CHIPID_F4) {
/* todo: check write operation */
/* First unlock the cr */
fprintf(stdout, "\r");
if ((off % sl->flash_pgsz) > (sl->flash_pgsz -5)) {
- fprintf(stdout, "\r%3u/%u pages written",
+ fprintf(stdout, "\r%3zd/%3zd pages written",
off/sl->flash_pgsz, len/sl->flash_pgsz);
fflush(stdout);
}
#define CM3_REG_FP_COMP0 0xE0002008
/* cortex core ids */
+ // TODO clean this up...
#define STM32VL_CORE_ID 0x1ba01477
#define STM32L_CORE_ID 0x2ba01477
#define STM32F4_CORE_ID 0x2ba01477
-
+#define CORE_M3_R1 0x1BA00477
+#define CORE_M3_R2 0x4BA00477
+#define CORE_M4_R0 0x2BA01477
+
+/*
+ * Chip IDs are explained in the appropriate programming manual for the
+ * DBGMCU_IDCODE register (0xE0042000)
+ */
// stm32 chipids, only lower 12 bits..
#define STM32_CHIPID_F1_MEDIUM 0x410
#define STM32_CHIPID_F2 0x411
#define STM32_FLASH_BASE 0x08000000
#define STM32_SRAM_BASE 0x20000000
-/*
- * Chip IDs are explained in the appropriate programming manual for the
- * DBGMCU_IDCODE register (0xE0042000)
- */
-#define CORE_M3_R1 0x1BA00477
-#define CORE_M3_R2 0x4BA00477
-#define CORE_M4_R0 0x2BA01477
-
-/* using chip id for F4 ident, since core id is same as F1 */
-#define STM32F4_CHIP_ID 0x413
-
/* Cortex™-M3 Technical Reference Manual */
/* Debug Halting Control and Status Register */
#define DHCSR 0xe000edf0