}
// FIXME - hardcoded to usb....
- stlink_t *sl =stlink_open_usb(argv[2], 10);
+ stlink_t *sl = stlink_open_usb(argv[2], 10);
if (sl == NULL)
return 1;
static void init_code_breakpoints(stlink_t *sl) {
memset(sl->q_buf, 0, 4);
sl->q_buf[0] = 0x03; // KEY | ENABLE
- stlink_write_mem32(sl, 0xe0002000, 4);
+ stlink_write_mem32(sl, CM3_REG_FP_CTRL, 4);
+ printf("KARL - should read back as 0x03, not 60 02 00 00\n");
+ stlink_read_mem32(sl, CM3_REG_FP_CTRL, 4);
memset(sl->q_buf, 0, 4);
for(int i = 0; i < CODE_BREAK_NUM; i++) {
code_breaks[i].type = 0;
- stlink_write_mem32(sl, 0xe0002008 + i * 4, 4);
+ stlink_write_mem32(sl, CM3_REG_FP_COMP0 + i * 4, 4);
}
}
// cortex m3 technical reference manual
#define CM3_REG_CPUID 0xE000ED00
+#define CM3_REG_FP_CTRL 0xE0002000
+#define CM3_REG_FP_COMP0 0xE0002008
typedef struct {
uint32_t r[16];
for (off = 0; off < 16; off += 4)
stlink_read_mem32(sl, sram_base + off, 4);
- printf("-- read_mem, cpuid\n");
- stlink_read_mem32(sl, 0xe000e008, 4); // ACTLR
+ printf("FP_CTRL\n");
+ stlink_read_mem32(sl, CM3_REG_FP_CTRL, 4);
+
// no idea what reg this is.. */
/* stlink_read_mem32(sl, 0xe000ed90, 4);
// no idea what register this is...