CFLAGS=-g -O2 -mlittle-endian -mthumb
ifeq ($(CONFIG_STM32L_DISCOVERY), 1)
- CFLAGS+=-mcpu=cortex-m3 -DCONFIG_STM32L_DISCOVERY
+ CFLAGS+=-mcpu=cortex-m3 -DCONFIG_STM32L_DISCOVERY=1
else ifeq ($(CONFIG_STM32VL_DISCOVERY), 1)
CFLAGS+=-mcpu=cortex-m3 -DCONFIG_STM32VL_DISCOVERY=1
else ifeq ($(CONFIG_STM32F4_DISCOVERY), 1)
/* do the copy by 1k blocks */
for (off = 0; off < size; off += 1024) {
size_t read_size = 1024;
+ size_t rounded_size;
if ((off + read_size) > size)
- read_size = off + read_size;
+ read_size = size - off;
/* round size if needed */
- if (read_size & 3)
- read_size = (read_size + 4) & ~(3);
+ rounded_size = read_size;
+ if (rounded_size & 3)
+ rounded_size = (rounded_size + 4) & ~(3);
- stlink_read_mem32(sl, addr + off, read_size);
+ stlink_read_mem32(sl, addr + off, rounded_size);
if (write(fd, sl->q_buf, read_size) != (ssize_t) read_size) {
fprintf(stderr, "write() != read_size\n");
sl->core_stat = STLINK_CORE_STAT_UNKNOWN;
- /* flash memory settings */
- sl->flash_base = STM32_FLASH_BASE;
- sl->flash_size = STM32_FLASH_SIZE;
- sl->flash_pgsz = STM32_FLASH_PGSZ;
-
- /* system memory */
- sl->sys_base = STM32_SYSTEM_BASE;
- sl->sys_size = STM32_SYSTEM_SIZE;
-
- /* sram memory settings */
- sl->sram_base = STM32_SRAM_BASE;
- sl->sram_size = STM32L_SRAM_SIZE;
-
if (libusb_init(&(slu->libusb_ctx))) {
fprintf(stderr, "failed to init libusb context, wrong version of libraries?\n");
goto on_error;
stlink_exit_dfu_mode(sl);
}
stlink_version(sl);
+
+ /* per device family initialization */
+ stlink_core_id(sl);
+ if (sl->core_id == 0x2ba01477) /* stm32l */ {
+
+ /* flash memory settings */
+ sl->flash_base = STM32_FLASH_BASE;
+ sl->flash_size = STM32_FLASH_SIZE;
+ sl->flash_pgsz = STM32L_FLASH_PGSZ;
+
+ /* system memory */
+ sl->sys_base = STM32_SYSTEM_BASE;
+ sl->sys_size = STM32_SYSTEM_SIZE;
+
+ /* sram memory settings */
+ sl->sram_base = STM32_SRAM_BASE;
+ sl->sram_size = STM32L_SRAM_SIZE;
+
+ } else /* stm32vl */ {
+
+ /* flash memory settings */
+ sl->flash_base = STM32_FLASH_BASE;
+ sl->flash_size = STM32_FLASH_SIZE;
+ sl->flash_pgsz = STM32_FLASH_PGSZ;
+
+ /* system memory */
+ sl->sys_base = STM32_SYSTEM_BASE;
+ sl->sys_size = STM32_SYSTEM_SIZE;
+
+ /* sram memory settings */
+ sl->sram_base = STM32_SRAM_BASE;
+ sl->sram_size = STM32_SRAM_SIZE;
+
+ }
+
error = 0;
on_libusb_error: