2 * File: stlink-common.h
3 * Bulk import from stlink-hw.h
5 * This should contain all the common top level stlink interfaces, regardless
6 * of how the backend does the work....
9 #ifndef STLINK_COMMON_H
10 #define STLINK_COMMON_H
18 // Max data transfer size.
19 // 6kB = max mem32_read block, 8kB sram
20 //#define Q_BUF_LEN 96
21 #define Q_BUF_LEN (1024 * 100)
23 // st-link vendor cmd's
24 #define USB_ST_VID 0x0483
25 #define USB_STLINK_PID 0x3744
26 #define USB_STLINK_32L_PID 0x3748
28 // STLINK_DEBUG_RESETSYS, etc:
29 #define STLINK_OK 0x80
30 #define STLINK_FALSE 0x81
31 #define STLINK_CORE_RUNNING 0x80
32 #define STLINK_CORE_HALTED 0x81
33 #define STLINK_CORE_STAT_UNKNOWN -1
35 #define STLINK_GET_VERSION 0xf1
36 #define STLINK_GET_CURRENT_MODE 0xf5
38 #define STLINK_DEBUG_COMMAND 0xF2
39 #define STLINK_DFU_COMMAND 0xF3
40 #define STLINK_DFU_EXIT 0x07
41 // enter dfu could be 0x08?
43 // STLINK_GET_CURRENT_MODE
44 #define STLINK_DEV_DFU_MODE 0x00
45 #define STLINK_DEV_MASS_MODE 0x01
46 #define STLINK_DEV_DEBUG_MODE 0x02
47 #define STLINK_DEV_UNKNOWN_MODE -1
50 #define STLINK_DEBUG_ENTER 0x20
51 #define STLINK_DEBUG_EXIT 0x21
52 #define STLINK_DEBUG_READCOREID 0x22
53 #define STLINK_DEBUG_GETSTATUS 0x01
54 #define STLINK_DEBUG_FORCEDEBUG 0x02
55 #define STLINK_DEBUG_RESETSYS 0x03
56 #define STLINK_DEBUG_READALLREGS 0x04
57 #define STLINK_DEBUG_READREG 0x05
58 #define STLINK_DEBUG_WRITEREG 0x06
59 #define STLINK_DEBUG_READMEM_32BIT 0x07
60 #define STLINK_DEBUG_WRITEMEM_32BIT 0x08
61 #define STLINK_DEBUG_RUNCORE 0x09
62 #define STLINK_DEBUG_STEPCORE 0x0a
63 #define STLINK_DEBUG_SETFP 0x0b
64 #define STLINK_DEBUG_WRITEMEM_8BIT 0x0d
65 #define STLINK_DEBUG_CLEARFP 0x0e
66 #define STLINK_DEBUG_WRITEDEBUGREG 0x0f
67 #define STLINK_DEBUG_ENTER_SWD 0xa3
68 #define STLINK_DEBUG_ENTER_JTAG 0x00
70 // TODO - possible poor names...
71 #define STLINK_SWD_ENTER 0x30
72 #define STLINK_SWD_READCOREID 0x32 // TBD
73 #define STLINK_JTAG_WRITEDEBUG_32BIT 0x35
74 #define STLINK_JTAG_READDEBUG_32BIT 0x36
75 #define STLINK_JTAG_DRIVE_NRST 0x3c
76 #define STLINK_JTAG_DRIVE_NRST 0x3c
78 // cortex m3 technical reference manual
79 #define CM3_REG_CPUID 0xE000ED00
80 #define CM3_REG_FP_CTRL 0xE0002000
81 #define CM3_REG_FP_COMP0 0xE0002008
84 // TODO clean this up...
85 #define STM32VL_CORE_ID 0x1ba01477
86 #define STM32L_CORE_ID 0x2ba01477
87 #define STM32F4_CORE_ID 0x2ba01477
88 #define CORE_M3_R1 0x1BA00477
89 #define CORE_M3_R2 0x4BA00477
90 #define CORE_M4_R0 0x2BA01477
93 * Chip IDs are explained in the appropriate programming manual for the
94 * DBGMCU_IDCODE register (0xE0042000)
96 // stm32 chipids, only lower 12 bits..
97 #define STM32_CHIPID_F1_MEDIUM 0x410
98 #define STM32_CHIPID_F2 0x411
99 #define STM32_CHIPID_F1_LOW 0x412
100 #define STM32_CHIPID_F4 0x413
101 #define STM32_CHIPID_F1_HIGH 0x414
102 #define STM32_CHIPID_L1_MEDIUM 0x416
103 #define STM32_CHIPID_L1_MEDIUM_PLUS 0x427
104 #define STM32_CHIPID_L1_HIGH 0x436
105 #define STM32_CHIPID_F1_CONN 0x418
106 #define STM32_CHIPID_F1_VL_MEDIUM 0x420
107 #define STM32_CHIPID_F1_VL_HIGH 0x428
108 #define STM32_CHIPID_F1_XL 0x430
110 // Constant STM32 memory map figures
111 #define STM32_FLASH_BASE 0x08000000
112 #define STM32_SRAM_BASE 0x20000000
114 /* Cortex™-M3 Technical Reference Manual */
115 /* Debug Halting Control and Status Register */
116 #define DHCSR 0xe000edf0
117 #define DBGKEY 0xa05f0000
119 /* Enough space to hold both a V2 command or a V1 command packaged as generic scsi*/
122 typedef struct chip_params_ {
125 uint32_t flash_size_reg;
126 uint32_t flash_pagesize;
128 uint32_t bootrom_base, bootrom_size;
132 // These maps are from a combination of the Programming Manuals, and
133 // also the Reference manuals. (flash size reg is normally in ref man)
134 static const chip_params_t devices[] = {
137 .description = "F1 Medium-density device",
138 .flash_size_reg = 0x1ffff7e0,
139 .flash_pagesize = 0x400,
141 .bootrom_base = 0x1ffff000,
142 .bootrom_size = 0x800
146 .description = "F2 device",
147 .flash_size_reg = 0, /* no flash size reg found in the docs! */
148 .flash_pagesize = 0x20000,
149 .sram_size = 0x20000,
150 .bootrom_base = 0x1fff0000,
151 .bootrom_size = 0x7800
155 .description = "F1 Low-density device",
156 .flash_size_reg = 0x1ffff7e0,
157 .flash_pagesize = 0x400,
159 .bootrom_base = 0x1ffff000,
160 .bootrom_size = 0x800
164 .description = "F4 device",
165 .flash_size_reg = 0x1FFF7A10, //RM0090 error same as unique ID
166 .flash_pagesize = 0x4000,
167 .sram_size = 0x30000,
168 .bootrom_base = 0x1fff0000,
169 .bootrom_size = 0x7800
173 .description = "F1 High-density device",
174 .flash_size_reg = 0x1ffff7e0,
175 .flash_pagesize = 0x800,
176 .sram_size = 0x10000,
177 .bootrom_base = 0x1ffff000,
178 .bootrom_size = 0x800
181 // This ignores the EEPROM! (and uses the page erase size,
182 // not the sector write protection...)
184 .description = "L1 Med-density device",
185 .flash_size_reg = 0x1ff8004c,
186 .flash_pagesize = 0x100,
188 .bootrom_base = 0x1ff00000,
189 .bootrom_size = 0x1000
193 .description = "F1 Connectivity line device",
194 .flash_size_reg = 0x1ffff7e0,
195 .flash_pagesize = 0x800,
196 .sram_size = 0x10000,
197 .bootrom_base = 0x1fffb000,
198 .bootrom_size = 0x4800
202 .description = "F1 Medium-density Value Line device",
203 .flash_size_reg = 0x1ffff7e0,
204 .flash_pagesize = 0x400,
206 .bootrom_base = 0x1ffff000,
207 .bootrom_size = 0x800
210 // This ignores the EEPROM! (and uses the page erase size,
211 // not the sector write protection...)
213 .description = "L1 Med-density device plus",
214 .flash_size_reg = 0x1ff800cc,
215 .flash_pagesize = 0x100,
217 .bootrom_base = 0x1ff00000,
218 .bootrom_size = 0x1000
222 .description = "F1 High-density value line device",
223 .flash_size_reg = 0x1ffff7e0,
224 .flash_pagesize = 0x800,
226 .bootrom_base = 0x1ffff000,
227 .bootrom_size = 0x800
231 .description = "F1 XL-density device",
232 .flash_size_reg = 0x1ffff7e0,
233 .flash_pagesize = 0x800,
234 .sram_size = 0x18000,
235 .bootrom_base = 0x1fffe000,
236 .bootrom_size = 0x1800
239 // This ignores the EEPROM! (and uses the page erase size,
240 // not the sector write protection...)
242 .description = "L1 High-density device",
243 .flash_size_reg = 0x1ff8004c,
244 .flash_pagesize = 0x100,
246 .bootrom_base = 0x1ff00000,
247 .bootrom_size = 0x1000
261 typedef uint32_t stm32_addr_t;
263 typedef struct _cortex_m3_cpuid_ {
264 uint16_t implementer_id;
270 typedef struct stlink_version_ {
278 typedef struct flash_loader {
279 stm32_addr_t loader_addr; /* loader sram adddr */
280 stm32_addr_t buf_addr; /* buffer sram address */
283 enum transport_type {
284 TRANSPORT_TYPE_ZERO = 0,
285 TRANSPORT_TYPE_LIBSG,
286 TRANSPORT_TYPE_LIBUSB,
287 TRANSPORT_TYPE_INVALID
290 typedef struct _stlink stlink_t;
292 typedef struct _stlink_backend {
293 void (*close) (stlink_t * sl);
294 void (*exit_debug_mode) (stlink_t * sl);
295 void (*enter_swd_mode) (stlink_t * sl);
296 void (*enter_jtag_mode) (stlink_t * stl);
297 void (*exit_dfu_mode) (stlink_t * stl);
298 void (*core_id) (stlink_t * stl);
299 void (*reset) (stlink_t * stl);
300 void (*jtag_reset) (stlink_t * stl, int value);
301 void (*run) (stlink_t * stl);
302 void (*status) (stlink_t * stl);
303 void (*version) (stlink_t *sl);
304 uint32_t (*read_debug32) (stlink_t *sl, uint32_t addr);
305 void (*read_mem32) (stlink_t *sl, uint32_t addr, uint16_t len);
306 void (*write_debug32) (stlink_t *sl, uint32_t addr, uint32_t data);
307 void (*write_mem32) (stlink_t *sl, uint32_t addr, uint16_t len);
308 void (*write_mem8) (stlink_t *sl, uint32_t addr, uint16_t len);
309 void (*read_all_regs) (stlink_t *sl, reg * regp);
310 void (*read_reg) (stlink_t *sl, int r_idx, reg * regp);
311 void (*write_reg) (stlink_t *sl, uint32_t reg, int idx);
312 void (*step) (stlink_t * stl);
313 int (*current_mode) (stlink_t * stl);
314 void (*force_debug) (stlink_t *sl);
318 struct _stlink_backend *backend;
321 // Room for the command header
322 unsigned char c_buf[C_BUF_LEN];
323 // Data transferred from or to device
324 unsigned char q_buf[Q_BUF_LEN];
327 // transport layer verboseness: 0 for no debug info, 10 for lots
333 #define STM32_FLASH_PGSZ 1024
334 #define STM32L_FLASH_PGSZ 256
336 #define STM32F4_FLASH_PGSZ 16384
337 #define STM32F4_FLASH_SIZE (128 * 1024 * 8)
339 stm32_addr_t flash_base;
344 #define STM32_SRAM_SIZE (8 * 1024)
345 #define STM32L_SRAM_SIZE (16 * 1024)
346 stm32_addr_t sram_base;
350 stm32_addr_t sys_base;
353 struct stlink_version_ version;
356 //stlink_t* stlink_quirk_open(const char *dev_name, const int verbose);
358 // delegated functions...
359 void stlink_enter_swd_mode(stlink_t *sl);
360 void stlink_enter_jtag_mode(stlink_t *sl);
361 void stlink_exit_debug_mode(stlink_t *sl);
362 void stlink_exit_dfu_mode(stlink_t *sl);
363 void stlink_close(stlink_t *sl);
364 uint32_t stlink_core_id(stlink_t *sl);
365 void stlink_reset(stlink_t *sl);
366 void stlink_jtag_reset(stlink_t *sl, int value);
367 void stlink_run(stlink_t *sl);
368 void stlink_status(stlink_t *sl);
369 void stlink_version(stlink_t *sl);
370 uint32_t stlink_read_debug32(stlink_t *sl, uint32_t addr);
371 void stlink_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len);
372 void stlink_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data);
373 void stlink_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len);
374 void stlink_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len);
375 void stlink_read_all_regs(stlink_t *sl, reg *regp);
376 void stlink_read_reg(stlink_t *sl, int r_idx, reg *regp);
377 void stlink_write_reg(stlink_t *sl, uint32_t reg, int idx);
378 void stlink_step(stlink_t *sl);
379 int stlink_current_mode(stlink_t *sl);
380 void stlink_force_debug(stlink_t *sl);
384 int stlink_erase_flash_mass(stlink_t* sl);
385 int stlink_write_flash(stlink_t* sl, stm32_addr_t address, uint8_t* data, unsigned length);
386 int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr);
387 int stlink_fwrite_sram(stlink_t *sl, const char* path, stm32_addr_t addr);
388 int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, unsigned length);
391 uint32_t stlink_chip_id(stlink_t *sl);
392 void stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid);
394 // privates, publics, the rest....
395 // TODO sort what is private, and what is not
396 int stlink_erase_flash_page(stlink_t* sl, stm32_addr_t flashaddr);
397 uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr);
398 uint16_t read_uint16(const unsigned char *c, const int pt);
399 void stlink_core_stat(stlink_t *sl);
400 void stlink_print_data(stlink_t *sl);
401 unsigned int is_bigendian(void);
402 uint32_t read_uint32(const unsigned char *c, const int pt);
403 void write_uint32(unsigned char* buf, uint32_t ui);
404 void write_uint16(unsigned char* buf, uint16_t ui);
405 unsigned int is_core_halted(stlink_t *sl);
406 int write_buffer_to_sram(stlink_t *sl, flash_loader_t* fl, const uint8_t* buf, size_t size);
407 int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size);
408 int stlink_fread(stlink_t* sl, const char* path, stm32_addr_t addr, size_t size);
409 int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, const uint8_t* buf, size_t size);
410 int stlink_load_device_params(stlink_t *sl);
414 #include "stlink-sg.h"
415 #include "stlink-usb.h"
423 #endif /* STLINK_COMMON_H */