10 #include <sys/types.h>
15 #include "stlink-common.h"
16 #include "uglylogging.h"
18 #define LOG_TAG __FILE__
19 #define DLOG(format, args...) ugly_log(UDEBUG, LOG_TAG, format, ## args)
20 #define ILOG(format, args...) ugly_log(UINFO, LOG_TAG, format, ## args)
21 #define WLOG(format, args...) ugly_log(UWARN, LOG_TAG, format, ## args)
22 #define fatal(format, args...) ugly_log(UFATAL, LOG_TAG, format, ## args)
24 /* todo: stm32l15xxx flash memory, pm0062 manual */
26 /* stm32f FPEC flash controller interface, pm0063 manual */
27 // TODO - all of this needs to be abstracted out....
28 #define FLASH_REGS_ADDR 0x40022000
29 #define FLASH_REGS_SIZE 0x28
31 #define FLASH_ACR (FLASH_REGS_ADDR + 0x00)
32 #define FLASH_KEYR (FLASH_REGS_ADDR + 0x04)
33 #define FLASH_SR (FLASH_REGS_ADDR + 0x0c)
34 #define FLASH_CR (FLASH_REGS_ADDR + 0x10)
35 #define FLASH_AR (FLASH_REGS_ADDR + 0x14)
36 #define FLASH_OBR (FLASH_REGS_ADDR + 0x1c)
37 #define FLASH_WRPR (FLASH_REGS_ADDR + 0x20)
39 #define FLASH_RDPTR_KEY 0x00a5
40 #define FLASH_KEY1 0x45670123
41 #define FLASH_KEY2 0xcdef89ab
43 #define FLASH_SR_BSY 0
44 #define FLASH_SR_EOP 5
47 #define FLASH_CR_PER 1
48 #define FLASH_CR_MER 2
49 #define FLASH_CR_STRT 6
50 #define FLASH_CR_LOCK 7
53 //32L = 32F1 same CoreID as 32F4!
54 #define STM32L_FLASH_REGS_ADDR ((uint32_t)0x40023c00)
55 #define STM32L_FLASH_ACR (STM32L_FLASH_REGS_ADDR + 0x00)
56 #define STM32L_FLASH_PECR (STM32L_FLASH_REGS_ADDR + 0x04)
57 #define STM32L_FLASH_PDKEYR (STM32L_FLASH_REGS_ADDR + 0x08)
58 #define STM32L_FLASH_PEKEYR (STM32L_FLASH_REGS_ADDR + 0x0c)
59 #define STM32L_FLASH_PRGKEYR (STM32L_FLASH_REGS_ADDR + 0x10)
60 #define STM32L_FLASH_OPTKEYR (STM32L_FLASH_REGS_ADDR + 0x14)
61 #define STM32L_FLASH_SR (STM32L_FLASH_REGS_ADDR + 0x18)
62 #define STM32L_FLASH_OBR (STM32L_FLASH_REGS_ADDR + 0x1c)
63 #define STM32L_FLASH_WRPR (STM32L_FLASH_REGS_ADDR + 0x20)
64 #define FLASH_L1_FPRG 10
65 #define FLASH_L1_PROG 3
69 #define FLASH_F4_REGS_ADDR ((uint32_t)0x40023c00)
70 #define FLASH_F4_KEYR (FLASH_F4_REGS_ADDR + 0x04)
71 #define FLASH_F4_OPT_KEYR (FLASH_F4_REGS_ADDR + 0x08)
72 #define FLASH_F4_SR (FLASH_F4_REGS_ADDR + 0x0c)
73 #define FLASH_F4_CR (FLASH_F4_REGS_ADDR + 0x10)
74 #define FLASH_F4_OPT_CR (FLASH_F4_REGS_ADDR + 0x14)
75 #define FLASH_F4_CR_STRT 16
76 #define FLASH_F4_CR_LOCK 31
77 #define FLASH_F4_CR_SER 1
78 #define FLASH_F4_CR_SNB 3
79 #define FLASH_F4_CR_SNB_MASK 0x38
80 #define FLASH_F4_SR_BSY 16
83 void write_uint32(unsigned char* buf, uint32_t ui) {
84 if (!is_bigendian()) { // le -> le (don't swap)
85 buf[0] = ((unsigned char*) &ui)[0];
86 buf[1] = ((unsigned char*) &ui)[1];
87 buf[2] = ((unsigned char*) &ui)[2];
88 buf[3] = ((unsigned char*) &ui)[3];
90 buf[0] = ((unsigned char*) &ui)[3];
91 buf[1] = ((unsigned char*) &ui)[2];
92 buf[2] = ((unsigned char*) &ui)[1];
93 buf[3] = ((unsigned char*) &ui)[0];
97 void write_uint16(unsigned char* buf, uint16_t ui) {
98 if (!is_bigendian()) { // le -> le (don't swap)
99 buf[0] = ((unsigned char*) &ui)[0];
100 buf[1] = ((unsigned char*) &ui)[1];
102 buf[0] = ((unsigned char*) &ui)[1];
103 buf[1] = ((unsigned char*) &ui)[0];
107 uint32_t read_uint32(const unsigned char *c, const int pt) {
109 char *p = (char *) &ui;
111 if (!is_bigendian()) { // le -> le (don't swap)
125 static uint32_t __attribute__((unused)) read_flash_rdp(stlink_t *sl) {
126 return stlink_read_debug32(sl, FLASH_WRPR) & 0xff;
129 static inline uint32_t read_flash_wrpr(stlink_t *sl) {
130 return stlink_read_debug32(sl, FLASH_WRPR);
133 static inline uint32_t read_flash_obr(stlink_t *sl) {
134 return stlink_read_debug32(sl, FLASH_OBR);
137 static inline uint32_t read_flash_cr(stlink_t *sl) {
139 if(sl->chip_id==STM32F4_CHIP_ID)
140 res = stlink_read_debug32(sl, FLASH_F4_CR);
142 res = stlink_read_debug32(sl, FLASH_CR);
144 fprintf(stdout, "CR:0x%x\n", res);
149 static inline unsigned int is_flash_locked(stlink_t *sl) {
150 /* return non zero for true */
151 if(sl->chip_id==STM32F4_CHIP_ID)
152 return read_flash_cr(sl) & (1 << FLASH_F4_CR_LOCK);
154 return read_flash_cr(sl) & (1 << FLASH_CR_LOCK);
157 static void unlock_flash(stlink_t *sl) {
158 /* the unlock sequence consists of 2 write cycles where
159 2 key values are written to the FLASH_KEYR register.
160 an invalid sequence results in a definitive lock of
161 the FPEC block until next reset.
163 if(sl->chip_id==STM32F4_CHIP_ID) {
164 stlink_write_debug32(sl, FLASH_F4_KEYR, FLASH_KEY1);
165 stlink_write_debug32(sl, FLASH_F4_KEYR, FLASH_KEY2);
168 stlink_write_debug32(sl, FLASH_KEYR, FLASH_KEY1);
169 stlink_write_debug32(sl, FLASH_KEYR, FLASH_KEY2);
174 static int unlock_flash_if(stlink_t *sl) {
175 /* unlock flash if already locked */
177 if (is_flash_locked(sl)) {
179 if (is_flash_locked(sl)) {
180 WLOG("Failed to unlock flash!\n");
184 DLOG("Successfully unlocked flash\n");
188 static void lock_flash(stlink_t *sl) {
189 if(sl->chip_id==STM32F4_CHIP_ID) {
190 const uint32_t n = read_flash_cr(sl) | (1 << FLASH_F4_CR_LOCK);
191 stlink_write_debug32(sl, FLASH_F4_CR, n);
194 /* write to 1 only. reset by hw at unlock sequence */
195 const uint32_t n = read_flash_cr(sl) | (1 << FLASH_CR_LOCK);
196 stlink_write_debug32(sl, FLASH_CR, n);
201 static void set_flash_cr_pg(stlink_t *sl) {
202 if(sl->chip_id==STM32F4_CHIP_ID) {
203 uint32_t x = read_flash_cr(sl);
204 x |= (1 << FLASH_CR_PG);
205 stlink_write_debug32(sl, FLASH_F4_CR, x);
208 const uint32_t n = 1 << FLASH_CR_PG;
209 stlink_write_debug32(sl, FLASH_CR, n);
213 static void __attribute__((unused)) clear_flash_cr_pg(stlink_t *sl) {
214 const uint32_t n = read_flash_cr(sl) & ~(1 << FLASH_CR_PG);
215 if(sl->chip_id==STM32F4_CHIP_ID)
216 stlink_write_debug32(sl, FLASH_F4_CR, n);
218 stlink_write_debug32(sl, FLASH_CR, n);
221 static void set_flash_cr_per(stlink_t *sl) {
222 const uint32_t n = 1 << FLASH_CR_PER;
223 stlink_write_debug32(sl, FLASH_CR, n);
226 static void __attribute__((unused)) clear_flash_cr_per(stlink_t *sl) {
227 const uint32_t n = read_flash_cr(sl) & ~(1 << FLASH_CR_PER);
228 stlink_write_debug32(sl, FLASH_CR, n);
231 static void set_flash_cr_mer(stlink_t *sl) {
232 const uint32_t n = 1 << FLASH_CR_MER;
233 stlink_write_debug32(sl, FLASH_CR, n);
236 static void __attribute__((unused)) clear_flash_cr_mer(stlink_t *sl) {
237 const uint32_t n = read_flash_cr(sl) & ~(1 << FLASH_CR_MER);
238 stlink_write_debug32(sl, FLASH_CR, n);
241 static void set_flash_cr_strt(stlink_t *sl) {
242 if(sl->chip_id == STM32F4_CHIP_ID)
244 uint32_t x = read_flash_cr(sl);
245 x |= (1 << FLASH_F4_CR_STRT);
246 stlink_write_debug32(sl, FLASH_F4_CR, x);
249 /* assume come on the flash_cr_per path */
250 const uint32_t n = (1 << FLASH_CR_PER) | (1 << FLASH_CR_STRT);
251 stlink_write_debug32(sl, FLASH_CR, n);
255 static inline uint32_t read_flash_acr(stlink_t *sl) {
256 return stlink_read_debug32(sl, FLASH_ACR);
259 static inline uint32_t read_flash_sr(stlink_t *sl) {
261 if(sl->chip_id==STM32F4_CHIP_ID)
262 res = stlink_read_debug32(sl, FLASH_F4_SR);
264 res = stlink_read_debug32(sl, FLASH_SR);
265 //fprintf(stdout, "SR:0x%x\n", *(uint32_t*) sl->q_buf);
269 static inline unsigned int is_flash_busy(stlink_t *sl) {
270 if(sl->chip_id==STM32F4_CHIP_ID)
271 return read_flash_sr(sl) & (1 << FLASH_F4_SR_BSY);
273 return read_flash_sr(sl) & (1 << FLASH_SR_BSY);
276 static void wait_flash_busy(stlink_t *sl) {
277 /* todo: add some delays here */
278 while (is_flash_busy(sl))
282 static inline unsigned int is_flash_eop(stlink_t *sl) {
283 return read_flash_sr(sl) & (1 << FLASH_SR_EOP);
286 static void __attribute__((unused)) clear_flash_sr_eop(stlink_t *sl) {
287 const uint32_t n = read_flash_sr(sl) & ~(1 << FLASH_SR_EOP);
288 stlink_write_debug32(sl, FLASH_SR, n);
291 static void __attribute__((unused)) wait_flash_eop(stlink_t *sl) {
292 /* todo: add some delays here */
293 while (is_flash_eop(sl) == 0)
297 static inline void write_flash_ar(stlink_t *sl, uint32_t n) {
298 stlink_write_debug32(sl, FLASH_AR, n);
301 static inline void write_flash_cr_psiz(stlink_t *sl, uint32_t n) {
302 uint32_t x = read_flash_cr(sl);
306 fprintf(stdout, "PSIZ:0x%x 0x%x\n", x, n);
308 stlink_write_debug32(sl, FLASH_F4_CR, x);
312 static inline void write_flash_cr_snb(stlink_t *sl, uint32_t n) {
313 uint32_t x = read_flash_cr(sl);
314 x &= ~FLASH_F4_CR_SNB_MASK;
315 x |= (n << FLASH_F4_CR_SNB);
316 x |= (1 << FLASH_F4_CR_SER);
318 fprintf(stdout, "SNB:0x%x 0x%x\n", x, n);
320 stlink_write_debug32(sl, FLASH_F4_CR, x);
325 static void disable_flash_read_protection(stlink_t *sl) {
326 /* erase the option byte area */
333 // Delegates to the backends...
335 void stlink_close(stlink_t *sl) {
336 DLOG("*** stlink_close ***\n");
337 sl->backend->close(sl);
341 void stlink_exit_debug_mode(stlink_t *sl) {
342 DLOG("*** stlink_exit_debug_mode ***\n");
343 stlink_write_debug32(sl, DHCSR, DBGKEY);
344 sl->backend->exit_debug_mode(sl);
347 void stlink_enter_swd_mode(stlink_t *sl) {
348 DLOG("*** stlink_enter_swd_mode ***\n");
349 sl->backend->enter_swd_mode(sl);
352 // Force the core into the debug mode -> halted state.
353 void stlink_force_debug(stlink_t *sl) {
354 DLOG("*** stlink_force_debug_mode ***\n");
355 sl->backend->force_debug(sl);
358 void stlink_exit_dfu_mode(stlink_t *sl) {
359 DLOG("*** stlink_exit_dfu_mode ***\n");
360 sl->backend->exit_dfu_mode(sl);
363 uint32_t stlink_core_id(stlink_t *sl) {
364 DLOG("*** stlink_core_id ***\n");
365 sl->backend->core_id(sl);
367 stlink_print_data(sl);
368 DLOG("core_id = 0x%08x\n", sl->core_id);
372 uint32_t stlink_chip_id(stlink_t *sl) {
373 uint32_t chip_id = stlink_read_debug32(sl, 0xE0042000);
378 * Cortex m3 tech ref manual, CPUID register description
379 * @param sl stlink context
380 * @param cpuid pointer to the result object
382 void stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid) {
383 uint32_t raw = stlink_read_debug32(sl, CM3_REG_CPUID);
384 cpuid->implementer_id = (raw >> 24) & 0x7f;
385 cpuid->variant = (raw >> 20) & 0xf;
386 cpuid->part = (raw >> 4) & 0xfff;
387 cpuid->revision = raw & 0xf;
392 * reads and decodes the flash parameters, as dynamically as possible
394 * @return 0 for success, or -1 for unsupported core type.
396 int stlink_load_device_params(stlink_t *sl) {
397 ILOG("Loading device parameters....\n");
398 const chip_params_t *params = NULL;
400 sl->core_id = stlink_core_id(sl);
401 uint32_t chip_id = stlink_chip_id(sl);
403 /* Fix chip_id for F4 rev A errata */
404 if (((chip_id & 0xFFF) == 0x411) && (sl->core_id == CORE_M4_R0)) {
408 sl->chip_id = chip_id & 0xfff;
409 for(size_t i = 0; i < sizeof(devices) / sizeof(devices[0]); i++) {
410 if(devices[i].chip_id == sl->chip_id) {
411 params = &devices[i];
415 if (params == NULL) {
416 WLOG("unknown chip id! %#x\n", chip_id);
420 // These are fixed...
421 sl->flash_base = STM32_FLASH_BASE;
422 sl->sram_base = STM32_SRAM_BASE;
424 // read flash size from hardware, if possible...
425 if (sl->chip_id == STM32_CHIPID_F2) {
426 sl->flash_size = 0; // FIXME - need to work this out some other way, just set to max possible?
427 } else if (sl->chip_id == STM32_CHIPID_F4) {
428 sl->flash_size = 0x100000; //todo: RM0090 error; size register same address as unique ID
430 uint32_t flash_size = stlink_read_debug32(sl, params->flash_size_reg) & 0xffff;
431 sl->flash_size = flash_size * 1024;
433 sl->flash_pgsz = params->flash_pagesize;
434 sl->sram_size = params->sram_size;
435 sl->sys_base = params->bootrom_base;
436 sl->sys_size = params->bootrom_size;
438 ILOG("Device connected is: %s, id %#x\n", params->description, chip_id);
439 // TODO make note of variable page size here.....
440 ILOG("SRAM size: %#x bytes (%d KiB), Flash: %#x bytes (%d KiB) in pages of %zd bytes\n",
441 sl->sram_size, sl->sram_size / 1024, sl->flash_size, sl->flash_size / 1024,
446 void stlink_reset(stlink_t *sl) {
447 DLOG("*** stlink_reset ***\n");
448 sl->backend->reset(sl);
451 void stlink_jtag_reset(stlink_t *sl, int value) {
452 DLOG("*** stlink_jtag_reset ***\n");
453 sl->backend->jtag_reset(sl, value);
456 void stlink_run(stlink_t *sl) {
457 DLOG("*** stlink_run ***\n");
458 sl->backend->run(sl);
461 void stlink_status(stlink_t *sl) {
462 DLOG("*** stlink_status ***\n");
463 sl->backend->status(sl);
464 stlink_core_stat(sl);
468 * Decode the version bits, originally from -sg, verified with usb
469 * @param sl stlink context, assumed to contain valid data in the buffer
470 * @param slv output parsed version object
472 void _parse_version(stlink_t *sl, stlink_version_t *slv) {
473 uint32_t b0 = sl->q_buf[0]; //lsb
474 uint32_t b1 = sl->q_buf[1];
475 uint32_t b2 = sl->q_buf[2];
476 uint32_t b3 = sl->q_buf[3];
477 uint32_t b4 = sl->q_buf[4];
478 uint32_t b5 = sl->q_buf[5]; //msb
480 // b0 b1 || b2 b3 | b4 b5
481 // 4b | 6b | 6b || 2B | 2B
482 // stlink_v | jtag_v | swim_v || st_vid | stlink_pid
484 slv->stlink_v = (b0 & 0xf0) >> 4;
485 slv->jtag_v = ((b0 & 0x0f) << 2) | ((b1 & 0xc0) >> 6);
486 slv->swim_v = b1 & 0x3f;
487 slv->st_vid = (b3 << 8) | b2;
488 slv->stlink_pid = (b5 << 8) | b4;
492 void stlink_version(stlink_t *sl) {
493 DLOG("*** looking up stlink version\n");
494 sl->backend->version(sl);
495 _parse_version(sl, &sl->version);
497 DLOG("st vid = 0x%04x (expect 0x%04x)\n", sl->version.st_vid, USB_ST_VID);
498 DLOG("stlink pid = 0x%04x\n", sl->version.stlink_pid);
499 DLOG("stlink version = 0x%x\n", sl->version.stlink_v);
500 DLOG("jtag version = 0x%x\n", sl->version.jtag_v);
501 DLOG("swim version = 0x%x\n", sl->version.swim_v);
502 if (sl->version.jtag_v == 0) {
503 DLOG(" notice: the firmware doesn't support a jtag/swd interface\n");
505 if (sl->version.swim_v == 0) {
506 DLOG(" notice: the firmware doesn't support a swim interface\n");
510 uint32_t stlink_read_debug32(stlink_t *sl, uint32_t addr) {
511 uint32_t data = sl->backend->read_debug32(sl, addr);
512 DLOG("*** stlink_read_debug32 %x is %#x\n", data, addr);
516 void stlink_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data) {
517 DLOG("*** stlink_write_debug32 %x to %#x\n", data, addr);
518 sl->backend->write_debug32(sl, addr, data);
521 void stlink_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) {
522 DLOG("*** stlink_write_mem32 %u bytes to %#x\n", len, addr);
524 fprintf(stderr, "Error: Data length doesn't have a 32 bit alignment: +%d byte.\n", len % 4);
527 sl->backend->write_mem32(sl, addr, len);
530 void stlink_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len) {
531 DLOG("*** stlink_read_mem32 ***\n");
532 if (len % 4 != 0) { // !!! never ever: fw gives just wrong values
533 fprintf(stderr, "Error: Data length doesn't have a 32 bit alignment: +%d byte.\n",
537 sl->backend->read_mem32(sl, addr, len);
540 void stlink_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len) {
541 DLOG("*** stlink_write_mem8 ***\n");
542 if (len > 0x40 ) { // !!! never ever: Writing more then 0x40 bytes gives unexpected behaviour
543 fprintf(stderr, "Error: Data length > 64: +%d byte.\n",
547 sl->backend->write_mem8(sl, addr, len);
550 void stlink_read_all_regs(stlink_t *sl, reg *regp) {
551 DLOG("*** stlink_read_all_regs ***\n");
552 sl->backend->read_all_regs(sl, regp);
555 void stlink_write_reg(stlink_t *sl, uint32_t reg, int idx) {
556 DLOG("*** stlink_write_reg\n");
557 sl->backend->write_reg(sl, reg, idx);
560 void stlink_read_reg(stlink_t *sl, int r_idx, reg *regp) {
561 DLOG("*** stlink_read_reg\n");
562 DLOG(" (%d) ***\n", r_idx);
564 if (r_idx > 20 || r_idx < 0) {
565 fprintf(stderr, "Error: register index must be in [0..20]\n");
569 sl->backend->read_reg(sl, r_idx, regp);
572 unsigned int is_core_halted(stlink_t *sl) {
573 /* return non zero if core is halted */
575 return sl->q_buf[0] == STLINK_CORE_HALTED;
578 void stlink_step(stlink_t *sl) {
579 DLOG("*** stlink_step ***\n");
580 sl->backend->step(sl);
583 int stlink_current_mode(stlink_t *sl) {
584 int mode = sl->backend->current_mode(sl);
586 case STLINK_DEV_DFU_MODE:
587 DLOG("stlink current mode: dfu\n");
589 case STLINK_DEV_DEBUG_MODE:
590 DLOG("stlink current mode: debug (jtag or swd)\n");
592 case STLINK_DEV_MASS_MODE:
593 DLOG("stlink current mode: mass\n");
596 DLOG("stlink mode: unknown!\n");
597 return STLINK_DEV_UNKNOWN_MODE;
603 // End of delegates.... Common code below here...
606 // http://www.ibm.com/developerworks/aix/library/au-endianc/index.html
608 // #define is_bigendian() ( (*(char*)&i) == 0 )
610 inline unsigned int is_bigendian(void) {
611 static volatile const unsigned int i = 1;
612 return *(volatile const char*) &i == 0;
615 uint16_t read_uint16(const unsigned char *c, const int pt) {
617 char *p = (char *) &ui;
619 if (!is_bigendian()) { // le -> le (don't swap)
629 // same as above with entrypoint.
631 void stlink_run_at(stlink_t *sl, stm32_addr_t addr) {
632 stlink_write_reg(sl, addr, 15); /* pc register */
636 while (is_core_halted(sl) == 0)
640 void stlink_core_stat(stlink_t *sl) {
644 switch (sl->q_buf[0]) {
645 case STLINK_CORE_RUNNING:
646 sl->core_stat = STLINK_CORE_RUNNING;
647 DLOG(" core status: running\n");
649 case STLINK_CORE_HALTED:
650 sl->core_stat = STLINK_CORE_HALTED;
651 DLOG(" core status: halted\n");
654 sl->core_stat = STLINK_CORE_STAT_UNKNOWN;
655 fprintf(stderr, " core status: unknown\n");
659 void stlink_print_data(stlink_t * sl) {
660 if (sl->q_len <= 0 || sl->verbose < UDEBUG)
663 fprintf(stdout, "data_len = %d 0x%x\n", sl->q_len, sl->q_len);
665 for (int i = 0; i < sl->q_len; i++) {
668 if (sl->q_data_dir == Q_DATA_OUT)
669 fprintf(stdout, "\n<- 0x%08x ", sl->q_addr + i);
671 fprintf(stdout, "\n-> 0x%08x ", sl->q_addr + i);
674 fprintf(stdout, " %02x", (unsigned int) sl->q_buf[i]);
676 fputs("\n\n", stdout);
679 /* memory mapped file */
681 typedef struct mapped_file {
686 #define MAPPED_FILE_INITIALIZER { NULL, 0 }
688 static int map_file(mapped_file_t* mf, const char* path) {
692 const int fd = open(path, O_RDONLY);
694 fprintf(stderr, "open(%s) == -1\n", path);
698 if (fstat(fd, &st) == -1) {
699 fprintf(stderr, "fstat() == -1\n");
703 mf->base = (uint8_t*) mmap(NULL, st.st_size, PROT_READ, MAP_SHARED, fd, 0);
704 if (mf->base == MAP_FAILED) {
705 fprintf(stderr, "mmap() == MAP_FAILED\n");
709 mf->len = st.st_size;
720 static void unmap_file(mapped_file_t * mf) {
721 munmap((void*) mf->base, mf->len);
722 mf->base = (unsigned char*) MAP_FAILED;
726 static int check_file(stlink_t* sl, mapped_file_t* mf, stm32_addr_t addr) {
729 for (off = 0; off < mf->len; off += sl->flash_pgsz) {
732 /* adjust last page size */
733 size_t cmp_size = sl->flash_pgsz;
734 if ((off + sl->flash_pgsz) > mf->len)
735 cmp_size = mf->len - off;
737 aligned_size = cmp_size;
738 if (aligned_size & (4 - 1))
739 aligned_size = (cmp_size + 4) & ~(4 - 1);
741 stlink_read_mem32(sl, addr + off, aligned_size);
743 if (memcmp(sl->q_buf, mf->base + off, cmp_size))
750 int stlink_fwrite_sram
751 (stlink_t * sl, const char* path, stm32_addr_t addr) {
752 /* write the file in sram at addr */
756 mapped_file_t mf = MAPPED_FILE_INITIALIZER;
758 if (map_file(&mf, path) == -1) {
759 fprintf(stderr, "map_file() == -1\n");
763 /* check addr range is inside the sram */
764 if (addr < sl->sram_base) {
765 fprintf(stderr, "addr too low\n");
767 } else if ((addr + mf.len) < addr) {
768 fprintf(stderr, "addr overruns\n");
770 } else if ((addr + mf.len) > (sl->sram_base + sl->sram_size)) {
771 fprintf(stderr, "addr too high\n");
773 } else if ((addr & 3) || (mf.len & 3)) {
775 fprintf(stderr, "unaligned addr or size\n");
779 /* do the copy by 1k blocks */
780 for (off = 0; off < mf.len; off += 1024) {
782 if ((off + size) > mf.len)
785 memcpy(sl->q_buf, mf.base + off, size);
787 /* round size if needed */
791 stlink_write_mem32(sl, addr + off, size);
794 /* check the file ha been written */
795 if (check_file(sl, &mf, addr) == -1) {
796 fprintf(stderr, "check_file() == -1\n");
803 stlink_write_reg(sl, stlink_read_debug32(sl, addr ),13);
804 /* Set PC to the reset routine*/
805 stlink_write_reg(sl, stlink_read_debug32(sl, addr + 4),15);
813 int stlink_fread(stlink_t* sl, const char* path, stm32_addr_t addr, size_t size) {
814 /* read size bytes from addr to file */
819 unsigned char erased_pattern =(sl->chip_id == STM32_CHIPID_L1_MEDIUM)?0:0xff;
821 const int fd = open(path, O_RDWR | O_TRUNC | O_CREAT, 00700);
823 fprintf(stderr, "open(%s) == -1\n", path);
828 size = sl->flash_size;
830 if (size > sl->flash_size)
831 size = sl->flash_size;
833 /* do the copy by 1k blocks */
834 for (off = 0; off < size; off += 1024) {
835 size_t read_size = 1024;
838 if ((off + read_size) > size)
839 read_size = size - off;
841 /* round size if needed */
842 rounded_size = read_size;
843 if (rounded_size & 3)
844 rounded_size = (rounded_size + 4) & ~(3);
846 stlink_read_mem32(sl, addr + off, rounded_size);
848 for(index = 0; index < read_size; index ++) {
849 if (sl->q_buf[index] == erased_pattern)
854 if (write(fd, sl->q_buf, read_size) != (ssize_t) read_size) {
855 fprintf(stderr, "write() != read_size\n");
860 /* Ignore NULL Bytes at end of file */
861 ftruncate(fd, size - num_empty);
872 int write_buffer_to_sram(stlink_t *sl, flash_loader_t* fl, const uint8_t* buf, size_t size) {
873 /* write the buffer right after the loader */
874 size_t chunk = size & ~0x3;
875 size_t rem = size & 0x3;
877 memcpy(sl->q_buf, buf, chunk);
878 stlink_write_mem32(sl, fl->buf_addr, chunk);
881 memcpy(sl->q_buf, buf+chunk, rem);
882 stlink_write_mem8(sl, (fl->buf_addr)+chunk, rem);
887 uint32_t calculate_F4_sectornum(uint32_t flashaddr){
888 flashaddr &= ~STM32_FLASH_BASE; //Page now holding the actual flash address
889 if (flashaddr<0x4000) return (0);
890 else if(flashaddr<0x8000) return(1);
891 else if(flashaddr<0xc000) return(2);
892 else if(flashaddr<0x10000) return(3);
893 else if(flashaddr<0x20000) return(4);
894 else return(flashaddr/0x20000)+4;
898 uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr){
899 if(sl->chip_id == STM32F4_CHIP_ID) {
900 uint32_t sector=calculate_F4_sectornum(flashaddr);
901 if (sector<4) sl->flash_pgsz=0x4000;
902 else if(sector<5) sl->flash_pgsz=0x10000;
903 else sl->flash_pgsz=0x20000;
905 return (sl->flash_pgsz);
909 * Erase a page of flash, assumes sl is fully populated with things like chip/core ids
910 * @param sl stlink context
911 * @param flashaddr an address in the flash page to erase
912 * @return 0 on success -ve on failure
914 int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr)
916 if (sl->chip_id == STM32F4_CHIP_ID)
918 /* wait for ongoing op to finish */
921 /* unlock if locked */
924 /* select the page to erase */
925 // calculate the actual page from the address
926 uint32_t sector=calculate_F4_sectornum(flashaddr);
928 fprintf(stderr, "EraseFlash - Sector:0x%x Size:0x%x\n", sector, stlink_calculate_pagesize(sl, flashaddr));
929 write_flash_cr_snb(sl, sector);
931 /* start erase operation */
932 set_flash_cr_strt(sl);
934 /* wait for completion */
937 /* relock the flash */
938 //todo: fails to program if this is in
941 fprintf(stdout, "Erase Final CR:0x%x\n", read_flash_cr(sl));
944 else if (sl->core_id == STM32L_CORE_ID)
949 /* disable pecr protection */
950 stlink_write_debug32(sl, STM32L_FLASH_PEKEYR, 0x89abcdef);
951 stlink_write_debug32(sl, STM32L_FLASH_PEKEYR, 0x02030405);
953 /* check pecr.pelock is cleared */
954 val = stlink_read_debug32(sl, STM32L_FLASH_PECR);
957 WLOG("pecr.pelock not clear (%#x)\n", val);
961 /* unlock program memory */
962 stlink_write_debug32(sl, STM32L_FLASH_PRGKEYR, 0x8c9daebf);
963 stlink_write_debug32(sl, STM32L_FLASH_PRGKEYR, 0x13141516);
965 /* check pecr.prglock is cleared */
966 val = stlink_read_debug32(sl, STM32L_FLASH_PECR);
969 WLOG("pecr.prglock not clear (%#x)\n", val);
973 /* unused: unlock the option byte block */
975 stlink_write_debug32(sl, STM32L_FLASH_OPTKEYR, 0xfbead9c8);
976 stlink_write_debug32(sl, STM32L_FLASH_OPTKEYR, 0x24252627);
978 /* check pecr.optlock is cleared */
979 val = stlink_read_debug32(sl, STM32L_FLASH_PECR);
982 fprintf(stderr, "pecr.prglock not clear\n");
987 /* set pecr.{erase,prog} */
988 val |= (1 << 9) | (1 << 3);
989 stlink_write_debug32(sl, STM32L_FLASH_PECR, val);
991 #if 0 /* fix_to_be_confirmed */
993 /* wait for sr.busy to be cleared
994 MP: Test shows that busy bit is not set here. Perhaps, PM0062 is
995 wrong and we do not need to wait here for clearing the busy bit.
996 TEXANE: ok, if experience says so and it works for you, we comment
997 it. If someone has a problem, please drop an email.
999 while ((stlink_read_debug32(sl, STM32L_FLASH_SR) & (1 << 0)) != 0)
1003 #endif /* fix_to_be_confirmed */
1005 /* write 0 to the first word of the page to be erased */
1006 stlink_write_debug32(sl, flashaddr, 0);
1008 /* MP: It is better to wait for clearing the busy bit after issuing
1009 page erase command, even though PM0062 recommends to wait before it.
1010 Test shows that a few iterations is performed in the following loop
1011 before busy bit is cleared.*/
1012 while ((stlink_read_debug32(sl, STM32L_FLASH_SR) & (1 << 0)) != 0)
1016 /* reset lock bits */
1017 val = stlink_read_debug32(sl, STM32L_FLASH_PECR)
1018 | (1 << 0) | (1 << 1) | (1 << 2);
1019 stlink_write_debug32(sl, STM32L_FLASH_PECR, val);
1021 else if (sl->core_id == STM32VL_CORE_ID)
1023 /* wait for ongoing op to finish */
1024 wait_flash_busy(sl);
1026 /* unlock if locked */
1027 unlock_flash_if(sl);
1029 /* set the page erase bit */
1030 set_flash_cr_per(sl);
1032 /* select the page to erase */
1033 write_flash_ar(sl, flashaddr);
1035 /* start erase operation, reset by hw with bsy bit */
1036 set_flash_cr_strt(sl);
1038 /* wait for completion */
1039 wait_flash_busy(sl);
1041 /* relock the flash */
1046 WLOG("unknown coreid: %x\n", sl->core_id);
1050 /* todo: verify the erased page */
1055 int stlink_erase_flash_mass(stlink_t *sl) {
1056 if (sl->chip_id == STM32_CHIPID_F4) {
1057 DLOG("(FIXME) Mass erase of STM32F4\n");
1059 else if (sl->chip_id == STM32_CHIPID_L1_MEDIUM) {
1060 /* erase each page */
1061 int i = 0, num_pages = sl->flash_size/sl->flash_pgsz;
1062 for (i = 0; i < num_pages; i++) {
1063 /* addr must be an addr inside the page */
1064 stm32_addr_t addr = sl->flash_base + i * sl->flash_pgsz;
1065 if (stlink_erase_flash_page(sl, addr) == -1) {
1066 WLOG("Failed to erase_flash_page(%#zx) == -1\n", addr);
1069 fprintf(stdout,"\rFlash page at %5d/%5d erased", i, num_pages);
1074 /* wait for ongoing op to finish */
1075 wait_flash_busy(sl);
1077 /* unlock if locked */
1078 unlock_flash_if(sl);
1080 /* set the mass erase bit */
1081 set_flash_cr_mer(sl);
1083 /* start erase operation, reset by hw with bsy bit */
1084 set_flash_cr_strt(sl);
1086 /* wait for completion */
1087 wait_flash_busy(sl);
1089 /* relock the flash */
1092 /* todo: verify the erased memory */
1097 int init_flash_loader(stlink_t *sl, flash_loader_t* fl) {
1100 /* allocate the loader in sram */
1101 if (write_loader_to_sram(sl, &fl->loader_addr, &size) == -1) {
1102 WLOG("Failed to write flash loader to sram!\n");
1106 /* allocate a one page buffer in sram right after loader */
1107 fl->buf_addr = fl->loader_addr + size;
1108 ILOG("Successfully loaded flash loader in sram\n");
1112 int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) {
1113 /* from openocd, contrib/loaders/flash/stm32.s */
1114 static const uint8_t loader_code_stm32vl[] = {
1115 0x08, 0x4c, /* ldr r4, STM32_FLASH_BASE */
1116 0x1c, 0x44, /* add r4, r3 */
1117 /* write_half_word: */
1118 0x01, 0x23, /* movs r3, #0x01 */
1119 0x23, 0x61, /* str r3, [r4, #STM32_FLASH_CR_OFFSET] */
1120 0x30, 0xf8, 0x02, 0x3b, /* ldrh r3, [r0], #0x02 */
1121 0x21, 0xf8, 0x02, 0x3b, /* strh r3, [r1], #0x02 */
1123 0xe3, 0x68, /* ldr r3, [r4, #STM32_FLASH_SR_OFFSET] */
1124 0x13, 0xf0, 0x01, 0x0f, /* tst r3, #0x01 */
1125 0xfb, 0xd0, /* beq busy */
1126 0x13, 0xf0, 0x14, 0x0f, /* tst r3, #0x14 */
1127 0x01, 0xd1, /* bne exit */
1128 0x01, 0x3a, /* subs r2, r2, #0x01 */
1129 0xf0, 0xd1, /* bne write_half_word */
1131 0x00, 0xbe, /* bkpt #0x00 */
1132 0x00, 0x20, 0x02, 0x40, /* STM32_FLASH_BASE: .word 0x40022000 */
1135 static const uint8_t loader_code_stm32l[] = {
1137 /* openocd.git/contrib/loaders/flash/stm32lx.S
1138 r0, input, dest addr
1139 r1, input, source addr
1140 r2, input, word count
1141 r3, output, word count
1147 0x51, 0xf8, 0x04, 0xcb,
1148 0x40, 0xf8, 0x04, 0xcb,
1156 const uint8_t* loader_code;
1159 if (sl->core_id == STM32L_CORE_ID) /* stm32l */
1161 loader_code = loader_code_stm32l;
1162 loader_size = sizeof(loader_code_stm32l);
1164 else if (sl->core_id == STM32VL_CORE_ID)
1166 loader_code = loader_code_stm32vl;
1167 loader_size = sizeof(loader_code_stm32vl);
1171 WLOG("unknown coreid, not sure what flash loader to use, aborting!: %x\n", sl->core_id);
1175 memcpy(sl->q_buf, loader_code, loader_size);
1176 stlink_write_mem32(sl, sl->sram_base, loader_size);
1178 *addr = sl->sram_base;
1179 *size = loader_size;
1185 int stlink_fcheck_flash(stlink_t *sl, const char* path, stm32_addr_t addr) {
1186 /* check the contents of path are at addr */
1189 mapped_file_t mf = MAPPED_FILE_INITIALIZER;
1191 if (map_file(&mf, path) == -1)
1194 res = check_file(sl, &mf, addr);
1202 * Verify addr..addr+len is binary identical to base...base+len
1203 * @param sl stlink context
1204 * @param address stm device address
1205 * @param data host side buffer to check against
1206 * @param length how much
1207 * @return 0 for success, -ve for failure
1209 int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, unsigned length) {
1211 if (sl->chip_id == STM32_CHIPID_F4) {
1212 DLOG("(FIXME)Skipping verification for F4, not enough ram (yet)\n");
1215 ILOG("Starting verification of write complete\n");
1216 for (off = 0; off < length; off += sl->flash_pgsz) {
1217 size_t aligned_size;
1219 /* adjust last page size */
1220 size_t cmp_size = sl->flash_pgsz;
1221 if ((off + sl->flash_pgsz) > length)
1222 cmp_size = length - off;
1224 aligned_size = cmp_size;
1225 if (aligned_size & (4 - 1))
1226 aligned_size = (cmp_size + 4) & ~(4 - 1);
1228 stlink_read_mem32(sl, address + off, aligned_size);
1230 if (memcmp(sl->q_buf, data + off, cmp_size)) {
1231 WLOG("Verification of flash failed at offset: %zd\n", off);
1235 ILOG("Flash written and verified! jolly good!\n");
1240 int stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned num_half_pages)
1246 ILOG("Starting Half page flash write for STM32L core id\n");
1247 /* flash loader initialization */
1248 if (init_flash_loader(sl, &fl) == -1) {
1249 WLOG("init_flash_loader() == -1\n");
1252 /* Unlock already done */
1253 val = stlink_read_debug32(sl, STM32L_FLASH_PECR);
1254 val |= (1 << FLASH_L1_FPRG);
1255 stlink_write_debug32(sl, STM32L_FLASH_PECR, val);
1257 val |= (1 << FLASH_L1_PROG);
1258 stlink_write_debug32(sl, STM32L_FLASH_PECR, val);
1259 while ((stlink_read_debug32(sl, STM32L_FLASH_SR) & (1 << 0)) != 0) {}
1261 #define L1_WRITE_BLOCK_SIZE 0x80
1262 for (count = 0; count < num_half_pages; count ++) {
1263 if (run_flash_loader(sl, &fl, addr + count * L1_WRITE_BLOCK_SIZE, base + count * L1_WRITE_BLOCK_SIZE, L1_WRITE_BLOCK_SIZE) == -1) {
1264 WLOG("l1_run_flash_loader(%#zx) failed! == -1\n", addr + count * L1_WRITE_BLOCK_SIZE);
1265 val = stlink_read_debug32(sl, STM32L_FLASH_PECR);
1266 val &= ~((1 << FLASH_L1_FPRG) |(1 << FLASH_L1_PROG));
1267 stlink_write_debug32(sl, STM32L_FLASH_PECR, val);
1270 /* wait for sr.busy to be cleared */
1271 if (sl->verbose >= 1) {
1272 /* show progress. writing procedure is slow
1273 and previous errors are misleading */
1274 fprintf(stdout, "\r%3u/%u halfpages written", count, num_half_pages);
1277 while ((stlink_read_debug32(sl, STM32L_FLASH_SR) & (1 << 0)) != 0) {
1280 fprintf(stdout, "\n");
1281 val = stlink_read_debug32(sl, STM32L_FLASH_PECR);
1282 val &= ~(1 << FLASH_L1_PROG);
1283 stlink_write_debug32(sl, STM32L_FLASH_PECR, val);
1284 val = stlink_read_debug32(sl, STM32L_FLASH_PECR);
1285 val &= ~(1 << FLASH_L1_FPRG);
1286 stlink_write_debug32(sl, STM32L_FLASH_PECR, val);
1291 int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned len) {
1294 ILOG("Attempting to write %d (%#x) bytes to stm32 address: %u (%#x)\n",
1295 len, len, addr, addr);
1296 /* check addr range is inside the flash */
1297 stlink_calculate_pagesize(sl, addr);
1298 if (addr < sl->flash_base) {
1299 WLOG("addr too low %#x < %#x\n", addr, sl->flash_base);
1301 } else if ((addr + len) < addr) {
1302 WLOG("addr overruns\n");
1304 } else if ((addr + len) > (sl->flash_base + sl->flash_size)) {
1305 WLOG("addr too high\n");
1307 } else if ((addr & 1) || (len & 1)) {
1308 WLOG("unaligned addr or size\n");
1310 } else if (addr & (sl->flash_pgsz - 1)) {
1311 WLOG("addr not a multiple of pagesize, not supported\n");
1315 // Make sure we've loaded the context with the chip details
1317 /* erase each page */
1319 for (off = 0; off < len; off += stlink_calculate_pagesize(sl, addr + off)) {
1320 /* addr must be an addr inside the page */
1321 if (stlink_erase_flash_page(sl, addr + off) == -1) {
1322 WLOG("Failed to erase_flash_page(%#zx) == -1\n", addr + off);
1325 fprintf(stdout,"\rFlash page at addr: 0x%08lx erased",
1326 (unsigned long)addr + off);
1330 fprintf(stdout,"\n");
1331 ILOG("Finished erasing %d pages of %d (%#x) bytes\n",
1332 page_count, sl->flash_pgsz, sl->flash_pgsz);
1334 if (sl->chip_id == STM32F4_CHIP_ID) {
1335 /* todo: check write operation */
1337 /* First unlock the cr */
1338 unlock_flash_if(sl);
1340 /* TODO: Check that Voltage range is 2.7 - 3.6 V */
1341 /* set parallelisim to 32 bit*/
1342 write_flash_cr_psiz(sl, 2);
1344 /* set programming mode */
1345 set_flash_cr_pg(sl);
1347 #define PROGRESS_CHUNK_SIZE 0x1000
1348 /* write a word in program memory */
1349 for (off = 0; off < len; off += sizeof(uint32_t)) {
1351 if (sl->verbose >= 1) {
1352 if ((off & (PROGRESS_CHUNK_SIZE - 1)) == 0) {
1353 /* show progress. writing procedure is slow
1354 and previous errors are misleading */
1355 const uint32_t pgnum = (off / PROGRESS_CHUNK_SIZE)+1;
1356 const uint32_t pgcount = len / PROGRESS_CHUNK_SIZE;
1357 fprintf(stdout, "Writing %ukB chunk %u out of %u\n", PROGRESS_CHUNK_SIZE/1024, pgnum, pgcount);
1361 write_uint32((unsigned char*) &data, *(uint32_t*) (base + off));
1362 stlink_write_debug32(sl, addr + off, data);
1364 /* wait for sr.busy to be cleared */
1365 wait_flash_busy(sl);
1371 #if 0 /* todo: debug mode */
1372 fprintf(stdout, "Final CR:0x%x\n", read_flash_cr(sl));
1379 else if (sl->core_id == STM32L_CORE_ID) {
1380 /* use fast word write. todo: half page. */
1383 #if 0 /* todo: check write operation */
1385 uint32_t nwrites = sl->flash_pgsz;
1389 #endif /* todo: check write operation */
1391 /* disable pecr protection */
1392 stlink_write_debug32(sl, STM32L_FLASH_PEKEYR, 0x89abcdef);
1393 stlink_write_debug32(sl, STM32L_FLASH_PEKEYR, 0x02030405);
1395 /* check pecr.pelock is cleared */
1396 val = stlink_read_debug32(sl, STM32L_FLASH_PECR);
1397 if (val & (1 << 0)) {
1398 fprintf(stderr, "pecr.pelock not clear\n");
1402 /* unlock program memory */
1403 stlink_write_debug32(sl, STM32L_FLASH_PRGKEYR, 0x8c9daebf);
1404 stlink_write_debug32(sl, STM32L_FLASH_PRGKEYR, 0x13141516);
1406 /* check pecr.prglock is cleared */
1407 val = stlink_read_debug32(sl, STM32L_FLASH_PECR);
1408 if (val & (1 << 1)) {
1409 fprintf(stderr, "pecr.prglock not clear\n");
1412 if (len > L1_WRITE_BLOCK_SIZE) {
1413 if (stm32l1_write_half_pages(sl, addr, base, len/L1_WRITE_BLOCK_SIZE) == -1){
1414 WLOG("\nwrite_half_pages failed == -1\n");
1419 /* write remainingword in program memory */
1420 for (off = (len /L1_WRITE_BLOCK_SIZE)*L1_WRITE_BLOCK_SIZE; off < len; off += sizeof(uint32_t)) {
1422 write_uint32((unsigned char*) &data, *(uint32_t*) (base + off));
1423 stlink_write_debug32(sl, addr + off, data);
1425 /* wait for sr.busy to be cleared */
1426 while ((stlink_read_debug32(sl, STM32L_FLASH_SR) & (1 << 0)) != 0) {
1429 #if 0 /* todo: check redo write operation */
1431 /* check written bytes. todo: should be on a per page basis. */
1432 data = stlink_read_debug32(sl, addr + off);
1433 if (data == *(uint32_t*)(base + off)) {
1434 /* re erase the page and redo the write operation */
1438 /* fail if successive write count too low */
1439 if (nwrites < sl->flash_pgsz) {
1440 fprintf(stderr, "writes operation failure count too high, aborting\n");
1446 /* assume addr aligned */
1447 if (off % sl->flash_pgsz) off &= ~(sl->flash_pgsz - 1);
1450 fprintf(stderr, "invalid write @0x%x(0x%x): 0x%x != 0x%x. retrying.\n",
1451 page, addr + off, read_uint32(base + off, 0), read_uint32(sl->q_buf, 0));
1453 /* reset lock bits */
1454 val = stlink_read_debug32(sl, STM32L_FLASH_PECR)
1455 | (1 << 0) | (1 << 1) | (1 << 2);
1456 stlink_write_debug32(sl, STM32L_FLASH_PECR, val);
1458 stlink_erase_flash_page(sl, page);
1463 /* increment successive writes counter */
1466 #endif /* todo: check redo write operation */
1468 fprintf(stdout, "\n");
1469 /* reset lock bits */
1470 val = stlink_read_debug32(sl, STM32L_FLASH_PECR)
1471 | (1 << 0) | (1 << 1) | (1 << 2);
1472 stlink_write_debug32(sl, STM32L_FLASH_PECR, val);
1473 } else if (sl->core_id == STM32VL_CORE_ID) {
1474 ILOG("Starting Flash write for VL core id\n");
1475 /* flash loader initialization */
1476 if (init_flash_loader(sl, &fl) == -1) {
1477 WLOG("init_flash_loader() == -1\n");
1481 int write_block_count = 0;
1482 for (off = 0; off < len; off += sl->flash_pgsz) {
1483 /* adjust last write size */
1484 size_t size = sl->flash_pgsz;
1485 if ((off + sl->flash_pgsz) > len) size = len - off;
1487 /* unlock and set programming mode */
1488 unlock_flash_if(sl);
1489 set_flash_cr_pg(sl);
1490 //DLOG("Finished setting flash cr pg, running loader!\n");
1491 if (run_flash_loader(sl, &fl, addr + off, base + off, size) == -1) {
1492 WLOG("run_flash_loader(%#zx) failed! == -1\n", addr + off);
1496 if (sl->verbose >= 1) {
1497 /* show progress. writing procedure is slow
1498 and previous errors are misleading */
1499 fprintf(stdout, "\r%3u/%lu pages written", write_block_count++, (unsigned long)len/sl->flash_pgsz);
1503 fprintf(stdout, "\n");
1505 WLOG("unknown coreid, not sure how to write: %x\n", sl->core_id);
1509 return stlink_verify_write_flash(sl, addr, base, len);
1513 * Write the given binary file into flash at address "addr"
1515 * @param path readable file path, should be binary image
1516 * @param addr where to start writing
1517 * @return 0 on success, -ve on failure.
1519 int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr) {
1520 /* write the file in flash at addr */
1522 unsigned int num_empty = 0, index;
1523 unsigned char erased_pattern =(sl->chip_id == STM32_CHIPID_L1_MEDIUM)?0:0xff;
1524 mapped_file_t mf = MAPPED_FILE_INITIALIZER;
1525 if (map_file(&mf, path) == -1) {
1526 WLOG("map_file() == -1\n");
1529 for(index = 0; index < mf.len; index ++) {
1530 if (mf.base[index] == erased_pattern)
1535 if(num_empty != 0) {
1536 ILOG("Ignoring %d bytes of Zeros at end of file\n",num_empty);
1537 mf.len -= num_empty;
1539 err = stlink_write_flash(sl, addr, mf.base, mf.len);
1541 stlink_write_reg(sl, stlink_read_debug32(sl, addr ),13);
1542 /* Set PC to the reset routine*/
1543 stlink_write_reg(sl, stlink_read_debug32(sl, addr + 4),15);
1549 int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, const uint8_t* buf, size_t size) {
1553 DLOG("Running flash loader, write address:%#x, size: %zd\n", target, size);
1554 // FIXME This can never return -1
1555 if (write_buffer_to_sram(sl, fl, buf, size) == -1) {
1557 WLOG("write_buffer_to_sram() == -1\n");
1561 if (sl->core_id == STM32L_CORE_ID) {
1563 size_t count = size / sizeof(uint32_t);
1564 if (size % sizeof(uint32_t)) ++count;
1567 stlink_write_reg(sl, target, 0); /* target */
1568 stlink_write_reg(sl, fl->buf_addr, 1); /* source */
1569 stlink_write_reg(sl, count, 2); /* count (32 bits words) */
1570 stlink_write_reg(sl, fl->loader_addr, 15); /* pc register */
1572 } else if (sl->core_id == STM32VL_CORE_ID) {
1574 size_t count = size / sizeof(uint16_t);
1575 if (size % sizeof(uint16_t)) ++count;
1578 stlink_write_reg(sl, fl->buf_addr, 0); /* source */
1579 stlink_write_reg(sl, target, 1); /* target */
1580 stlink_write_reg(sl, count, 2); /* count (16 bits half words) */
1581 stlink_write_reg(sl, 0, 3); /* flash bank 0 (input) */
1582 stlink_write_reg(sl, fl->loader_addr, 15); /* pc register */
1585 fprintf(stderr, "unknown coreid: 0x%x\n", sl->core_id);
1592 /* wait until done (reaches breakpoint) */
1593 while ((is_core_halted(sl) == 0) && (i <10000))
1599 fprintf(stderr, "run error\n");
1603 /* check written byte count */
1604 if (sl->core_id == STM32L_CORE_ID) {
1606 size_t count = size / sizeof(uint32_t);
1607 if (size % sizeof(uint32_t)) ++count;
1609 stlink_read_reg(sl, 3, &rr);
1610 if (rr.r[3] != count) {
1611 fprintf(stderr, "write error, count == %u\n", rr.r[3]);
1615 } else if (sl->core_id == STM32VL_CORE_ID) {
1617 stlink_read_reg(sl, 2, &rr);
1619 fprintf(stderr, "write error, count == %u\n", rr.r[2]);
1625 fprintf(stderr, "unknown coreid: 0x%x\n", sl->core_id);