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   1 #include "stlink.h"
   2 #include "stlink/chipid.h"
   3
   4 static const struct stlink_chipid_params devices[] = {
   5         {
   6             //RM0385 and DS10916 document was used to find these paramaters
   7             .chip_id = STLINK_CHIPID_STM32_F7,
   8             .description = "F7 device",
   9             .flash_type = FLASH_TYPE_F4,
  10             .flash_size_reg = 0x1ff0f442,      // section 41.2
  11             .flash_pagesize = 0x800,           // No flash pages
  12             .sram_size = 0x50000,              // "SRAM" byte size in hex from DS Fig 18
  13             .bootrom_base = 0x00100000,        // "System memory" starting address from DS Fig 18
  14             .bootrom_size = 0xEDC0             // "System memory" byte size in hex from DS Fig 18
  15         },
  16         { // table 2, PM0063
  17             .chip_id = STLINK_CHIPID_STM32_F1_MEDIUM,
  18             .description = "F1 Medium-density device",
  19             .flash_type = FLASH_TYPE_F0,
  20             .flash_size_reg = 0x1ffff7e0,
  21             .flash_pagesize = 0x400,
  22             .sram_size = 0x5000,
  23             .bootrom_base = 0x1ffff000,
  24             .bootrom_size = 0x800
  25         },
  26         {  // table 1, PM0059
  27             .chip_id = STLINK_CHIPID_STM32_F2,
  28             .description = "F2 device",
  29             .flash_type = FLASH_TYPE_F4,
  30             .flash_size_reg = 0x1fff7a22, /* As in RM0033 Rev 5*/
  31             .flash_pagesize = 0x20000,
  32             .sram_size = 0x20000,
  33             .bootrom_base = 0x1fff0000,
  34             .bootrom_size = 0x7800
  35         },
  36         { // PM0063
  37             .chip_id = STLINK_CHIPID_STM32_F1_LOW,
  38             .description = "F1 Low-density device",
  39             .flash_type = FLASH_TYPE_F0,
  40             .flash_size_reg = 0x1ffff7e0,
  41             .flash_pagesize = 0x400,
  42             .sram_size = 0x2800,
  43             .bootrom_base = 0x1ffff000,
  44             .bootrom_size = 0x800
  45         },
  46         {
  47             .chip_id = STLINK_CHIPID_STM32_F4,
  48             .description = "F4 device",
  49             .flash_type = FLASH_TYPE_F4,
  50             .flash_size_reg = 0x1FFF7A22,  /* As in rm0090 since Rev 2*/
  51             .flash_pagesize = 0x4000,
  52             .sram_size = 0x30000,
  53             .bootrom_base = 0x1fff0000,
  54             .bootrom_size = 0x7800
  55         },
  56         {
  57             .chip_id = STLINK_CHIPID_STM32_F4_DSI,
  58             .description = "F46x and F47x device",
  59             .flash_type = FLASH_TYPE_F4,
  60             .flash_size_reg = 0x1FFF7A22,  /* As in rm0090 since Rev 2*/
  61             .flash_pagesize = 0x4000,
  62             .sram_size = 0x40000,
  63             .bootrom_base = 0x1fff0000,
  64             .bootrom_size = 0x7800
  65         },
  66         {
  67             .chip_id = STLINK_CHIPID_STM32_F4_HD,
  68             .description = "F42x and F43x device",
  69             .flash_type = FLASH_TYPE_F4,
  70             .flash_size_reg = 0x1FFF7A22,  /* As in rm0090 since Rev 2*/
  71             .flash_pagesize = 0x4000,
  72             .sram_size = 0x40000,
  73             .bootrom_base = 0x1fff0000,
  74             .bootrom_size = 0x7800
  75         },
  76         {
  77             .chip_id = STLINK_CHIPID_STM32_F4_LP,
  78             .description = "F4 device (low power)",
  79             .flash_type = FLASH_TYPE_F4,
  80             .flash_size_reg = 0x1FFF7A22,
  81             .flash_pagesize = 0x4000,
  82             .sram_size = 0x10000,
  83             .bootrom_base = 0x1fff0000,
  84             .bootrom_size = 0x7800
  85         },
  86         {
  87             .chip_id = STLINK_CHIPID_STM32_F411RE,
  88             .description = "F4 device (low power) - stm32f411re",
  89             .flash_type = FLASH_TYPE_F4,
  90             .flash_size_reg = 0x1FFF7A22,
  91             .flash_pagesize = 0x4000,
  92             .sram_size = 0x20000,
  93             .bootrom_base = 0x1fff0000,
  94             .bootrom_size = 0x7800
  95         },
  96         {
  97             .chip_id = STLINK_CHIPID_STM32_F4_DE,
  98             .description = "F4 device (Dynamic Efficency)",
  99             .flash_type = FLASH_TYPE_F4,
 100             .flash_size_reg = 0x1FFF7A22,
 101             .flash_pagesize = 0x4000,
 102             .sram_size = 0x18000,
 103             .bootrom_base = 0x1fff0000,
 104             .bootrom_size = 0x7800
 105         },
 106         {
 107             .chip_id = STLINK_CHIPID_STM32_F1_HIGH,
 108             .description = "F1 High-density device",
 109             .flash_type = FLASH_TYPE_F0,
 110             .flash_size_reg = 0x1ffff7e0,
 111             .flash_pagesize = 0x800,
 112             .sram_size = 0x10000,
 113             .bootrom_base = 0x1ffff000,
 114             .bootrom_size = 0x800
 115         },
 116         {
 117             // This ignores the EEPROM! (and uses the page erase size,
 118             // not the sector write protection...)
 119             .chip_id = STLINK_CHIPID_STM32_L1_MEDIUM,
 120             .description = "L1 Med-density device",
 121             .flash_type = FLASH_TYPE_L0,
 122             .flash_size_reg = 0x1ff8004c,
 123             .flash_pagesize = 0x100,
 124             .sram_size = 0x4000,
 125             .bootrom_base = 0x1ff00000,
 126             .bootrom_size = 0x1000
 127         },
 128         {
 129             .chip_id = STLINK_CHIPID_STM32_L1_CAT2,
 130             .description = "L1 Cat.2 device",
 131             .flash_type = FLASH_TYPE_L0,
 132             .flash_size_reg = 0x1ff8004c,
 133             .flash_pagesize = 0x100,
 134             .sram_size = 0x8000,
 135             .bootrom_base = 0x1ff00000,
 136             .bootrom_size = 0x1000
 137         },
 138         {
 139             .chip_id = STLINK_CHIPID_STM32_L1_MEDIUM_PLUS,
 140             .description = "L1 Medium-Plus-density device",
 141             .flash_type = FLASH_TYPE_L0,
 142             .flash_size_reg = 0x1ff800cc,
 143             .flash_pagesize = 0x100,
 144             .sram_size = 0x8000,/*Not completely clear if there are some with 48K*/
 145             .bootrom_base = 0x1ff00000,
 146             .bootrom_size = 0x1000
 147         },
 148         {
 149             .chip_id = STLINK_CHIPID_STM32_L1_HIGH,
 150             .description = "L1 High-density device",
 151             .flash_type = FLASH_TYPE_L0,
 152             .flash_size_reg = 0x1ff800cc,
 153             .flash_pagesize = 0x100,
 154             .sram_size = 0xC000, /*Not completely clear if there are some with 32K*/
 155             .bootrom_base = 0x1ff00000,
 156             .bootrom_size = 0x1000
 157         },
 158         {
 159             .chip_id = STLINK_CHIPID_STM32_L152_RE,
 160             .description = "L152RE",
 161             .flash_type = FLASH_TYPE_L0,
 162             .flash_size_reg = 0x1ff800cc,
 163             .flash_pagesize = 0x100,
 164             .sram_size = 0x14000, /*Not completely clear if there are some with 32K*/
 165             .bootrom_base = 0x1ff00000,
 166             .bootrom_size = 0x1000
 167         },
 168         {
 169             .chip_id = STLINK_CHIPID_STM32_F1_CONN,
 170             .description = "F1 Connectivity line device",
 171             .flash_type = FLASH_TYPE_F0,
 172             .flash_size_reg = 0x1ffff7e0,
 173             .flash_pagesize = 0x800,
 174             .sram_size = 0x10000,
 175             .bootrom_base = 0x1fffb000,
 176             .bootrom_size = 0x4800
 177         },
 178         {//Low and Medium density VL have same chipid. RM0041 25.6.1
 179             .chip_id = STLINK_CHIPID_STM32_F1_VL_MEDIUM_LOW,
 180             .description = "F1 Medium/Low-density Value Line device",
 181             .flash_type = FLASH_TYPE_F0,
 182             .flash_size_reg = 0x1ffff7e0,
 183             .flash_pagesize = 0x400,
 184             .sram_size = 0x2000,//0x1000 for low density devices
 185             .bootrom_base = 0x1ffff000,
 186             .bootrom_size = 0x800
 187         },
 188         {
 189             // STM32F446x family. Support based on DM00135183.pdf (RM0390) document.
 190             .chip_id = STLINK_CHIPID_STM32_F446,
 191             .description = "F446 device",
 192             .flash_type = FLASH_TYPE_F4,
 193             .flash_size_reg = 0x1fff7a22,
 194             .flash_pagesize = 0x20000,
 195             .sram_size = 0x20000,
 196             .bootrom_base = 0x1fff0000,
 197             .bootrom_size = 0x7800
 198         },
 199         {
 200             // STM32F410 MCUs. Support based on DM00180366.pdf (RM0401) document.
 201             .chip_id = STLINK_CHIPID_STM32_F410,
 202             .description = "F410 device",
 203             .flash_type = FLASH_TYPE_F4,
 204             .flash_size_reg = 0x1fff7a22,
 205             .flash_pagesize = 0x4000,
 206             .sram_size = 0x8000,
 207             .bootrom_base = 0x1fff0000,
 208             .bootrom_size = 0x7800
 209         },
 210         {
 211             // This is STK32F303VCT6 device from STM32 F3 Discovery board.
 212             // Support based on DM00043574.pdf (RM0316) document.
 213             .chip_id = STLINK_CHIPID_STM32_F3,
 214             .description = "F3 device",
 215             .flash_type = FLASH_TYPE_F0,
 216             .flash_size_reg = 0x1ffff7cc,
 217             .flash_pagesize = 0x800,
 218             .sram_size = 0xa000,
 219             .bootrom_base = 0x1ffff000,
 220             .bootrom_size = 0x800
 221         },
 222         {
 223             // This is STK32F373VCT6 device from STM32 F373 eval board
 224             // Support based on 303 above (37x and 30x have same memory map)
 225             .chip_id = STLINK_CHIPID_STM32_F37x,
 226             .description = "F3 device",
 227             .flash_type = FLASH_TYPE_F0,
 228             .flash_size_reg = 0x1ffff7cc,
 229             .flash_pagesize = 0x800,
 230             .sram_size = 0xa000,
 231             .bootrom_base = 0x1ffff000,
 232             .bootrom_size = 0x800
 233         },
 234         {
 235             .chip_id = STLINK_CHIPID_STM32_F1_VL_HIGH,
 236             .description = "F1 High-density value line device",
 237             .flash_type = FLASH_TYPE_F0,
 238             .flash_size_reg = 0x1ffff7e0,
 239             .flash_pagesize = 0x800,
 240             .sram_size = 0x8000,
 241             .bootrom_base = 0x1ffff000,
 242             .bootrom_size = 0x800
 243         },
 244         {
 245             .chip_id = STLINK_CHIPID_STM32_F1_XL,
 246             .description = "F1 XL-density device",
 247             .flash_type = FLASH_TYPE_F0,
 248             .flash_size_reg = 0x1ffff7e0,
 249             .flash_pagesize = 0x800,
 250             .sram_size = 0x18000,
 251             .bootrom_base = 0x1fffe000,
 252             .bootrom_size = 0x1800
 253         },
 254         {
 255             //Use this as an example for mapping future chips:
 256             //RM0091 document was used to find these paramaters
 257             .chip_id = STLINK_CHIPID_STM32_F0_CAN,
 258             .description = "F07x device",
 259             .flash_type = FLASH_TYPE_F0,
 260             .flash_size_reg = 0x1ffff7cc,      // "Flash size data register" (pg735)
 261             .flash_pagesize = 0x800,           // Page sizes listed in Table 4
 262             .sram_size = 0x4000,               // "SRAM" byte size in hex from Table 2
 263             .bootrom_base = 0x1fffC800,                // "System memory" starting address from Table 2
 264             .bootrom_size = 0x3000             // "System memory" byte size in hex from Table 2
 265         },
 266         {
 267             //Use this as an example for mapping future chips:
 268             //RM0091 document was used to find these paramaters
 269             .chip_id = STLINK_CHIPID_STM32_F0,
 270             .description = "F0 device",
 271             .flash_type = FLASH_TYPE_F0,
 272             .flash_size_reg = 0x1ffff7cc,       // "Flash size data register" (pg735)
 273             .flash_pagesize = 0x400,            // Page sizes listed in Table 4
 274             .sram_size = 0x2000,                // "SRAM" byte size in hex from Table 2
 275             .bootrom_base = 0x1fffec00,         // "System memory" starting address from Table 2
 276             .bootrom_size = 0xC00               // "System memory" byte size in hex from Table 2
 277         },
 278         {
 279             .chip_id = STLINK_CHIPID_STM32_F09X,
 280             .description = "F09X device",
 281             .flash_type = FLASH_TYPE_F0,
 282             .flash_size_reg = 0x1ffff7cc,       // "Flash size data register" (pg735)
 283             .flash_pagesize = 0x800,            // Page sizes listed in Table 4 (pg 56)
 284             .sram_size = 0x8000,                // "SRAM" byte size in hex from Table 2 (pg 50)
 285             .bootrom_base = 0x1fffd800,         // "System memory" starting address from Table 2
 286             .bootrom_size = 0x2000              // "System memory" byte size in hex from Table 2
 287         },
 288         {
 289             //Use this as an example for mapping future chips:
 290             //RM0091 document was used to find these paramaters
 291             .chip_id = STLINK_CHIPID_STM32_F04,
 292             .description = "F04x device",
 293             .flash_type = FLASH_TYPE_F0,
 294             .flash_size_reg = 0x1ffff7cc,       // "Flash size data register" (pg735)
 295             .flash_pagesize = 0x400,            // Page sizes listed in Table 4
 296             .sram_size = 0x1800,                // "SRAM" byte size in hex from Table 2
 297             .bootrom_base = 0x1fffec00,         // "System memory" starting address from Table 2
 298             .bootrom_size = 0xC00               // "System memory" byte size in hex from Table 2
 299         },
 300         {
 301             //Use this as an example for mapping future chips:
 302             //RM0091 document was used to find these paramaters
 303             .chip_id = STLINK_CHIPID_STM32_F0_SMALL,
 304             .description = "F0 small device",
 305             .flash_type = FLASH_TYPE_F0,
 306             .flash_size_reg = 0x1ffff7cc,       // "Flash size data register" (pg735)
 307             .flash_pagesize = 0x400,            // Page sizes listed in Table 4
 308             .sram_size = 0x1000,                // "SRAM" byte size in hex from Table 2
 309             .bootrom_base = 0x1fffec00,         // "System memory" starting address from Table 2
 310             .bootrom_size = 0xC00               // "System memory" byte size in hex from Table 2
 311         },
 312         {
 313             // STM32F30x
 314             .chip_id = STLINK_CHIPID_STM32_F3_SMALL,
 315             .description = "F3 small device",
 316             .flash_type = FLASH_TYPE_F0,
 317             .flash_size_reg = 0x1ffff7cc,
 318             .flash_pagesize = 0x800,
 319             .sram_size = 0xa000,
 320             .bootrom_base = 0x1fffd800,
 321             .bootrom_size = 0x2000
 322         },
 323         {
 324             // STM32L0x
 325             // RM0367,RM0377 documents was used to find these parameters
 326             .chip_id = STLINK_CHIPID_STM32_L0,
 327             .description = "L0x3 device",
 328             .flash_type = FLASH_TYPE_L0,
 329             .flash_size_reg = 0x1ff8007c,
 330             .flash_pagesize = 0x80,
 331             .sram_size = 0x2000,
 332             .bootrom_base = 0x1ff0000,
 333             .bootrom_size = 0x1000
 334         },
 335         {
 336             // STM32L0x Category 5
 337             // RM0367,RM0377 documents was used to find these parameters
 338             .chip_id = STLINK_CHIPID_STM32_L0_CAT5,
 339             .description = "L0x Category 5 device",
 340             .flash_type = FLASH_TYPE_L0,
 341             .flash_size_reg = 0x1ff8007c,
 342             .flash_pagesize = 0x80,
 343             .sram_size = 0x5000,
 344             .bootrom_base = 0x1ff0000,
 345             .bootrom_size = 0x2000
 346         },
 347         {
 348             // STM32L0x Category 2
 349             // RM0367,RM0377 documents was used to find these parameters
 350             .chip_id = STLINK_CHIPID_STM32_L0_CAT2,
 351             .description = "L0x Category 2 device",
 352             .flash_type = FLASH_TYPE_L0,
 353             .flash_size_reg = 0x1ff8007c,
 354             .flash_pagesize = 0x80,
 355             .sram_size = 0x2000,
 356             .bootrom_base = 0x1ff0000,
 357             .bootrom_size = 0x1000
 358         },
 359         {
 360             // STM32F334
 361             // RM0364 document was used to find these parameters
 362             .chip_id = STLINK_CHIPID_STM32_F334,
 363             .description = "F334 device",
 364             .flash_type = FLASH_TYPE_F0,
 365             .flash_size_reg = 0x1ffff7cc,
 366             .flash_pagesize = 0x800,
 367             .sram_size = 0x3000,
 368             .bootrom_base = 0x1fffd800,
 369             .bootrom_size = 0x2000
 370         },
 371         {
 372             // This is STK32F303RET6 device from STM32 F3 Nucelo board.
 373             // Support based on DM00043574.pdf (RM0316) document rev 5.
 374             .chip_id = STLINK_CHIPID_STM32_F303_HIGH,
 375             .description = "F303 high density device",
 376             .flash_type = FLASH_TYPE_F0,
 377             .flash_size_reg = 0x1ffff7cc,    // 34.2.1 Flash size data register
 378             .flash_pagesize = 0x800,         // 4.2.1 Flash memory organization
 379             .sram_size = 0x10000,            // 3.3 Embedded SRAM
 380             .bootrom_base = 0x1fffd800,      // 3.3.2 / Table 4 System Memory
 381             .bootrom_size = 0x2000
 382         },
 383         {
 384             // STM32L4x6
 385             // From RM0351.
 386             .chip_id = STLINK_CHIPID_STM32_L4,
 387             .description = "L4 device",
 388             .flash_type = FLASH_TYPE_L4,
 389             .flash_size_reg = 0x1fff75e0,    // "Flash size data register" (sec 45.2, page 1671)
 390             .flash_pagesize = 0x800,         // 2K (sec 3.2, page 78; also appears in sec 3.3.1 and tables 4-6 on pages 79-81)
 391             // SRAM1 is "up to" 96k in the standard Cortex-M memory map;
 392             // SRAM2 is 32k mapped at at 0x10000000 (sec 2.3, page 73 for
 393             // sizes; table 2, page 74 for SRAM2 location)
 394             .sram_size = 0x18000,
 395             .bootrom_base = 0x1fff0000,      // Tables 4-6, pages 80-81 (Bank 1 system memory)
 396             .bootrom_size = 0x7000           // 28k (per bank), same source as base
 397         },
 398
 399  };
 400
 401 const struct stlink_chipid_params *stlink_chipid_get_params(uint32_t chipid)
 402 {
 403         struct stlink_chipid_params *params = NULL;
 404
 405         for (size_t n = 0; n < STLINK_ARRAY_SIZE(devices); n++) {
 406                 if (devices[n].chip_id == chipid) {
 407                         params = &devices[n];
 408                         break;
 409                 }
 410         }
 411
 412         return params;
 413 }