4 * This should contain all the common top level stlink interfaces, regardless
5 * of how the backend does the work....
18 #define STLINK_ARRAY_SIZE(x) (sizeof(x)/sizeof(x[0]))
20 // Max data transfer size.
21 // 6kB = max mem32_read block, 8kB sram
22 //#define Q_BUF_LEN 96
23 #define Q_BUF_LEN (1024 * 100)
25 // STLINK_DEBUG_RESETSYS, etc:
26 #define STLINK_CORE_RUNNING 0x80
27 #define STLINK_CORE_HALTED 0x81
28 #define STLINK_CORE_STAT_UNKNOWN -1
30 #define STLINK_GET_VERSION 0xf1
31 #define STLINK_GET_CURRENT_MODE 0xf5
32 #define STLINK_GET_TARGET_VOLTAGE 0xF7
34 #define STLINK_DEBUG_COMMAND 0xF2
35 #define STLINK_DFU_COMMAND 0xF3
36 #define STLINK_DFU_EXIT 0x07
38 // STLINK_GET_CURRENT_MODE
39 #define STLINK_DEV_DFU_MODE 0x00
40 #define STLINK_DEV_MASS_MODE 0x01
41 #define STLINK_DEV_DEBUG_MODE 0x02
42 #define STLINK_DEV_UNKNOWN_MODE -1
44 // TODO - possible poor names...
45 #define STLINK_SWD_ENTER 0x30
46 #define STLINK_SWD_READCOREID 0x32 // TBD
47 #define STLINK_JTAG_WRITEDEBUG_32BIT 0x35
48 #define STLINK_JTAG_READDEBUG_32BIT 0x36
49 #define STLINK_JTAG_DRIVE_NRST 0x3c
52 // TODO clean this up...
53 #define STM32VL_CORE_ID 0x1ba01477
55 // Constant STM32 memory map figures
56 #define STM32_FLASH_BASE 0x08000000
57 #define STM32_SRAM_BASE 0x20000000
59 /* Enough space to hold both a V2 command or a V1 command packaged as generic scsi*/
62 enum stlink_flash_type {
63 STLINK_FLASH_TYPE_UNKNOWN = 0,
85 typedef uint32_t stm32_addr_t;
87 typedef struct flash_loader {
88 stm32_addr_t loader_addr; /* loader sram adddr */
89 stm32_addr_t buf_addr; /* buffer sram address */
92 typedef struct _cortex_m3_cpuid_ {
93 uint16_t implementer_id;
99 typedef struct stlink_version_ {
107 enum transport_type {
108 TRANSPORT_TYPE_ZERO = 0,
109 TRANSPORT_TYPE_LIBSG,
110 TRANSPORT_TYPE_LIBUSB,
111 TRANSPORT_TYPE_INVALID
114 typedef struct _stlink stlink_t;
116 #include "stlink/backend.h"
119 struct _stlink_backend *backend;
122 // Room for the command header
123 unsigned char c_buf[C_BUF_LEN];
124 // Data transferred from or to device
125 unsigned char q_buf[Q_BUF_LEN];
128 // transport layer verboseness: 0 for no debug info, 10 for lots
137 enum stlink_flash_type flash_type;
138 stm32_addr_t flash_base;
143 stm32_addr_t sram_base;
147 stm32_addr_t sys_base;
150 struct stlink_version_ version;
153 int stlink_enter_swd_mode(stlink_t *sl);
154 int stlink_enter_jtag_mode(stlink_t *sl);
155 int stlink_exit_debug_mode(stlink_t *sl);
156 int stlink_exit_dfu_mode(stlink_t *sl);
157 void stlink_close(stlink_t *sl);
158 int stlink_core_id(stlink_t *sl);
159 int stlink_reset(stlink_t *sl);
160 int stlink_jtag_reset(stlink_t *sl, int value);
161 int stlink_run(stlink_t *sl);
162 int stlink_status(stlink_t *sl);
163 int stlink_version(stlink_t *sl);
164 int stlink_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data);
165 int stlink_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len);
166 int stlink_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data);
167 int stlink_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len);
168 int stlink_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len);
169 int stlink_read_all_regs(stlink_t *sl, reg *regp);
170 int stlink_read_all_unsupported_regs(stlink_t *sl, reg *regp);
171 int stlink_read_reg(stlink_t *sl, int r_idx, reg *regp);
172 int stlink_read_unsupported_reg(stlink_t *sl, int r_idx, reg *regp);
173 int stlink_write_unsupported_reg(stlink_t *sl, uint32_t value, int r_idx, reg *regp);
174 int stlink_write_reg(stlink_t *sl, uint32_t reg, int idx);
175 int stlink_step(stlink_t *sl);
176 int stlink_current_mode(stlink_t *sl);
177 int stlink_force_debug(stlink_t *sl);
178 int stlink_target_voltage(stlink_t *sl);
180 int stlink_erase_flash_mass(stlink_t* sl);
181 int stlink_write_flash(stlink_t* sl, stm32_addr_t address, uint8_t* data, uint32_t length, uint8_t eraseonly);
182 int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr);
183 int stlink_fwrite_sram(stlink_t *sl, const char* path, stm32_addr_t addr);
184 int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, uint32_t length);
186 int stlink_chip_id(stlink_t *sl, uint32_t *chip_id);
187 int stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid);
189 int stlink_erase_flash_page(stlink_t* sl, stm32_addr_t flashaddr);
190 uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr);
191 uint16_t read_uint16(const unsigned char *c, const int pt);
192 void stlink_core_stat(stlink_t *sl);
193 void stlink_print_data(stlink_t *sl);
194 unsigned int is_bigendian(void);
195 uint32_t read_uint32(const unsigned char *c, const int pt);
196 void write_uint32(unsigned char* buf, uint32_t ui);
197 void write_uint16(unsigned char* buf, uint16_t ui);
198 bool stlink_is_core_halted(stlink_t *sl);
199 int write_buffer_to_sram(stlink_t *sl, flash_loader_t* fl, const uint8_t* buf, size_t size);
200 int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size);
201 int stlink_fread(stlink_t* sl, const char* path, stm32_addr_t addr, size_t size);
202 int stlink_load_device_params(stlink_t *sl);
204 #include "stlink/sg.h"
205 #include "stlink/usb.h"
206 #include "stlink/reg.h"
207 #include "stlink/commands.h"
208 #include "stlink/chipid.h"
209 #include "stlink/flash_loader.h"
215 #endif /* STLINK_H */