2 ******************************************************************************
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3 * @file stm32l1xx_adc.c
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4 * @author MCD Application Team
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6 * @date 31-December-2010
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7 * @brief This file provides firmware functions to manage the following
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8 * functionalities of the Analog to Digital Convertor (ADC) peripheral:
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9 * - Initialization and Configuration
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11 * - Analog Watchdog configuration
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12 * - Temperature Sensor & Vrefint (Voltage Reference internal) management
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13 * - Regular Channels Configuration
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14 * - Regular Channels DMA Configuration
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15 * - Injected channels Configuration
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16 * - Interrupts and flags management
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20 * ===================================================================
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21 * How to use this driver
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22 * ===================================================================
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23 * - Configure the ADC Prescaler, conversion resolution and data
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24 * alignment using the ADC_Init() function.
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25 * - Activate the ADC peripheral using ADC_Cmd() function.
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27 * Regular channels group configuration
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28 * ====================================
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29 * - To configure the ADC regular channels group features, use
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30 * ADC_Init() and ADC_RegularChannelConfig() functions.
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31 * - To activate the continuous mode, use the ADC_continuousModeCmd()
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33 * - To configurate and activate the Discontinuous mode, use the
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34 * ADC_DiscModeChannelCountConfig() and ADC_DiscModeCmd() functions.
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35 * - To read the ADC converted values, use the ADC_GetConversionValue()
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38 * DMA for Regular channels group features configuration
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39 * ======================================================
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40 * - To enable the DMA mode for regular channels group, use the
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41 * ADC_DMACmd() function.
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42 * - To enable the generation of DMA requests continuously at the end
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43 * of the last DMA transfer, use the ADC_DMARequestAfterLastTransferCmd()
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46 * Injected channels group configuration
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47 * =====================================
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48 * - To configure the ADC Injected channels group features, use
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49 * ADC_InjectedChannelConfig() and ADC_InjectedSequencerLengthConfig()
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51 * - To activate the continuous mode, use the ADC_continuousModeCmd()
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53 * - To activate the Injected Discontinuous mode, use the
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54 * ADC_InjectedDiscModeCmd() function.
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55 * - To activate the AutoInjected mode, use the ADC_AutoInjectedConvCmd()
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57 * - To read the ADC converted values, use the ADC_GetInjectedConversionValue()
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62 ******************************************************************************
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65 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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66 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
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67 * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
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68 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
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69 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
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70 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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72 * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
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73 ******************************************************************************
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76 /* Includes ------------------------------------------------------------------*/
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77 #include "stm32l1xx_adc.h"
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78 #include "stm32l1xx_rcc.h"
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80 /** @addtogroup STM32L1xx_StdPeriph_Driver
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85 * @brief ADC driver modules
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89 /* Private typedef -----------------------------------------------------------*/
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90 /* Private define ------------------------------------------------------------*/
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91 /* ADC DISCNUM mask */
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92 #define CR1_DISCNUM_RESET ((uint32_t)0xFFFF1FFF)
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94 /* ADC AWDCH mask */
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95 #define CR1_AWDCH_RESET ((uint32_t)0xFFFFFFE0)
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97 /* ADC Analog watchdog enable mode mask */
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98 #define CR1_AWDMODE_RESET ((uint32_t)0xFF3FFDFF)
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100 /* CR1 register Mask */
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101 #define CR1_CLEAR_MASK ((uint32_t)0xFCFFFEFF)
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103 /* ADC DELAY mask */
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104 #define CR2_DELS_RESET ((uint32_t)0xFFFFFF0F)
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106 /* ADC JEXTEN mask */
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107 #define CR2_JEXTEN_RESET ((uint32_t)0xFFCFFFFF)
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109 /* ADC JEXTSEL mask */
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110 #define CR2_JEXTSEL_RESET ((uint32_t)0xFFF0FFFF)
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112 /* CR2 register Mask */
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113 #define CR2_CLEAR_MASK ((uint32_t)0xC0FFF7FD)
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116 #define SQR5_SQ_SET ((uint32_t)0x0000001F)
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117 #define SQR4_SQ_SET ((uint32_t)0x0000001F)
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118 #define SQR3_SQ_SET ((uint32_t)0x0000001F)
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119 #define SQR2_SQ_SET ((uint32_t)0x0000001F)
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120 #define SQR1_SQ_SET ((uint32_t)0x0000001F)
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123 #define SQR1_L_RESET ((uint32_t)0xFE0FFFFF)
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125 /* ADC JSQx mask */
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126 #define JSQR_JSQ_SET ((uint32_t)0x0000001F)
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129 #define JSQR_JL_SET ((uint32_t)0x00300000)
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130 #define JSQR_JL_RESET ((uint32_t)0xFFCFFFFF)
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132 /* ADC SMPx mask */
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133 #define SMPR1_SMP_SET ((uint32_t)0x00000007)
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134 #define SMPR2_SMP_SET ((uint32_t)0x00000007)
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135 #define SMPR3_SMP_SET ((uint32_t)0x00000007)
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137 /* ADC JDRx registers offset */
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138 #define JDR_OFFSET ((uint8_t)0x30)
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140 /* ADC CCR register Mask */
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141 #define CR_CLEAR_MASK ((uint32_t)0xFFFCFFFF)
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143 /* Private macro -------------------------------------------------------------*/
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144 /* Private variables ---------------------------------------------------------*/
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145 /* Private function prototypes -----------------------------------------------*/
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146 /* Private functions ---------------------------------------------------------*/
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148 /** @defgroup ADC_Private_Functions
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152 /** @defgroup ADC_Group1 Initialization and Configuration functions
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153 * @brief Initialization and Configuration functions
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156 ===============================================================================
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157 Initialization and Configuration functions
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158 ===============================================================================
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159 This section provides functions allowing to:
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160 - Initialize and configure the ADC Prescaler
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161 - ADC Conversion Resolution (12bit..6bit)
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162 - Scan Conversion Mode (multichannels or one channel) for regular group
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163 - ADC Continuous Conversion Mode (Continuous or Single conversion) for regular group
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164 - External trigger Edge and source of regular group,
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165 - Converted data alignment (left or right)
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166 - The number of ADC conversions that will be done using the sequencer for regular channel group
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167 - Enable or disable the ADC peripheral
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174 * @brief Deinitializes ADC1 peripheral registers to their default reset values.
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178 void ADC_DeInit(ADC_TypeDef* ADCx)
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180 /* Check the parameters */
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181 assert_param(IS_ADC_ALL_PERIPH(ADCx));
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183 /* Enable ADC1 reset state */
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184 RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, ENABLE);
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185 /* Release ADC1 from reset state */
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186 RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, DISABLE);
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190 * @brief Initializes the ADCx peripheral according to the specified parameters
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191 * in the ADC_InitStruct.
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192 * @note This function is used to configure the global features of the ADC (
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193 * Resolution and Data Alignment), however, the rest of the configuration
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194 * parameters are specific to the regular channels group (scan mode
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195 * activation, continuous mode activation, External trigger source and
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196 * edge, number of conversion in the regular channels group sequencer).
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197 * @param ADCx: where x can be 1 to select the ADC peripheral.
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198 * @param ADC_InitStruct: pointer to an ADC_InitTypeDef structure that contains
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199 * the configuration information for the specified ADC peripheral.
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202 void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct)
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204 uint32_t tmpreg1 = 0;
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205 uint8_t tmpreg2 = 0;
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207 /* Check the parameters */
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208 assert_param(IS_ADC_ALL_PERIPH(ADCx));
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209 assert_param(IS_ADC_RESOLUTION(ADC_InitStruct->ADC_Resolution));
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210 assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ScanConvMode));
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211 assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ContinuousConvMode));
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212 assert_param(IS_ADC_EXT_TRIG_EDGE(ADC_InitStruct->ADC_ExternalTrigConvEdge));
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213 assert_param(IS_ADC_EXT_TRIG(ADC_InitStruct->ADC_ExternalTrigConv));
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214 assert_param(IS_ADC_DATA_ALIGN(ADC_InitStruct->ADC_DataAlign));
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215 assert_param(IS_ADC_REGULAR_LENGTH(ADC_InitStruct->ADC_NbrOfConversion));
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217 /*---------------------------- ADCx CR1 Configuration -----------------*/
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218 /* Get the ADCx CR1 value */
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219 tmpreg1 = ADCx->CR1;
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220 /* Clear RES and SCAN bits */
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221 tmpreg1 &= CR1_CLEAR_MASK;
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222 /* Configure ADCx: scan conversion mode and resolution */
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223 /* Set SCAN bit according to ADC_ScanConvMode value */
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224 /* Set RES bit according to ADC_Resolution value */
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225 tmpreg1 |= (uint32_t)(((uint32_t)ADC_InitStruct->ADC_ScanConvMode << 8) | ADC_InitStruct->ADC_Resolution);
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226 /* Write to ADCx CR1 */
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227 ADCx->CR1 = tmpreg1;
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229 /*---------------------------- ADCx CR2 Configuration -----------------*/
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230 /* Get the ADCx CR2 value */
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231 tmpreg1 = ADCx->CR2;
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232 /* Clear CONT, ALIGN, EXTEN and EXTSEL bits */
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233 tmpreg1 &= CR2_CLEAR_MASK;
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234 /* Configure ADCx: external trigger event and edge, data alignment and continuous conversion mode */
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235 /* Set ALIGN bit according to ADC_DataAlign value */
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236 /* Set EXTEN bits according to ADC_ExternalTrigConvEdge value */
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237 /* Set EXTSEL bits according to ADC_ExternalTrigConv value */
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238 /* Set CONT bit according to ADC_ContinuousConvMode value */
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239 tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_DataAlign | ADC_InitStruct->ADC_ExternalTrigConv |
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240 ADC_InitStruct->ADC_ExternalTrigConvEdge | ((uint32_t)ADC_InitStruct->ADC_ContinuousConvMode << 1));
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241 /* Write to ADCx CR2 */
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242 ADCx->CR2 = tmpreg1;
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244 /*---------------------------- ADCx SQR1 Configuration -----------------*/
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245 /* Get the ADCx SQR1 value */
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246 tmpreg1 = ADCx->SQR1;
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248 tmpreg1 &= SQR1_L_RESET;
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249 /* Configure ADCx: regular channel sequence length */
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250 /* Set L bits according to ADC_NbrOfConversion value */
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251 tmpreg2 |= (uint8_t)(ADC_InitStruct->ADC_NbrOfConversion - (uint8_t)1);
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252 tmpreg1 |= ((uint32_t)tmpreg2 << 20);
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253 /* Write to ADCx SQR1 */
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254 ADCx->SQR1 = tmpreg1;
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258 * @brief Fills each ADC_InitStruct member with its default value.
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259 * @note This function is used to initialize the global features of the ADC (
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260 * Resolution and Data Alignment), however, the rest of the configuration
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261 * parameters are specific to the regular channels group (scan mode
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262 * activation, continuous mode activation, External trigger source and
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263 * edge, number of conversion in the regular channels group sequencer).
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264 * @param ADC_InitStruct: pointer to an ADC_InitTypeDef structure which will
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268 void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct)
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270 /* Reset ADC init structure parameters values */
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271 /* Initialize the ADC_Resolution member */
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272 ADC_InitStruct->ADC_Resolution = ADC_Resolution_12b;
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274 /* Initialize the ADC_ScanConvMode member */
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275 ADC_InitStruct->ADC_ScanConvMode = DISABLE;
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277 /* Initialize the ADC_ContinuousConvMode member */
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278 ADC_InitStruct->ADC_ContinuousConvMode = DISABLE;
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280 /* Initialize the ADC_ExternalTrigConvEdge member */
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281 ADC_InitStruct->ADC_ExternalTrigConvEdge = ADC_ExternalTrigConvEdge_None;
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283 /* Initialize the ADC_ExternalTrigConv member */
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284 ADC_InitStruct->ADC_ExternalTrigConv = ADC_ExternalTrigConv_T2_CC2;
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286 /* Initialize the ADC_DataAlign member */
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287 ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right;
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289 /* Initialize the ADC_NbrOfConversion member */
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290 ADC_InitStruct->ADC_NbrOfConversion = 1;
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294 * @brief Initializes the ADCs peripherals according to the specified parameters
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295 * in the ADC_CommonInitStruct.
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296 * @param ADC_CommonInitStruct: pointer to an ADC_CommonInitTypeDef structure
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297 * that contains the configuration information (Prescaler) for ADC1 peripheral.
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300 void ADC_CommonInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct)
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302 uint32_t tmpreg = 0;
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304 /* Check the parameters */
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305 assert_param(IS_ADC_PRESCALER(ADC_CommonInitStruct->ADC_Prescaler));
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307 /*---------------------------- ADC CCR Configuration -----------------*/
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308 /* Get the ADC CCR value */
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311 /* Clear ADCPRE bit */
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312 tmpreg &= CR_CLEAR_MASK;
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314 /* Configure ADCx: ADC prescaler according to ADC_Prescaler */
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315 tmpreg |= (uint32_t)(ADC_CommonInitStruct->ADC_Prescaler);
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317 /* Write to ADC CCR */
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322 * @brief Fills each ADC_CommonInitStruct member with its default value.
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323 * @param ADC_CommonInitStruct: pointer to an ADC_CommonInitTypeDef structure
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324 * which will be initialized.
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327 void ADC_CommonStructInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct)
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329 /* Reset ADC init structure parameters values */
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330 /* Initialize the ADC_Prescaler member */
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331 ADC_CommonInitStruct->ADC_Prescaler = ADC_Prescaler_Div1;
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336 * @brief Enables or disables the specified ADC peripheral.
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337 * @param ADCx: where x can be 1 to select the ADC1 peripheral.
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338 * @param NewState: new state of the ADCx peripheral.
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339 * This parameter can be: ENABLE or DISABLE.
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342 void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState)
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344 /* Check the parameters */
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345 assert_param(IS_ADC_ALL_PERIPH(ADCx));
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346 assert_param(IS_FUNCTIONAL_STATE(NewState));
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348 if (NewState != DISABLE)
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350 /* Set the ADON bit to wake up the ADC from power down mode */
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351 ADCx->CR2 |= (uint32_t)ADC_CR2_ADON;
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355 /* Disable the selected ADC peripheral */
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356 ADCx->CR2 &= (uint32_t)(~ADC_CR2_ADON);
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364 /** @defgroup ADC_Group2 Power saving functions
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365 * @brief Power saving functions
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368 ===============================================================================
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369 Power saving functions
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370 ===============================================================================
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372 This section provides functions allowing to reduce power consumption.
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373 The two function must be combined to get the maximal benefits:
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374 When the ADC frequency is higher than the CPU one, it is recommended to
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375 1. Insert a freeze delay :
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376 ==> using ADC_DelaySelectionConfig(ADC1, ADC_DelayLength_Freeze);
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377 2. Enable the power down in Idle and Delay phases :
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378 ==> using ADC_PowerDownCmd(ADC1, ADC_PowerDown_Idle_Delay, ENABLE);
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385 * @brief Enables or disables the ADC Power Down during Delay and/or Idle phase.
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386 * @note ADC power-on and power-off can be managed by hardware to cut the
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387 * consumption when the ADC is not converting.
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388 * @param ADCx: where x can be 1 to select the ADC1 peripheral.
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389 * @param ADC_PowerDown: The ADC power down configuration.
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390 * This parameter can be one of the following values:
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391 * @arg ADC_PowerDown_Delay: ADC is powered down during delay phase
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392 * @arg ADC_PowerDown_Idle: ADC is powered down during Idle phase
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393 * @arg ADC_PowerDown_Idle_Delay: ADC is powered down during Delay and Idle phases
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394 * @note The ADC can be powered down:
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395 * - During the hardware delay insertion (using the ADC_PowerDown_Delay
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397 * => The ADC is powered up again at the end of the delay.
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398 * - During the ADC is waiting for a trigger event ( using the
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399 * ADC_PowerDown_Idle parameter)
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400 * => The ADC is powered up at the next trigger event.
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401 * - During the hardware delay insertion or the ADC is waiting for a
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402 * trigger event (using the ADC_PowerDown_Idle_Delay parameter)
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403 * => The ADC is powered up only at the end of the delay and at the
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404 * next trigger event.
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405 * @param NewState: new state of the ADCx power down.
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406 * This parameter can be: ENABLE or DISABLE.
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409 void ADC_PowerDownCmd(ADC_TypeDef* ADCx, uint32_t ADC_PowerDown, FunctionalState NewState)
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411 /* Check the parameters */
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412 assert_param(IS_ADC_ALL_PERIPH(ADCx));
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413 assert_param(IS_FUNCTIONAL_STATE(NewState));
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414 assert_param(IS_ADC_POWER_DOWN(ADC_PowerDown));
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416 if (NewState != DISABLE)
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418 /* Enable the ADC power-down during Delay and/or Idle phase */
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419 ADCx->CR1 |= ADC_PowerDown;
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423 /* Disable The ADC power-down during Delay and/or Idle phase */
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424 ADCx->CR1 &= (uint32_t)~ADC_PowerDown;
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429 * @brief Defines the length of the delay which is applied after a conversion
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430 * or a sequence of conversion.
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431 * @note When the CPU clock is not fast enough to manage the data rate, a
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432 * Hardware delay can be introduced between ADC conversions to reduce
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434 * @note The Hardware delay is inserted after :
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435 * - each regular conversion
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436 * - after each sequence of injected conversions
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437 * @note No Hardware delay is inserted between conversions of different groups.
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438 * @note When the hardware delay is not enough, the Freeze Delay Mode can be
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439 * selected and a new conversion can start only if all the previous data
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440 * of the same group have been treated:
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441 * - for a regular conversion: once the ADC conversion data register has
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442 * been read (using ADC_GetConversionValue() function) or if the EOC
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443 * Flag has been cleared (using ADC_ClearFlag() function).
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444 * - for an injected conversion: when the JEOC bit has been cleared
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445 * (using ADC_ClearFlag() function).
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446 * @param ADCx: where x can be 1 to select the ADC1 peripheral.
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447 * @param ADC_DelayLength: The length of delay which is applied after a
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448 * conversion or a sequence of conversion.
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449 * This parameter can be one of the following values:
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450 * @arg ADC_DelayLength_None: No delay
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451 * @arg ADC_DelayLength_Freeze: Delay until the converted data has been read.
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452 * @arg ADC_DelayLength_7Cycles: Delay length equal to 7 APB clock cycles
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453 * @arg ADC_DelayLength_15Cycles: Delay length equal to 15 APB clock cycles
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454 * @arg ADC_DelayLength_31Cycles: Delay length equal to 31 APB clock cycles
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455 * @arg ADC_DelayLength_63Cycles: Delay length equal to 63 APB clock cycles
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456 * @arg ADC_DelayLength_127Cycles: Delay length equal to 127 APB clock cycles
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457 * @arg ADC_DelayLength_255Cycles: Delay length equal to 255 APB clock cycles
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460 void ADC_DelaySelectionConfig(ADC_TypeDef* ADCx, uint8_t ADC_DelayLength)
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462 uint32_t tmpreg = 0;
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464 /* Check the parameters */
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465 assert_param(IS_ADC_ALL_PERIPH(ADCx));
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466 assert_param(IS_ADC_DELAY_LENGTH(ADC_DelayLength));
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468 /* Get the old register value */
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469 tmpreg = ADCx->CR2;
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470 /* Clear the old delay length */
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471 tmpreg &= CR2_DELS_RESET;
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472 /* Set the delay length */
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473 tmpreg |= ADC_DelayLength;
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474 /* Store the new register value */
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475 ADCx->CR2 = tmpreg;
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483 /** @defgroup ADC_Group3 Analog Watchdog configuration functions
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484 * @brief Analog Watchdog configuration functions
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487 ===============================================================================
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488 Analog Watchdog configuration functions
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489 ===============================================================================
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491 This section provides functions allowing to configure the Analog Watchdog
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492 (AWD) feature in the ADC.
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494 A typical configuration Analog Watchdog is done following these steps :
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495 1. the ADC guarded channel(s) is (are) selected using the
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496 ADC_AnalogWatchdogSingleChannelConfig() function.
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497 2. The Analog watchdog lower and higher threshold are configured using the
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498 ADC_AnalogWatchdogThresholdsConfig() function.
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499 3. The Analog watchdog is enabled and configured to enable the check, on one
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500 or more channels, using the ADC_AnalogWatchdogCmd() function.
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507 * @brief Enables or disables the analog watchdog on single/all regular
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508 * or injected channels
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509 * @param ADCx: where x can be 1 to select the ADC1 peripheral.
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510 * @param ADC_AnalogWatchdog: the ADC analog watchdog configuration.
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511 * This parameter can be one of the following values:
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512 * @arg ADC_AnalogWatchdog_SingleRegEnable: Analog watchdog on a single
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514 * @arg ADC_AnalogWatchdog_SingleInjecEnable: Analog watchdog on a single
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516 * @arg ADC_AnalogWatchdog_SingleRegOrInjecEnable: Analog watchdog on a
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517 * single regular or injected channel
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518 * @arg ADC_AnalogWatchdog_AllRegEnable: Analog watchdog on all regular
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520 * @arg ADC_AnalogWatchdog_AllInjecEnable: Analog watchdog on all injected
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522 * @arg ADC_AnalogWatchdog_AllRegAllInjecEnable: Analog watchdog on all
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523 * regular and injected channels
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524 * @arg ADC_AnalogWatchdog_None: No channel guarded by the analog watchdog
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527 void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog)
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529 uint32_t tmpreg = 0;
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531 /* Check the parameters */
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532 assert_param(IS_ADC_ALL_PERIPH(ADCx));
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533 assert_param(IS_ADC_ANALOG_WATCHDOG(ADC_AnalogWatchdog));
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535 /* Get the old register value */
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536 tmpreg = ADCx->CR1;
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537 /* Clear AWDEN, JAWDEN and AWDSGL bits */
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538 tmpreg &= CR1_AWDMODE_RESET;
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539 /* Set the analog watchdog enable mode */
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540 tmpreg |= ADC_AnalogWatchdog;
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541 /* Store the new register value */
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542 ADCx->CR1 = tmpreg;
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546 * @brief Configures the high and low thresholds of the analog watchdog.
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547 * @param ADCx: where x can be 1 to select the ADC1 peripheral.
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548 * @param HighThreshold: the ADC analog watchdog High threshold value.
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549 * This parameter must be a 12bit value.
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550 * @param LowThreshold: the ADC analog watchdog Low threshold value.
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551 * This parameter must be a 12bit value.
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554 void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold,
\r
555 uint16_t LowThreshold)
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557 /* Check the parameters */
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558 assert_param(IS_ADC_ALL_PERIPH(ADCx));
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559 assert_param(IS_ADC_THRESHOLD(HighThreshold));
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560 assert_param(IS_ADC_THRESHOLD(LowThreshold));
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562 /* Set the ADCx high threshold */
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563 ADCx->HTR = HighThreshold;
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564 /* Set the ADCx low threshold */
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565 ADCx->LTR = LowThreshold;
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569 * @brief Configures the analog watchdog guarded single channel
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570 * @param ADCx: where x can be 1 to select the ADC1 peripheral.
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571 * @param ADC_Channel: the ADC channel to configure for the analog watchdog.
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572 * This parameter can be one of the following values:
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573 * @arg ADC_Channel_0: ADC Channel0 selected
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574 * @arg ADC_Channel_1: ADC Channel1 selected
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575 * @arg ADC_Channel_2: ADC Channel2 selected
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576 * @arg ADC_Channel_3: ADC Channel3 selected
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577 * @arg ADC_Channel_4: ADC Channel4 selected
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578 * @arg ADC_Channel_5: ADC Channel5 selected
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579 * @arg ADC_Channel_6: ADC Channel6 selected
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580 * @arg ADC_Channel_7: ADC Channel7 selected
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581 * @arg ADC_Channel_8: ADC Channel8 selected
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582 * @arg ADC_Channel_9: ADC Channel9 selected
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583 * @arg ADC_Channel_10: ADC Channel10 selected
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584 * @arg ADC_Channel_11: ADC Channel11 selected
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585 * @arg ADC_Channel_12: ADC Channel12 selected
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586 * @arg ADC_Channel_13: ADC Channel13 selected
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587 * @arg ADC_Channel_14: ADC Channel14 selected
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588 * @arg ADC_Channel_15: ADC Channel15 selected
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589 * @arg ADC_Channel_16: ADC Channel16 selected
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590 * @arg ADC_Channel_17: ADC Channel17 selected
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591 * @arg ADC_Channel_18: ADC Channel18 selected
\r
592 * @arg ADC_Channel_19: ADC Channel19 selected
\r
593 * @arg ADC_Channel_20: ADC Channel20 selected
\r
594 * @arg ADC_Channel_21: ADC Channel21 selected
\r
595 * @arg ADC_Channel_22: ADC Channel22 selected
\r
596 * @arg ADC_Channel_23: ADC Channel23 selected
\r
597 * @arg ADC_Channel_24: ADC Channel24 selected
\r
598 * @arg ADC_Channel_25: ADC Channel25 selected
\r
601 void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel)
\r
603 uint32_t tmpreg = 0;
\r
605 /* Check the parameters */
\r
606 assert_param(IS_ADC_ALL_PERIPH(ADCx));
\r
607 assert_param(IS_ADC_CHANNEL(ADC_Channel));
\r
609 /* Get the old register value */
\r
610 tmpreg = ADCx->CR1;
\r
611 /* Clear the Analog watchdog channel select bits */
\r
612 tmpreg &= CR1_AWDCH_RESET;
\r
613 /* Set the Analog watchdog channel */
\r
614 tmpreg |= ADC_Channel;
\r
615 /* Store the new register value */
\r
616 ADCx->CR1 = tmpreg;
\r
623 /** @defgroup ADC_Group4 Temperature Sensor & Vrefint (Voltage Reference internal) management function
\r
624 * @brief Temperature Sensor & Vrefint (Voltage Reference internal) management function
\r
627 ===============================================================================
\r
628 Temperature Sensor & Vrefint (Voltage Reference internal) management function
\r
629 ===============================================================================
\r
631 This section provides a function allowing to enable/ disable the internal
\r
632 connections between the ADC and the Temperature Sensor and the Vrefint source.
\r
634 A typical configuration to get the Temperature sensor and Vrefint channels
\r
635 voltages or is done following these steps :
\r
636 1. Enable the internal connection of Temperature sensor and Vrefint sources
\r
637 with the ADC channels using ADC_TempSensorVrefintCmd() function.
\r
638 2. select the ADC_Channel_TempSensor and/or ADC_Channel_Vrefint using
\r
639 ADC_RegularChannelConfig() or ADC_InjectedChannelConfig() functions
\r
640 3. Get the voltage values, using ADC_GetConversionValue() or
\r
641 ADC_GetInjectedConversionValue().
\r
648 * @brief Enables or disables the temperature sensor and Vrefint channel.
\r
649 * @param NewState: new state of the temperature sensor and Vref int channels.
\r
650 * This parameter can be: ENABLE or DISABLE.
\r
653 void ADC_TempSensorVrefintCmd(FunctionalState NewState)
\r
655 /* Check the parameters */
\r
656 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
658 if (NewState != DISABLE)
\r
660 /* Enable the temperature sensor and Vrefint channel*/
\r
661 ADC->CCR |= (uint32_t)ADC_CCR_TSVREFE;
\r
665 /* Disable the temperature sensor and Vrefint channel*/
\r
666 ADC->CCR &= (uint32_t)(~ADC_CCR_TSVREFE);
\r
674 /** @defgroup ADC_Group5 Regular Channels Configuration functions
\r
675 * @brief Regular Channels Configuration functions
\r
678 ===============================================================================
\r
679 Regular Channels Configuration functions
\r
680 ===============================================================================
\r
682 This section provides functions allowing to manage the ADC regular channels,
\r
683 it is composed of 2 sub sections :
\r
685 1. Configuration and management functions for regular channels: This subsection
\r
686 provides functions allowing to configure the ADC regular channels :
\r
687 - Configure the rank in the regular group sequencer for each channel
\r
688 - Configure the sampling time for each channel
\r
689 - select the conversion Trigger for regular channels
\r
690 - select the desired EOC event behavior configuration
\r
691 - Activate the continuous Mode (*)
\r
692 - Activate the Discontinuous Mode
\r
693 Please Note that the following features for regular channels are configurated
\r
694 using the ADC_Init() function :
\r
695 - scan mode activation
\r
696 - continuous mode activation (**)
\r
697 - External trigger source
\r
698 - External trigger edge
\r
699 - number of conversion in the regular channels group sequencer.
\r
701 @note : (*) and (**) are performing the same configuration
\r
703 2. Get the conversion data: This subsection provides an important function in
\r
704 the ADC peripheral since it returns the converted data of the current
\r
705 regular channel. When the Conversion value is read, the EOC Flag is
\r
706 automatically cleared.
\r
713 * @brief Configures for the selected ADC regular channel its corresponding
\r
714 * rank in the sequencer and its sampling time.
\r
715 * @param ADCx: where x can be 1 to select the ADC peripheral.
\r
716 * @param ADC_Channel: the ADC channel to configure.
\r
717 * This parameter can be one of the following values:
\r
718 * @arg ADC_Channel_0: ADC Channel0 selected
\r
719 * @arg ADC_Channel_1: ADC Channel1 selected
\r
720 * @arg ADC_Channel_2: ADC Channel2 selected
\r
721 * @arg ADC_Channel_3: ADC Channel3 selected
\r
722 * @arg ADC_Channel_4: ADC Channel4 selected
\r
723 * @arg ADC_Channel_5: ADC Channel5 selected
\r
724 * @arg ADC_Channel_6: ADC Channel6 selected
\r
725 * @arg ADC_Channel_7: ADC Channel7 selected
\r
726 * @arg ADC_Channel_8: ADC Channel8 selected
\r
727 * @arg ADC_Channel_9: ADC Channel9 selected
\r
728 * @arg ADC_Channel_10: ADC Channel10 selected
\r
729 * @arg ADC_Channel_11: ADC Channel11 selected
\r
730 * @arg ADC_Channel_12: ADC Channel12 selected
\r
731 * @arg ADC_Channel_13: ADC Channel13 selected
\r
732 * @arg ADC_Channel_14: ADC Channel14 selected
\r
733 * @arg ADC_Channel_15: ADC Channel15 selected
\r
734 * @arg ADC_Channel_16: ADC Channel16 selected
\r
735 * @arg ADC_Channel_17: ADC Channel17 selected
\r
736 * @arg ADC_Channel_18: ADC Channel18 selected
\r
737 * @arg ADC_Channel_19: ADC Channel19 selected
\r
738 * @arg ADC_Channel_20: ADC Channel20 selected
\r
739 * @arg ADC_Channel_21: ADC Channel21 selected
\r
740 * @arg ADC_Channel_22: ADC Channel22 selected
\r
741 * @arg ADC_Channel_23: ADC Channel23 selected
\r
742 * @arg ADC_Channel_24: ADC Channel24 selected
\r
743 * @arg ADC_Channel_25: ADC Channel25 selected
\r
744 * @param Rank: The rank in the regular group sequencer. This parameter
\r
745 * must be between 1 to 26.
\r
746 * @param ADC_SampleTime: The sample time value to be set for the selected
\r
748 * This parameter can be one of the following values:
\r
749 * @arg ADC_SampleTime_4Cycles: Sample time equal to 4 cycles
\r
750 * @arg ADC_SampleTime_9Cycles: Sample time equal to 9 cycles
\r
751 * @arg ADC_SampleTime_16Cycles: Sample time equal to 16 cycles
\r
752 * @arg ADC_SampleTime_24Cycles: Sample time equal to 24 cycles
\r
753 * @arg ADC_SampleTime_48Cycles: Sample time equal to 48 cycles
\r
754 * @arg ADC_SampleTime_96Cycles: Sample time equal to 96 cycles
\r
755 * @arg ADC_SampleTime_192Cycles: Sample time equal to 192 cycles
\r
756 * @arg ADC_SampleTime_384Cycles: Sample time equal to 384 cycles
\r
759 void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)
\r
761 uint32_t tmpreg1 = 0, tmpreg2 = 0;
\r
763 /* Check the parameters */
\r
764 assert_param(IS_ADC_ALL_PERIPH(ADCx));
\r
765 assert_param(IS_ADC_CHANNEL(ADC_Channel));
\r
766 assert_param(IS_ADC_REGULAR_RANK(Rank));
\r
767 assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime));
\r
769 /* if ADC_Channel_20 ... ADC_Channel_25 is selected */
\r
770 if (ADC_Channel > ADC_Channel_19)
\r
772 /* Get the old register value */
\r
773 tmpreg1 = ADCx->SMPR1;
\r
774 /* Calculate the mask to clear */
\r
775 tmpreg2 = SMPR1_SMP_SET << (3 * (ADC_Channel - 20));
\r
776 /* Clear the old sample time */
\r
777 tmpreg1 &= ~tmpreg2;
\r
778 /* Calculate the mask to set */
\r
779 tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 20));
\r
780 /* Set the new sample time */
\r
781 tmpreg1 |= tmpreg2;
\r
782 /* Store the new register value */
\r
783 ADCx->SMPR1 = tmpreg1;
\r
786 /* if ADC_Channel_10 ... ADC_Channel_19 is selected */
\r
787 else if (ADC_Channel > ADC_Channel_9)
\r
789 /* Get the old register value */
\r
790 tmpreg1 = ADCx->SMPR2;
\r
791 /* Calculate the mask to clear */
\r
792 tmpreg2 = SMPR2_SMP_SET << (3 * (ADC_Channel - 10));
\r
793 /* Clear the old sample time */
\r
794 tmpreg1 &= ~tmpreg2;
\r
795 /* Calculate the mask to set */
\r
796 tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10));
\r
797 /* Set the new sample time */
\r
798 tmpreg1 |= tmpreg2;
\r
799 /* Store the new register value */
\r
800 ADCx->SMPR2 = tmpreg1;
\r
803 else /* ADC_Channel include in ADC_Channel_[0..9] */
\r
805 /* Get the old register value */
\r
806 tmpreg1 = ADCx->SMPR3;
\r
807 /* Calculate the mask to clear */
\r
808 tmpreg2 = SMPR3_SMP_SET << (3 * ADC_Channel);
\r
809 /* Clear the old sample time */
\r
810 tmpreg1 &= ~tmpreg2;
\r
811 /* Calculate the mask to set */
\r
812 tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel);
\r
813 /* Set the new sample time */
\r
814 tmpreg1 |= tmpreg2;
\r
815 /* Store the new register value */
\r
816 ADCx->SMPR3 = tmpreg1;
\r
818 /* For Rank 1 to 6 */
\r
821 /* Get the old register value */
\r
822 tmpreg1 = ADCx->SQR5;
\r
823 /* Calculate the mask to clear */
\r
824 tmpreg2 = SQR5_SQ_SET << (5 * (Rank - 1));
\r
825 /* Clear the old SQx bits for the selected rank */
\r
826 tmpreg1 &= ~tmpreg2;
\r
827 /* Calculate the mask to set */
\r
828 tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 1));
\r
829 /* Set the SQx bits for the selected rank */
\r
830 tmpreg1 |= tmpreg2;
\r
831 /* Store the new register value */
\r
832 ADCx->SQR5 = tmpreg1;
\r
834 /* For Rank 7 to 12 */
\r
835 else if (Rank < 13)
\r
837 /* Get the old register value */
\r
838 tmpreg1 = ADCx->SQR4;
\r
839 /* Calculate the mask to clear */
\r
840 tmpreg2 = SQR4_SQ_SET << (5 * (Rank - 7));
\r
841 /* Clear the old SQx bits for the selected rank */
\r
842 tmpreg1 &= ~tmpreg2;
\r
843 /* Calculate the mask to set */
\r
844 tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 7));
\r
845 /* Set the SQx bits for the selected rank */
\r
846 tmpreg1 |= tmpreg2;
\r
847 /* Store the new register value */
\r
848 ADCx->SQR4 = tmpreg1;
\r
850 /* For Rank 13 to 18 */
\r
851 else if (Rank < 19)
\r
853 /* Get the old register value */
\r
854 tmpreg1 = ADCx->SQR3;
\r
855 /* Calculate the mask to clear */
\r
856 tmpreg2 = SQR3_SQ_SET << (5 * (Rank - 13));
\r
857 /* Clear the old SQx bits for the selected rank */
\r
858 tmpreg1 &= ~tmpreg2;
\r
859 /* Calculate the mask to set */
\r
860 tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 13));
\r
861 /* Set the SQx bits for the selected rank */
\r
862 tmpreg1 |= tmpreg2;
\r
863 /* Store the new register value */
\r
864 ADCx->SQR3 = tmpreg1;
\r
867 /* For Rank 19 to 24 */
\r
868 else if (Rank < 25)
\r
870 /* Get the old register value */
\r
871 tmpreg1 = ADCx->SQR2;
\r
872 /* Calculate the mask to clear */
\r
873 tmpreg2 = SQR2_SQ_SET << (5 * (Rank - 19));
\r
874 /* Clear the old SQx bits for the selected rank */
\r
875 tmpreg1 &= ~tmpreg2;
\r
876 /* Calculate the mask to set */
\r
877 tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 19));
\r
878 /* Set the SQx bits for the selected rank */
\r
879 tmpreg1 |= tmpreg2;
\r
880 /* Store the new register value */
\r
881 ADCx->SQR2 = tmpreg1;
\r
884 /* For Rank 25 to 27 */
\r
887 /* Get the old register value */
\r
888 tmpreg1 = ADCx->SQR1;
\r
889 /* Calculate the mask to clear */
\r
890 tmpreg2 = SQR1_SQ_SET << (5 * (Rank - 25));
\r
891 /* Clear the old SQx bits for the selected rank */
\r
892 tmpreg1 &= ~tmpreg2;
\r
893 /* Calculate the mask to set */
\r
894 tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 25));
\r
895 /* Set the SQx bits for the selected rank */
\r
896 tmpreg1 |= tmpreg2;
\r
897 /* Store the new register value */
\r
898 ADCx->SQR1 = tmpreg1;
\r
903 * @brief Enables the selected ADC software start conversion of the regular channels.
\r
904 * @param ADCx: where x can be 1 to select the ADC1 peripheral.
\r
907 void ADC_SoftwareStartConv(ADC_TypeDef* ADCx)
\r
909 /* Check the parameters */
\r
910 assert_param(IS_ADC_ALL_PERIPH(ADCx));
\r
912 /* Enable the selected ADC conversion for regular group */
\r
913 ADCx->CR2 |= (uint32_t)ADC_CR2_SWSTART;
\r
917 * @brief Gets the selected ADC Software start regular conversion Status.
\r
918 * @param ADCx: where x can be 1 to select the ADC1 peripheral.
\r
919 * @retval The new state of ADC software start conversion (SET or RESET).
\r
921 FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx)
\r
923 FlagStatus bitstatus = RESET;
\r
925 /* Check the parameters */
\r
926 assert_param(IS_ADC_ALL_PERIPH(ADCx));
\r
928 /* Check the status of SWSTART bit */
\r
929 if ((ADCx->CR2 & ADC_CR2_SWSTART) != (uint32_t)RESET)
\r
931 /* SWSTART bit is set */
\r
936 /* SWSTART bit is reset */
\r
939 /* Return the SWSTART bit status */
\r
944 * @brief Enables or disables the EOC on each regular channel conversion
\r
945 * @param ADCx: where x can be 1 to select the ADC1 peripheral.
\r
946 * @param NewState: new state of the selected ADC EOC flag rising
\r
947 * This parameter can be: ENABLE or DISABLE.
\r
950 void ADC_EOCOnEachRegularChannelCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
\r
952 /* Check the parameters */
\r
953 assert_param(IS_ADC_ALL_PERIPH(ADCx));
\r
954 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
956 if (NewState != DISABLE)
\r
958 /* Enable the selected ADC EOC rising on each regular channel conversion */
\r
959 ADCx->CR2 |= ADC_CR2_EOCS;
\r
963 /* Disable the selected ADC EOC rising on each regular channel conversion */
\r
964 ADCx->CR2 &= (uint32_t)~ADC_CR2_EOCS;
\r
969 * @brief Enables or disables the ADC continuous conversion mode
\r
970 * @param ADCx: where x can be 1 to select the ADC1 peripheral.
\r
971 * @param NewState: new state of the selected ADC continuous conversion mode
\r
972 * This parameter can be: ENABLE or DISABLE.
\r
975 void ADC_ContinuousModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
\r
977 /* Check the parameters */
\r
978 assert_param(IS_ADC_ALL_PERIPH(ADCx));
\r
979 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
981 if (NewState != DISABLE)
\r
983 /* Enable the selected ADC continuous conversion mode */
\r
984 ADCx->CR2 |= (uint32_t)ADC_CR2_CONT;
\r
988 /* Disable the selected ADC continuous conversion mode */
\r
989 ADCx->CR2 &= (uint32_t)(~ADC_CR2_CONT);
\r
994 * @brief Configures the discontinuous mode for the selected ADC regular
\r
996 * @param ADCx: where x can be 1 to select the ADC1 peripheral.
\r
997 * @param Number: specifies the discontinuous mode regular channel count value.
\r
998 * This number must be between 1 and 8.
\r
1001 void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number)
\r
1003 uint32_t tmpreg1 = 0;
\r
1004 uint32_t tmpreg2 = 0;
\r
1006 /* Check the parameters */
\r
1007 assert_param(IS_ADC_ALL_PERIPH(ADCx));
\r
1008 assert_param(IS_ADC_REGULAR_DISC_NUMBER(Number));
\r
1010 /* Get the old register value */
\r
1011 tmpreg1 = ADCx->CR1;
\r
1012 /* Clear the old discontinuous mode channel count */
\r
1013 tmpreg1 &= CR1_DISCNUM_RESET;
\r
1014 /* Set the discontinuous mode channel count */
\r
1015 tmpreg2 = Number - 1;
\r
1016 tmpreg1 |= tmpreg2 << 13;
\r
1017 /* Store the new register value */
\r
1018 ADCx->CR1 = tmpreg1;
\r
1022 * @brief Enables or disables the discontinuous mode on regular group
\r
1023 * channel for the specified ADC
\r
1024 * @param ADCx: where x can be 1 to select the ADC1 peripheral.
\r
1025 * @param NewState: new state of the selected ADC discontinuous mode on regular
\r
1027 * This parameter can be: ENABLE or DISABLE.
\r
1030 void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
\r
1032 /* Check the parameters */
\r
1033 assert_param(IS_ADC_ALL_PERIPH(ADCx));
\r
1034 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
1036 if (NewState != DISABLE)
\r
1038 /* Enable the selected ADC regular discontinuous mode */
\r
1039 ADCx->CR1 |= (uint32_t)ADC_CR1_DISCEN;
\r
1043 /* Disable the selected ADC regular discontinuous mode */
\r
1044 ADCx->CR1 &= (uint32_t)(~ADC_CR1_DISCEN);
\r
1049 * @brief Returns the last ADCx conversion result data for regular channel.
\r
1050 * @param ADCx: where x can be 1 to select the ADC1 peripheral.
\r
1051 * @retval The Data conversion value.
\r
1053 uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx)
\r
1055 /* Check the parameters */
\r
1056 assert_param(IS_ADC_ALL_PERIPH(ADCx));
\r
1058 /* Return the selected ADC conversion value */
\r
1059 return (uint16_t) ADCx->DR;
\r
1066 /** @defgroup ADC_Group6 Regular Channels DMA Configuration functions
\r
1067 * @brief Regular Channels DMA Configuration functions
\r
1070 ===============================================================================
\r
1071 Regular Channels DMA Configuration functions
\r
1072 ===============================================================================
\r
1074 This section provides functions allowing to configure the DMA for ADC regular
\r
1076 Since converted regular channel values are stored into a unique data register,
\r
1077 it is useful to use DMA for conversion of more than one regular channel. This
\r
1078 avoids the loss of the data already stored in the ADC Data register.
\r
1080 When the DMA mode is enabled (using the ADC_DMACmd() function), after each
\r
1081 conversion of a regular channel, a DMA request is generated.
\r
1083 Depending on the "DMA disable selection" configuration (using the
\r
1084 ADC_DMARequestAfterLastTransferCmd() function), at the end of the last DMA
\r
1085 transfer, two possibilities are allowed:
\r
1086 - No new DMA request is issued to the DMA controller (feature DISABLED)
\r
1087 - Requests can continue to be generated (feature ENABLED).
\r
1094 * @brief Enables or disables the specified ADC DMA request.
\r
1095 * @param ADCx: where x can be 1 to select the ADC1 peripheral.
\r
1096 * @param NewState: new state of the selected ADC DMA transfer.
\r
1097 * This parameter can be: ENABLE or DISABLE.
\r
1100 void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState)
\r
1102 /* Check the parameters */
\r
1103 assert_param(IS_ADC_DMA_PERIPH(ADCx));
\r
1104 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
1106 if (NewState != DISABLE)
\r
1108 /* Enable the selected ADC DMA request */
\r
1109 ADCx->CR2 |= (uint32_t)ADC_CR2_DMA;
\r
1113 /* Disable the selected ADC DMA request */
\r
1114 ADCx->CR2 &= (uint32_t)(~ADC_CR2_DMA);
\r
1120 * @brief Enables or disables the ADC DMA request after last transfer (Single-ADC mode)
\r
1121 * @param ADCx: where x can be 1 to select the ADC1 peripheral.
\r
1122 * @param NewState: new state of the selected ADC EOC flag rising
\r
1123 * This parameter can be: ENABLE or DISABLE.
\r
1126 void ADC_DMARequestAfterLastTransferCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
\r
1128 /* Check the parameters */
\r
1129 assert_param(IS_ADC_ALL_PERIPH(ADCx));
\r
1130 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
1132 if (NewState != DISABLE)
\r
1134 /* Enable the selected ADC DMA request after last transfer */
\r
1135 ADCx->CR2 |= ADC_CR2_DDS;
\r
1139 /* Disable the selected ADC DMA request after last transfer */
\r
1140 ADCx->CR2 &= (uint32_t)~ADC_CR2_DDS;
\r
1148 /** @defgroup ADC_Group7 Injected channels Configuration functions
\r
1149 * @brief Injected channels Configuration functions
\r
1152 ===============================================================================
\r
1153 Injected channels Configuration functions
\r
1154 ===============================================================================
\r
1156 This section provide functions allowing to configure the ADC Injected channels,
\r
1157 it is composed of 2 sub sections :
\r
1159 1. Configuration functions for Injected channels: This subsection provides
\r
1160 functions allowing to configure the ADC injected channels :
\r
1161 - Configure the rank in the injected group sequencer for each channel
\r
1162 - Configure the sampling time for each channel
\r
1163 - Activate the Auto injected Mode
\r
1164 - Activate the Discontinuous Mode
\r
1165 - scan mode activation
\r
1166 - External/software trigger source
\r
1167 - External trigger edge
\r
1168 - injected channels sequencer.
\r
1170 2. Get the Specified Injected channel conversion data: This subsection
\r
1171 provides an important function in the ADC peripheral since it returns the
\r
1172 converted data of the specific injected channel.
\r
1179 * @brief Configures for the selected ADC injected channel its corresponding
\r
1180 * rank in the sequencer and its sample time.
\r
1181 * @param ADCx: where x can be 1 to select the ADC1 peripheral.
\r
1182 * @param ADC_Channel: the ADC channel to configure.
\r
1183 * This parameter can be one of the following values:
\r
1184 * @arg ADC_Channel_0: ADC Channel0 selected
\r
1185 * @arg ADC_Channel_1: ADC Channel1 selected
\r
1186 * @arg ADC_Channel_2: ADC Channel2 selected
\r
1187 * @arg ADC_Channel_3: ADC Channel3 selected
\r
1188 * @arg ADC_Channel_4: ADC Channel4 selected
\r
1189 * @arg ADC_Channel_5: ADC Channel5 selected
\r
1190 * @arg ADC_Channel_6: ADC Channel6 selected
\r
1191 * @arg ADC_Channel_7: ADC Channel7 selected
\r
1192 * @arg ADC_Channel_8: ADC Channel8 selected
\r
1193 * @arg ADC_Channel_9: ADC Channel9 selected
\r
1194 * @arg ADC_Channel_10: ADC Channel10 selected
\r
1195 * @arg ADC_Channel_11: ADC Channel11 selected
\r
1196 * @arg ADC_Channel_12: ADC Channel12 selected
\r
1197 * @arg ADC_Channel_13: ADC Channel13 selected
\r
1198 * @arg ADC_Channel_14: ADC Channel14 selected
\r
1199 * @arg ADC_Channel_15: ADC Channel15 selected
\r
1200 * @arg ADC_Channel_16: ADC Channel16 selected
\r
1201 * @arg ADC_Channel_17: ADC Channel17 selected
\r
1202 * @arg ADC_Channel_18: ADC Channel18 selected
\r
1203 * @arg ADC_Channel_19: ADC Channel19 selected
\r
1204 * @arg ADC_Channel_20: ADC Channel20 selected
\r
1205 * @arg ADC_Channel_21: ADC Channel21 selected
\r
1206 * @arg ADC_Channel_22: ADC Channel22 selected
\r
1207 * @arg ADC_Channel_23: ADC Channel23 selected
\r
1208 * @arg ADC_Channel_24: ADC Channel24 selected
\r
1209 * @arg ADC_Channel_25: ADC Channel25 selected
\r
1210 * @param Rank: The rank in the injected group sequencer. This parameter
\r
1211 * must be between 1 to 4.
\r
1212 * @param ADC_SampleTime: The sample time value to be set for the selected
\r
1213 * channel. This parameter can be one of the following values:
\r
1214 * @arg ADC_SampleTime_4Cycles: Sample time equal to 4 cycles
\r
1215 * @arg ADC_SampleTime_9Cycles: Sample time equal to 9 cycles
\r
1216 * @arg ADC_SampleTime_16Cycles: Sample time equal to 16 cycles
\r
1217 * @arg ADC_SampleTime_24Cycles: Sample time equal to 24 cycles
\r
1218 * @arg ADC_SampleTime_48Cycles: Sample time equal to 48 cycles
\r
1219 * @arg ADC_SampleTime_96Cycles: Sample time equal to 96 cycles
\r
1220 * @arg ADC_SampleTime_192Cycles: Sample time equal to 192 cycles
\r
1221 * @arg ADC_SampleTime_384Cycles: Sample time equal to 384 cycles
\r
1224 void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)
\r
1226 uint32_t tmpreg1 = 0, tmpreg2 = 0, tmpreg3 = 0;
\r
1228 /* Check the parameters */
\r
1229 assert_param(IS_ADC_ALL_PERIPH(ADCx));
\r
1230 assert_param(IS_ADC_CHANNEL(ADC_Channel));
\r
1231 assert_param(IS_ADC_INJECTED_RANK(Rank));
\r
1232 assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime));
\r
1234 /* if ADC_Channel_20 ... ADC_Channel_25 is selected */
\r
1235 if (ADC_Channel > ADC_Channel_19)
\r
1237 /* Get the old register value */
\r
1238 tmpreg1 = ADCx->SMPR1;
\r
1239 /* Calculate the mask to clear */
\r
1240 tmpreg2 = SMPR1_SMP_SET << (3 * (ADC_Channel - 20));
\r
1241 /* Clear the old sample time */
\r
1242 tmpreg1 &= ~tmpreg2;
\r
1243 /* Calculate the mask to set */
\r
1244 tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 20));
\r
1245 /* Set the new sample time */
\r
1246 tmpreg1 |= tmpreg2;
\r
1247 /* Store the new register value */
\r
1248 ADCx->SMPR1 = tmpreg1;
\r
1251 /* if ADC_Channel_10 ... ADC_Channel_19 is selected */
\r
1252 else if (ADC_Channel > ADC_Channel_9)
\r
1254 /* Get the old register value */
\r
1255 tmpreg1 = ADCx->SMPR2;
\r
1256 /* Calculate the mask to clear */
\r
1257 tmpreg2 = SMPR2_SMP_SET << (3 * (ADC_Channel - 10));
\r
1258 /* Clear the old sample time */
\r
1259 tmpreg1 &= ~tmpreg2;
\r
1260 /* Calculate the mask to set */
\r
1261 tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10));
\r
1262 /* Set the new sample time */
\r
1263 tmpreg1 |= tmpreg2;
\r
1264 /* Store the new register value */
\r
1265 ADCx->SMPR2 = tmpreg1;
\r
1268 else /* ADC_Channel include in ADC_Channel_[0..9] */
\r
1270 /* Get the old register value */
\r
1271 tmpreg1 = ADCx->SMPR3;
\r
1272 /* Calculate the mask to clear */
\r
1273 tmpreg2 = SMPR3_SMP_SET << (3 * ADC_Channel);
\r
1274 /* Clear the old sample time */
\r
1275 tmpreg1 &= ~tmpreg2;
\r
1276 /* Calculate the mask to set */
\r
1277 tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel);
\r
1278 /* Set the new sample time */
\r
1279 tmpreg1 |= tmpreg2;
\r
1280 /* Store the new register value */
\r
1281 ADCx->SMPR3 = tmpreg1;
\r
1284 /* Rank configuration */
\r
1285 /* Get the old register value */
\r
1286 tmpreg1 = ADCx->JSQR;
\r
1287 /* Get JL value: Number = JL+1 */
\r
1288 tmpreg3 = (tmpreg1 & JSQR_JL_SET)>> 20;
\r
1289 /* Calculate the mask to clear: ((Rank-1)+(4- (JL+1))) */
\r
1290 tmpreg2 = JSQR_JSQ_SET << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1)));
\r
1291 /* Clear the old JSQx bits for the selected rank */
\r
1292 tmpreg1 &= ~tmpreg2;
\r
1293 /* Calculate the mask to set: ((Rank-1)+(4- (JL+1))) */
\r
1294 tmpreg2 = (uint32_t)ADC_Channel << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1)));
\r
1295 /* Set the JSQx bits for the selected rank */
\r
1296 tmpreg1 |= tmpreg2;
\r
1297 /* Store the new register value */
\r
1298 ADCx->JSQR = tmpreg1;
\r
1302 * @brief Configures the sequencer length for injected channels
\r
1303 * @param ADCx: where x can be 1 to select the ADC1 peripheral.
\r
1304 * @param Length: The sequencer length.
\r
1305 * This parameter must be a number between 1 to 4.
\r
1308 void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length)
\r
1310 uint32_t tmpreg1 = 0;
\r
1311 uint32_t tmpreg2 = 0;
\r
1313 /* Check the parameters */
\r
1314 assert_param(IS_ADC_ALL_PERIPH(ADCx));
\r
1315 assert_param(IS_ADC_INJECTED_LENGTH(Length));
\r
1317 /* Get the old register value */
\r
1318 tmpreg1 = ADCx->JSQR;
\r
1319 /* Clear the old injected sequence length JL bits */
\r
1320 tmpreg1 &= JSQR_JL_RESET;
\r
1321 /* Set the injected sequence length JL bits */
\r
1322 tmpreg2 = Length - 1;
\r
1323 tmpreg1 |= tmpreg2 << 20;
\r
1324 /* Store the new register value */
\r
1325 ADCx->JSQR = tmpreg1;
\r
1329 * @brief Set the injected channels conversion value offset
\r
1330 * @param ADCx: where x can be 1 to select the ADC1 peripheral.
\r
1331 * @param ADC_InjectedChannel: the ADC injected channel to set its offset.
\r
1332 * This parameter can be one of the following values:
\r
1333 * @arg ADC_InjectedChannel_1: Injected Channel1 selected
\r
1334 * @arg ADC_InjectedChannel_2: Injected Channel2 selected
\r
1335 * @arg ADC_InjectedChannel_3: Injected Channel3 selected
\r
1336 * @arg ADC_InjectedChannel_4: Injected Channel4 selected
\r
1337 * @param Offset: the offset value for the selected ADC injected channel
\r
1338 * This parameter must be a 12bit value.
\r
1341 void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset)
\r
1343 __IO uint32_t tmp = 0;
\r
1345 /* Check the parameters */
\r
1346 assert_param(IS_ADC_ALL_PERIPH(ADCx));
\r
1347 assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel));
\r
1348 assert_param(IS_ADC_OFFSET(Offset));
\r
1350 tmp = (uint32_t)ADCx;
\r
1351 tmp += ADC_InjectedChannel;
\r
1353 /* Set the selected injected channel data offset */
\r
1354 *(__IO uint32_t *) tmp = (uint32_t)Offset;
\r
1358 * @brief Configures the ADCx external trigger for injected channels conversion.
\r
1359 * @param ADCx: where x can be 1 to select the ADC1 peripheral.
\r
1360 * @param ADC_ExternalTrigInjecConv: specifies the ADC trigger to start injected
\r
1361 * conversion. This parameter can be one of the following values:
\r
1362 * @arg ADC_ExternalTrigInjecConv_T9_CC1: Timer9 capture compare1 selected
\r
1363 * @arg ADC_ExternalTrigInjecConv_T9_TRGO: Timer9 TRGO event selected
\r
1364 * @arg ADC_ExternalTrigInjecConv_T2_TRGO: Timer2 TRGO event selected
\r
1365 * @arg ADC_ExternalTrigInjecConv_T2_CC1: Timer2 capture compare1 selected
\r
1366 * @arg ADC_ExternalTrigInjecConv_T3_CC4: Timer3 capture compare4 selected
\r
1367 * @arg ADC_ExternalTrigInjecConv_T4_TRGO: Timer4 TRGO event selected
\r
1368 * @arg ADC_ExternalTrigInjecConv_T4_CC1: Timer4 capture compare1 selected
\r
1369 * @arg ADC_ExternalTrigInjecConv_T4_CC2: Timer4 capture compare2 selected
\r
1370 * @arg ADC_ExternalTrigInjecConv_T4_CC3: Timer4 capture compare3 selected
\r
1371 * @arg ADC_ExternalTrigInjecConv_T10_CC1: Timer10 capture compare1 selected
\r
1372 * @arg ADC_ExternalTrigInjecConv_T7_TRGO: Timer7 TRGO event selected
\r
1373 * @arg ADC_ExternalTrigInjecConv_Ext_IT15: External interrupt line 15 event selected
\r
1376 void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv)
\r
1378 uint32_t tmpreg = 0;
\r
1380 /* Check the parameters */
\r
1381 assert_param(IS_ADC_ALL_PERIPH(ADCx));
\r
1382 assert_param(IS_ADC_EXT_INJEC_TRIG(ADC_ExternalTrigInjecConv));
\r
1384 /* Get the old register value */
\r
1385 tmpreg = ADCx->CR2;
\r
1386 /* Clear the old external event selection for injected group */
\r
1387 tmpreg &= CR2_JEXTSEL_RESET;
\r
1388 /* Set the external event selection for injected group */
\r
1389 tmpreg |= ADC_ExternalTrigInjecConv;
\r
1390 /* Store the new register value */
\r
1391 ADCx->CR2 = tmpreg;
\r
1395 * @brief Configures the ADCx external trigger edge for injected channels conversion.
\r
1396 * @param ADCx: where x can be 1 to select the ADC1 peripheral.
\r
1397 * @param ADC_ExternalTrigInjecConvEdge: specifies the ADC external trigger
\r
1398 * edge to start injected conversion.
\r
1399 * This parameter can be one of the following values:
\r
1400 * @arg ADC_ExternalTrigConvEdge_None: external trigger disabled for
\r
1401 * injected conversion
\r
1402 * @arg ADC_ExternalTrigConvEdge_Rising: detection on rising edge
\r
1403 * @arg ADC_ExternalTrigConvEdge_Falling: detection on falling edge
\r
1404 * @arg ADC_External ADC_ExternalTrigConvEdge_RisingFalling: detection on
\r
1405 * both rising and falling edge
\r
1408 void ADC_ExternalTrigInjectedConvEdgeConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConvEdge)
\r
1410 uint32_t tmpreg = 0;
\r
1412 /* Check the parameters */
\r
1413 assert_param(IS_ADC_ALL_PERIPH(ADCx));
\r
1414 assert_param(IS_ADC_EXT_INJEC_TRIG_EDGE(ADC_ExternalTrigInjecConvEdge));
\r
1416 /* Get the old register value */
\r
1417 tmpreg = ADCx->CR2;
\r
1418 /* Clear the old external trigger edge for injected group */
\r
1419 tmpreg &= CR2_JEXTEN_RESET;
\r
1420 /* Set the new external trigger edge for injected group */
\r
1421 tmpreg |= ADC_ExternalTrigInjecConvEdge;
\r
1422 /* Store the new register value */
\r
1423 ADCx->CR2 = tmpreg;
\r
1427 * @brief Enables the selected ADC software start conversion of the injected
\r
1429 * @param ADCx: where x can be 1 to select the ADC1 peripheral.
\r
1432 void ADC_SoftwareStartInjectedConv(ADC_TypeDef* ADCx)
\r
1434 /* Check the parameters */
\r
1435 assert_param(IS_ADC_ALL_PERIPH(ADCx));
\r
1436 /* Enable the selected ADC conversion for injected group */
\r
1437 ADCx->CR2 |= (uint32_t)ADC_CR2_JSWSTART;
\r
1441 * @brief Gets the selected ADC Software start injected conversion Status.
\r
1442 * @param ADCx: where x can be 1 to select the ADC1 peripheral.
\r
1443 * @retval The new state of ADC software start injected conversion (SET or RESET).
\r
1445 FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx)
\r
1447 FlagStatus bitstatus = RESET;
\r
1449 /* Check the parameters */
\r
1450 assert_param(IS_ADC_ALL_PERIPH(ADCx));
\r
1452 /* Check the status of JSWSTART bit */
\r
1453 if ((ADCx->CR2 & ADC_CR2_JSWSTART) != (uint32_t)RESET)
\r
1455 /* JSWSTART bit is set */
\r
1460 /* JSWSTART bit is reset */
\r
1461 bitstatus = RESET;
\r
1463 /* Return the JSWSTART bit status */
\r
1468 * @brief Enables or disables the selected ADC automatic injected group
\r
1469 * conversion after regular one.
\r
1470 * @param ADCx: where x can be 1 to select the ADC1 peripheral.
\r
1471 * @param NewState: new state of the selected ADC auto injected
\r
1473 * This parameter can be: ENABLE or DISABLE.
\r
1476 void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
\r
1478 /* Check the parameters */
\r
1479 assert_param(IS_ADC_ALL_PERIPH(ADCx));
\r
1480 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
1482 if (NewState != DISABLE)
\r
1484 /* Enable the selected ADC automatic injected group conversion */
\r
1485 ADCx->CR1 |= (uint32_t)ADC_CR1_JAUTO;
\r
1489 /* Disable the selected ADC automatic injected group conversion */
\r
1490 ADCx->CR1 &= (uint32_t)(~ADC_CR1_JAUTO);
\r
1495 * @brief Enables or disables the discontinuous mode for injected group
\r
1496 * channel for the specified ADC
\r
1497 * @param ADCx: where x can be 1 to select the ADC1 peripheral.
\r
1498 * @param NewState: new state of the selected ADC discontinuous mode
\r
1499 * on injected group channel. This parameter can be: ENABLE or DISABLE.
\r
1502 void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
\r
1504 /* Check the parameters */
\r
1505 assert_param(IS_ADC_ALL_PERIPH(ADCx));
\r
1506 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
1508 if (NewState != DISABLE)
\r
1510 /* Enable the selected ADC injected discontinuous mode */
\r
1511 ADCx->CR1 |= (uint32_t)ADC_CR1_JDISCEN;
\r
1515 /* Disable the selected ADC injected discontinuous mode */
\r
1516 ADCx->CR1 &= (uint32_t)(~ADC_CR1_JDISCEN);
\r
1521 * @brief Returns the ADC injected channel conversion result
\r
1522 * @param ADCx: where x can be 1 to select the ADC1 peripheral.
\r
1523 * @param ADC_InjectedChannel: the converted ADC injected channel.
\r
1524 * This parameter can be one of the following values:
\r
1525 * @arg ADC_InjectedChannel_1: Injected Channel1 selected
\r
1526 * @arg ADC_InjectedChannel_2: Injected Channel2 selected
\r
1527 * @arg ADC_InjectedChannel_3: Injected Channel3 selected
\r
1528 * @arg ADC_InjectedChannel_4: Injected Channel4 selected
\r
1529 * @retval The Data conversion value.
\r
1531 uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel)
\r
1533 __IO uint32_t tmp = 0;
\r
1535 /* Check the parameters */
\r
1536 assert_param(IS_ADC_ALL_PERIPH(ADCx));
\r
1537 assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel));
\r
1539 tmp = (uint32_t)ADCx;
\r
1540 tmp += ADC_InjectedChannel + JDR_OFFSET;
\r
1542 /* Returns the selected injected channel conversion data value */
\r
1543 return (uint16_t) (*(__IO uint32_t*) tmp);
\r
1550 /** @defgroup ADC_Group8 Interrupts and flags management functions
\r
1551 * @brief Interrupts and flags management functions
\r
1554 ===============================================================================
\r
1555 Interrupts and flags management functions
\r
1556 ===============================================================================
\r
1558 This section provides functions allowing to configure the ADC Interrupts and get
\r
1559 the status and clear flags and Interrupts pending bits.
\r
1561 The ADC provide 4 Interrupts sources and 9 Flags which can be divided into 3 groups:
\r
1563 I. Flags and Interrupts for ADC regular channels
\r
1564 =================================================
\r
1567 1. ADC_FLAG_OVR : Overrun detection when regular converted data are lost
\r
1569 2. ADC_FLAG_EOC : Regular channel end of conversion + to indicate (depending
\r
1570 on EOCS bit, managed by ADC_EOCOnEachRegularChannelCmd() ) the end of :
\r
1571 ==> a regular CHANNEL conversion
\r
1572 ==> sequence of regular GROUP conversions .
\r
1574 3. ADC_FLAG_STRT: Regular channel start + to indicate when regular CHANNEL
\r
1575 conversion starts.
\r
1577 4. ADC_FLAG_RCNR: Regular channel not ready+ to indicate if a new regular
\r
1578 conversion can be launched
\r
1586 II. Flags and Interrupts for ADC Injected channels
\r
1587 =================================================
\r
1590 1. ADC_FLAG_JEOC : Injected channel end of conversion+ to indicate at
\r
1591 the end of injected GROUP conversion
\r
1593 2. ADC_FLAG_JSTRT: Injected channel start + to indicate hardware when
\r
1594 injected GROUP conversion starts.
\r
1596 3. ADC_FLAG_JCNR: Injected channel not ready + to indicate if a new
\r
1597 injected conversion can be launched.
\r
1603 III. General Flags and Interrupts for the ADC
\r
1604 =================================================
\r
1607 1. ADC_FLAG_AWD: Analog watchdog + to indicate if the converted voltage
\r
1608 crosses the programmed thresholds values.
\r
1610 2. ADC_FLAG_ADONS: ADC ON status + to indicate if the ADC is ready to convert.
\r
1621 * @brief Enables or disables the specified ADC interrupts.
\r
1622 * @param ADCx: where x can be 1 to select the ADC peripheral.
\r
1623 * @param ADC_IT: specifies the ADC interrupt sources to be enabled or disabled.
\r
1624 * This parameter can be one of the following values:
\r
1625 * @arg ADC_IT_EOC: End of conversion interrupt
\r
1626 * @arg ADC_IT_AWD: Analog watchdog interrupt
\r
1627 * @arg ADC_IT_JEOC: End of injected conversion interrupt
\r
1628 * @arg ADC_IT_OVR: overrun interrupt
\r
1629 * @param NewState: new state of the specified ADC interrupts.
\r
1630 * This parameter can be: ENABLE or DISABLE.
\r
1633 void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState)
\r
1635 uint32_t itmask = 0;
\r
1637 /* Check the parameters */
\r
1638 assert_param(IS_ADC_ALL_PERIPH(ADCx));
\r
1639 assert_param(IS_FUNCTIONAL_STATE(NewState));
\r
1640 assert_param(IS_ADC_IT(ADC_IT));
\r
1642 /* Get the ADC IT index */
\r
1643 itmask = (uint8_t)ADC_IT;
\r
1644 itmask = (uint32_t)0x01 << itmask;
\r
1646 if (NewState != DISABLE)
\r
1648 /* Enable the selected ADC interrupts */
\r
1649 ADCx->CR1 |= itmask;
\r
1653 /* Disable the selected ADC interrupts */
\r
1654 ADCx->CR1 &= (~(uint32_t)itmask);
\r
1659 * @brief Checks whether the specified ADC flag is set or not.
\r
1660 * @param ADCx: where x can be 1 to select the ADC1 peripheral.
\r
1661 * @param ADC_FLAG: specifies the flag to check.
\r
1662 * This parameter can be one of the following values:
\r
1663 * @arg ADC_FLAG_AWD: Analog watchdog flag
\r
1664 * @arg ADC_FLAG_EOC: End of conversion flag
\r
1665 * @arg ADC_FLAG_JEOC: End of injected group conversion flag
\r
1666 * @arg ADC_FLAG_JSTRT: Start of injected group conversion flag
\r
1667 * @arg ADC_FLAG_STRT: Start of regular group conversion flag
\r
1668 * @arg ADC_FLAG_OVR: Overrun flag
\r
1669 * @arg ADC_FLAG_ADONS: ADC ON status
\r
1670 * @arg ADC_FLAG_RCNR: Regular channel not ready
\r
1671 * @arg ADC_FLAG_JCNR: Injected channel not ready
\r
1672 * @retval The new state of ADC_FLAG (SET or RESET).
\r
1674 FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint16_t ADC_FLAG)
\r
1676 FlagStatus bitstatus = RESET;
\r
1678 /* Check the parameters */
\r
1679 assert_param(IS_ADC_ALL_PERIPH(ADCx));
\r
1680 assert_param(IS_ADC_GET_FLAG(ADC_FLAG));
\r
1682 /* Check the status of the specified ADC flag */
\r
1683 if ((ADCx->SR & ADC_FLAG) != (uint8_t)RESET)
\r
1685 /* ADC_FLAG is set */
\r
1690 /* ADC_FLAG is reset */
\r
1691 bitstatus = RESET;
\r
1693 /* Return the ADC_FLAG status */
\r
1698 * @brief Clears the ADCx's pending flags.
\r
1699 * @param ADCx: where x can be 1 to select the ADC1 peripheral.
\r
1700 * @param ADC_FLAG: specifies the flag to clear.
\r
1701 * This parameter can be any combination of the following values:
\r
1702 * @arg ADC_FLAG_AWD: Analog watchdog flag
\r
1703 * @arg ADC_FLAG_EOC: End of conversion flag
\r
1704 * @arg ADC_FLAG_JEOC: End of injected group conversion flag
\r
1705 * @arg ADC_FLAG_JSTRT: Start of injected group conversion flag
\r
1706 * @arg ADC_FLAG_STRT: Start of regular group conversion flag
\r
1707 * @arg ADC_FLAG_OVR: overrun flag
\r
1710 void ADC_ClearFlag(ADC_TypeDef* ADCx, uint16_t ADC_FLAG)
\r
1712 /* Check the parameters */
\r
1713 assert_param(IS_ADC_ALL_PERIPH(ADCx));
\r
1714 assert_param(IS_ADC_CLEAR_FLAG(ADC_FLAG));
\r
1716 /* Clear the selected ADC flags */
\r
1717 ADCx->SR = ~(uint32_t)ADC_FLAG;
\r
1721 * @brief Checks whether the specified ADC interrupt has occurred or not.
\r
1722 * @param ADCx: where x can be 1 to select the ADC1 peripheral.
\r
1723 * @param ADC_IT: specifies the ADC interrupt source to check.
\r
1724 * This parameter can be one of the following values:
\r
1725 * @arg ADC_IT_EOC: End of conversion interrupt
\r
1726 * @arg ADC_IT_AWD: Analog watchdog interrupt
\r
1727 * @arg ADC_IT_JEOC: End of injected conversion interrupt
\r
1728 * @arg ADC_IT_OVR: Overrun interrupt
\r
1729 * @retval The new state of ADC_IT (SET or RESET).
\r
1731 ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT)
\r
1733 ITStatus bitstatus = RESET;
\r
1734 uint32_t itmask = 0, enablestatus = 0;
\r
1736 /* Check the parameters */
\r
1737 assert_param(IS_ADC_ALL_PERIPH(ADCx));
\r
1738 assert_param(IS_ADC_IT(ADC_IT));
\r
1740 /* Get the ADC IT index */
\r
1741 itmask = (uint32_t)((uint32_t)ADC_IT >> 8);
\r
1743 /* Get the ADC_IT enable bit status */
\r
1744 enablestatus = (ADCx->CR1 & ((uint32_t)0x01 << (uint8_t)ADC_IT));
\r
1746 /* Check the status of the specified ADC interrupt */
\r
1747 if (((uint32_t)(ADCx->SR & (uint32_t)itmask) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))
\r
1749 /* ADC_IT is set */
\r
1754 /* ADC_IT is reset */
\r
1755 bitstatus = RESET;
\r
1757 /* Return the ADC_IT status */
\r
1762 * @brief Clears the ADCx
\92s interrupt pending bits.
\r
1763 * @param ADCx: where x can be 1 to select the ADC1 peripheral.
\r
1764 * @param ADC_IT: specifies the ADC interrupt pending bit to clear.
\r
1765 * This parameter can be one of the following values:
\r
1766 * @arg ADC_IT_EOC: End of conversion interrupt
\r
1767 * @arg ADC_IT_AWD: Analog watchdog interrupt
\r
1768 * @arg ADC_IT_JEOC: End of injected conversion interrupt
\r
1769 * @arg ADC_IT_OVR: Overrun interrupt
\r
1772 void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT)
\r
1774 uint8_t itmask = 0;
\r
1776 /* Check the parameters */
\r
1777 assert_param(IS_ADC_ALL_PERIPH(ADCx));
\r
1778 assert_param(IS_ADC_IT(ADC_IT));
\r
1780 /* Get the ADC IT index */
\r
1781 itmask = (uint8_t)(ADC_IT >> 8);
\r
1783 /* Clear the selected ADC interrupt pending bits */
\r
1784 ADCx->SR = ~(uint32_t)itmask;
\r
1803 /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
\r