work in progress

git-svn-id: https://sdcc.svn.sourceforge.net/svnroot/sdcc/trunk/sdcc@1888 4a8a32a2-be11-0410-ad9d-d568d2c75423

diff --git a/sim/ucsim/xa.src/inst.cc b/sim/ucsim/xa.src/inst.cc
index 183deef7ba1e91f4c88ba2a658bf57fa4b639102..ed6f1f900e059539ed43be033630d3cd98a2c386 100644 (file)
--- a/sim/ucsim/xa.src/inst.cc
+++ b/sim/ucsim/xa.src/inst.cc
@@ -382,20 +382,17 @@ cl_xa::inst_BR(uint code, int operands)
 int
 cl_xa::inst_JMP(uint code, int operands)
 {
-  unsigned int jmpaddr;
-  short saddr;
+  int jmpAddr;
 
   switch(operands) {
     case REL16:
     {
-      saddr = fetch2();
-      jmpaddr = saddr;
-      jmpaddr *= 2;
-      PC = (PC + jmpaddr) & 0xfffffffe;
+      jmpAddr = (signed short)fetch2()*2;
+      PC = (PC + jmpAddr) & 0xfffffffe;
     }
     break;
     case IREG:
-      PC &= 0xffff0000;
+      PC &= 0xff0000;
       PC |= (reg2(RI_07) & 0xfffe);  /* word aligned */
     break;
     /* fixme 2 more... */
@@ -405,13 +402,13 @@ cl_xa::inst_JMP(uint code, int operands)
 int
 cl_xa::inst_CALL(uint code, int operands)
 {
-  unsigned int jmpaddr;
+  int jmpaddr;
   unsigned int sp;
 
   switch(operands) {
     case REL16:
     {
-      jmpaddr = fetch2();
+      jmpaddr = (signed short)fetch2();
       sp = get_sp() - 4;
       set_sp(sp);
       store2(sp, PC);
@@ -422,16 +419,18 @@ cl_xa::inst_CALL(uint code, int operands)
     break;
     case IREG:
     {
-      sp = get_sp() - 4;
+      sp = get_sp() - 2;
       set_sp(sp);
       store2(sp, PC);
-      store2(sp+2, 0);  /* segment(not sure about ordering...) */
+#if 0 // only in huge model
+      store2(sp+2, ...
+#endif
       jmpaddr = reg2(RI_07);
       jmpaddr *= 2;
       PC = (PC + jmpaddr) & 0xfffffffe;
     }
     break;
-    /* fixme 2 more... */
+    /* fixme 2 more... */ /* johan: which ones? */
   }
   return(resGO);
 }
@@ -442,7 +441,10 @@ cl_xa::inst_RET(uint code, int operands)
   unsigned short sp;
   sp = get_sp();
   retaddr = get2(sp);
-  //retaddr |= get2(sp+2) << 16);
+#if 0 // only in huge model
+  retaddr |= get2(sp+2) << 16;
+#endif
+  set_sp(sp+2);
   PC = retaddr;
   return(resGO);
 }
@@ -454,15 +456,22 @@ cl_xa::inst_Bcc(uint code, int operands)
 int
 cl_xa::inst_JB(uint code, int operands)
 {
-  short saddr = (fetch1() * 2);
-  if (get_psw() & BIT_Z) {
-      PC += saddr;
+  short bitAddr=((code&0x3)<<8) + fetch1();
+  short jmpAddr = (fetch1() * 2);
+  if (get_bit(bitAddr)) {
+    PC = (PC+jmpAddr)&0xfffffe;
   }
   return(resGO);
 }
 int
 cl_xa::inst_JNB(uint code, int operands)
 {
+  short bitAddr=((code&0x3)<<8) + fetch1();
+  short jmpAddr = (fetch1() * 2);
+  if (!get_bit(bitAddr)) {
+    PC = (PC+jmpAddr)&0xfffffe;
+  }
+  return(resGO);
   return(resGO);
 }
 int
@@ -573,7 +582,7 @@ cl_xa::inst_DJNZ(uint code, int operands)
 int
 cl_xa::inst_JZ(uint code, int operands)
 {
-  /* reg1(8) = R4.b, is ACC for MCS51 compatiblility */
+  /* reg1(8) = R4L, is ACC for MCS51 compatiblility */
   short saddr = (fetch1() * 2);
   if (reg1(8)==0) {
       PC += saddr;
@@ -584,7 +593,7 @@ int
 cl_xa::inst_JNZ(uint code, int operands)
 {
   short saddr = (fetch1() * 2);
-  /* reg1(8) = R4.b, is ACC for MCS51 compatiblility */
+  /* reg1(8) = R4L, is ACC for MCS51 compatiblility */
   if (reg1(8)!=0) {
     PC = (PC + saddr) & 0xfffffe;
   }

diff --git a/sim/ucsim/xa.src/regsxa.h b/sim/ucsim/xa.src/regsxa.h
index 8644882d7644b28d18147ed05ae6f88dda85f501..160e1cb18609811a8dcb4b29fcc5f8d2b74305fe 100644 (file)
--- a/sim/ucsim/xa.src/regsxa.h
+++ b/sim/ucsim/xa.src/regsxa.h
@@ -106,7 +106,11 @@ struct t_regs
     { set_reg1((_index), _value) } \
 }
 
-  /* R7 mirrors 1 of 2 real SP's */
+// fixme: implement
+#define get_bit(x) (x)
+#define set_bit(x,y)
+
+/* R7 mirrors 1 of 2 real SP's */
 #define set_sp(_value) { \
   { set_word_direct(0x400+(7*2), _value); } \
 }