+2001-10-11 Michael Hope <michaelh@juju.net.nz>
+
+ * src/z80/gen.c (gencjneshort): Fixed
+
+ * src/z80/ralloc.c (packRegsForHLUse): Added pack into HL for cast then ipush.
+
2001-10-09 Michael Hope <michaelh@juju.net.nz>
* support/regression/tests/bug-469671.c: Added.
enum
{
/* Set to enable debugging trace statements in the output assembly code. */
- DISABLE_DEBUG = 0,
+ DISABLE_DEBUG = 0
};
static char *_z80_return[] =
emit2 ("ld a,%s", aopGet (AOP (left), offset, FALSE));
if (size > 1)
{
- size--;
- offset++;
- while (size--)
+ while (--size)
{
- emit2 ("or a,%s", aopGet (AOP (left), offset, FALSE));
+ emit2 ("or a,%s", aopGet (AOP (left), ++offset, FALSE));
}
}
else
bit %3,a
jp %4,%5
} by {
- ; Rule 100: Removed redundent load
bit %3,%1(%2)
jp %4,%5
}
+replace {
+ ld %1,%2)
+ ld a,%2)
+} by {
+ ld %1,%2)
+ ld a,%1
+}
+replace {
+ ld %1),a
+ xor a,a
+ or a,%1)
+ jp z,%2
+} by {
+ ld %1),a
+ or a,a
+ jp z,%2
+}
replace restart {
ld %1,%1
} by {
- ; Rule 1: Removed redundent load
+ ; Removed redundent load
}
replace restart {
xor a,a
cp a,#0x00
jp nz,%1
} by {
- ; Rule 3: Changed cp #0 to or
or a,a
jp nz,%1
}
jp %3
%2:
} by {
- ; Rule 4: Changed jp order
jp z,%2
%1:
jp %3
jp %2
%1:
} by {
- ; Rule 5: Changed jump logic
jp z,%2
%1:
}
jp %2
%1:
} by {
- ; Rule 6: Changed jump logic
jp nz,%2
%1:
}
or a,%1
or a,a
} by {
- ; Rule 7: Removed redundent or
or a,%1
}
replace restart {
or a,%1)
or a,a
} by {
- ; Rule 8: Removed redundent or for (ix)
or a,%1)
}
replace restart {
if (ic->next != uic)
return;
+ if (ic->op == CAST && uic->op == IPUSH)
+ goto hluse;
if (ic->op == ADDRESS_OF && uic->op == IPUSH)
goto hluse;
if (ic->op == CALL && ic->parmBytes == 0 && (uic->op == '-' || uic->op == '+'))