small fixes

git-svn-id: https://sdcc.svn.sourceforge.net/svnroot/sdcc/trunk/sdcc@1885 4a8a32a2-be11-0410-ad9d-d568d2c75423

diff --git a/sim/ucsim/xa.src/glob.cc b/sim/ucsim/xa.src/glob.cc
index 660b07ff8f804ea1c41157b72bffe67ab4649c4d..685cc272d342c8ee90763f9879d3e7ba9c134efa 100644 (file)
--- a/sim/ucsim/xa.src/glob.cc
+++ b/sim/ucsim/xa.src/glob.cc
@@ -426,5 +426,24 @@ struct xa_dis_entry disass_xa[]= {
  {0x0000,0x0000,  0,1,BAD_OPCODE, REG_REG}
 };
 
+#if 0
+/*
+ * Names of SFRs
+ */
+
+struct name_entry sfr_tabXA51[]=
+{
+  {CPU_XA51G3,                    0x400, "PSW"},
+};
+
+/*
+ * Names SBITs
+ */
+
+struct name_entry bit_tabXA51[]=
+{
+  {CPU_XA51G3,                    0x33b, "ETI1"},
+};
+#endif
 
 /* End of xa.src/glob.cc */

diff --git a/sim/ucsim/xa.src/inst.cc b/sim/ucsim/xa.src/inst.cc
index d32e909b70e4f97086d51ff70c2d345535dabb73..e53858350295ea9ee1b474e7237a577938f44cfa 100644 (file)
--- a/sim/ucsim/xa.src/inst.cc
+++ b/sim/ucsim/xa.src/inst.cc
@@ -329,11 +329,17 @@ cl_xa::inst_XCH(uint code, int operands)
 int
 cl_xa::inst_SETB(uint code, int operands)
 {
+  unsigned short bitAddr = (code&0x03 << 8) + fetch();
+  // fixme: implement
+  bitAddr=bitAddr;
   return(resGO);
 }
 int
 cl_xa::inst_CLR(uint code, int operands)
 {
+  unsigned short bitAddr = (code&0x03 << 8) + fetch();
+  // fixme: implement
+  bitAddr=bitAddr;
   return(resGO);
 }
 int
@@ -357,8 +363,19 @@ cl_xa::inst_ORL(uint code, int operands)
   return(resGO);
 }
 int
+cl_xa::inst_BEQ(uint code, int operands)
+{
+  short jmpAddr = fetch1()*2;
+  if (get_psw() & BIT_Z) {
+    PC=(PC+jmpAddr)&0xfffffffe;
+  }
+  return(resGO);
+}
+int
 cl_xa::inst_BR(uint code, int operands)
 {
+  short jmpAddr = fetch1()*2;
+  PC=(PC+jmpAddr)&0xfffffffe;
   return(resGO);
 }
 int
@@ -457,7 +474,7 @@ int
 cl_xa::inst_JZ(uint code, int operands)
 {
   short saddr = (fetch1() * 2);
-  if (get_psw() & BIT_Z) {
+  if (reg1(8)==0) {
       PC += saddr;
   }
   return(resGO);
@@ -466,8 +483,8 @@ int
 cl_xa::inst_JNZ(uint code, int operands)
 {
   short saddr = (fetch1() * 2);
-  if (!(get_psw() & BIT_Z)) {
-      PC += saddr;
+  if (reg1(8)!=0) {
+    PC = (PC + saddr) & 0xfffffe;
   }
   return(resGO);
 }

diff --git a/sim/ucsim/xa.src/instcl.h b/sim/ucsim/xa.src/instcl.h
index 821a5becb8bf3757758016754445be1950f407d4..5bc5f02238097d1de4f86ecb5d3604876f31340f 100644 (file)
--- a/sim/ucsim/xa.src/instcl.h
+++ b/sim/ucsim/xa.src/instcl.h
@@ -36,6 +36,7 @@
   virtual int inst_MOV(uint code, int operands);
   virtual int inst_ANL(uint code, int operands);
   virtual int inst_ORL(uint code, int operands);
+  virtual int inst_BEQ(uint code, int operands);
   virtual int inst_BR(uint code, int operands);
   virtual int inst_JMP(uint code, int operands);
   virtual int inst_CALL(uint code, int operands);

diff --git a/sim/ucsim/xa.src/xa.cc b/sim/ucsim/xa.src/xa.cc
index b672ce8d501137f83be9d53b1d9397dd8bc60ac7..578f0d2cdaeffd7ee7c58164a0b810ce2c534100 100644 (file)
--- a/sim/ucsim/xa.src/xa.cc
+++ b/sim/ucsim/xa.src/xa.cc
@@ -334,7 +334,7 @@ cl_xa::disass(t_addr addr, char *sep)
       ++immed_offset;
     break;
     case REG_DATA16 :
-      sprintf(parm_str, "%s,#%04x",
+      sprintf(parm_str, "%s,#0x%04x",
               reg_strs[((code >> 4) & 0xf)],
               (short)((get_mem(MEM_ROM, addr+immed_offset+1)) |
                      (get_mem(MEM_ROM, addr+immed_offset)<<8)) );
@@ -669,6 +669,8 @@ cl_xa::exec_inst(void)
     return inst_ANL(code, operands);
     case ORL:
     return inst_ORL(code, operands);
+    case BEQ:
+    return inst_BEQ(code, operands);
     case BR:
     return inst_BR(code, operands);
     case JMP: