*** empty log message ***

git-svn-id: https://sdcc.svn.sourceforge.net/svnroot/sdcc/trunk/sdcc@1898 4a8a32a2-be11-0410-ad9d-d568d2c75423

diff --git a/sim/ucsim/xa.src/glob.cc b/sim/ucsim/xa.src/glob.cc
index 20b8a70b1ac65d7bc74c8555dfb454ba655afba6..21e0a775b8d5b8d634f482b564a62611126ee2e2 100644 (file)
--- a/sim/ucsim/xa.src/glob.cc
+++ b/sim/ucsim/xa.src/glob.cc
@@ -6,7 +6,7 @@
  * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
  * Other contributors include:
  *   Karl Bongers karl@turbobit.com,
- *   Johan Knol 
+ *   Johan Knol johan.knol@iduna.nl
  */
 
 /* This file is part of microcontroller simulator: ucsim.
@@ -202,12 +202,14 @@ struct xa_dis_entry disass_xa[]= {
  {0,0x9605,0xff8f,' ',4, AND,DIRECT_DATA8    },  // AND direct, #data8         1 0 0 1 0 1 1 0  0 b b b 0 1 0 1 
  {0,0x9e05,0xff8f,' ',5, AND,DIRECT_DATA16   },  // AND direct, #data16        1 0 0 1 0 1 1 0  1 b b b 0 1 0 1 
 
- {0,0x0840,0xfffc,' ',3,ANL, C_BIT           }, //  ANL C, bit                 0 0 0 0 1 0 0 0  0 1 0 0 0 0 b b
- {0,0x0850,0xfffc,' ',3,ANL, C_NOTBIT        }, //  ANL C, /bit                0 0 0 0 1 0 0 0  0 1 0 1 0 0 b b
- {0,0xc150,0xf300,' ',3,ASL, REG_REG         }, //  ASL Rd, Rs                 1 1 0 0 S S 0 1  d d d d s s s s
- /* 2 more ASL cases */
- {0,0xc250,0xf300,' ',3,ASR, REG_REG         }, //  ASR Rd, Rs                 1 1 0 0 S S 1 0  d d d d s s s s
- /* 2 more ASR cases */
+ {0,0x0840,0xfffc,' ',2,ANL, C_BIT           }, //  ANL C, bit                 0 0 0 0 1 0 0 0  0 1 0 0 0 0 b b
+ {0,0x0850,0xfffc,' ',2,ANL, C_NOTBIT        }, //  ANL C, /bit                0 0 0 0 1 0 0 0  0 1 0 1 0 0 b b
+ {0,0xc150,0xf300,' ',2,ASL, REG_REG         }, //  ASL Rd, Rs                 1 1 0 0 S S 0 1  d d d d s s s s
+ {0,0xdd00,0xff00,' ',2,ASL, REG_DATA5       }, //  ASL Rd, #data5 (dword)     1 1 0 1 1 1 0 1  d d d #data5
+ {0,0xd100,0xf300,' ',2,ASL, REG_DATA4       }, //  ASL Rd, #data4             1 1 0 1 S S 0 1  d d d d #data4
+ {0,0xc250,0xf300,' ',2,ASR, REG_REG         }, //  ASR Rd, Rs                 1 1 0 0 S S 1 0  d d d d s s s s
+ {0,0xde00,0xff00,' ',2,ASR, REG_DATA5       }, //  ASR Rd, #data5 (dword)     1 1 0 1 1 1 1 0  d d d #data5
+ {0,0xd200,0xf300,' ',2,ASR, REG_DATA4       }, //  ASR Rd, #data4             1 1 0 1 S S 1 0  d d d d #data4
  {1,0xf000,0xff00,' ',2,BCC, REL8            }, //  BCC rel8                   1 1 1 1 0 0 0 0  rel8
  {1,0xf100,0xff00,' ',2,BCS, REL8            }, //  BCS rel8                   1 1 1 1 0 0 0 1  rel8
  {1,0xf300,0xff00,' ',2,BEQ, REL8            }, //  BEQ rel8                   1 1 1 1 0 0 1 1  rel8
@@ -281,11 +283,12 @@ struct xa_dis_entry disass_xa[]= {
 
  {0,0x9780,0xfffc,' ',4, JB,    BIT_REL8     }, //  JB bit,rel8                1 0 0 1 0 1 1 1  1 0 0 0 0 0 b b
  {0,0x97c0,0xfffc,' ',4, JBC,   BIT_REL8     }, //  JBC bit,rel8               1 0 0 1 0 1 1 1  1 1 0 0 0 0 b b
- {1,0xd500,0xff00,' ',3, JMP,   REL16        }, //  JMP rel16                  1 1 0 1 0 1 0 1
+ {1,0xd500,0xff00,' ',3, JMP,   REL16        }, //  JMP rel16                  1 1 0 1 0 1 0 1  rel16
  {0,0xd670,0xfff8,' ',2, JMP,   IREG         }, //  JMP [Rs]                   1 1 0 1 0 1 1 0  0 1 1 1 0 s s s
  /* JMP(2) */
  {0,0x97a0,0xfffc,' ',4, JNB,   BIT_REL8     }, //  JNB bit,rel8               1 0 0 1 0 1 1 1  1 0 1 0 0 0 b b
- /* JNZ, JZ */
+ {1,0xee00,0xff00,' ',2, JNZ,   REL8         }, //  JNZ rel8                   1 1 1 0 1 1 1 0  rel8
+ {1,0xec00,0xff00,' ',2, JZ,    REL8         }, //  JZ rel8                    1 1 1 0 1 1 0 0  rel8
  {0,0x4000,0xff88,' ',3, LEA,   REG_REGOFF8  }, //  LEA Rd,Rs+offset8          0 1 0 0 0 0 0 0  0 d d d 0 s s s
  {0,0x4800,0xff88,' ',3, LEA,   REG_REGOFF16 }, //  LEA Rd,Rs+offset16         0 1 0 0 0 0 0 0  0 d d d 0 s s s
  /* LSR(3?)  */
@@ -317,10 +320,11 @@ struct xa_dis_entry disass_xa[]= {
  {0,0x8000,0xf308,' ',2,MOVC, REG_IREGINC    },  // MOVC Rd,[Rs+]              1 0 0 0 S 0 0 0  d d d d 0 s s s
  {0,0x904e,0xffff,' ',2,MOVC, A_APLUSDPTR    },  // MOVC A,[A+DPTR]            1 0 0 1 0 0 0 0  0 1 0 0 1 1 1 0
  {0,0x904c,0xffff,' ',2,MOVC, A_APLUSPC      },  // MOVC A,[A+PC]              1 0 0 1 0 0 0 0  0 1 0 0 1 1 0 0
-   /* MOVS(6), MOVX(2), MUL.x(6), NEG */
+   /* MOVS(6), MOVX(2), MUL.x(6) */
 
+ {0,0x900b,0xf70f,' ',2,NEG, REG             }, //  NEG Rd                     1 0 0 1 S 0 0 0  d d d d 1 0 1 1
  {1,0x0000,0xff00,' ',1,NOP, NO_OPERANDS     }, //  NOP                        0 0 0 0 0 0 0 0
-   /* NORM */
+ {0,0xc300,0xff00,' ',2,NORM, REG_REG        }, //  NORM Rd,Rs                 1 1 0 0 S S 1 1  d d d d s s s s
  {0,0x6100,0xf700,' ',2, OR, REG_REG         },  //  OR Rd, Rs                 0 1 1 0 S 0 0 1  d d d d s s s s
  {0,0x6200,0xf708,' ',2, OR, REG_IREG        },  //  OR Rd, [Rs]               0 1 1 0 S 0 1 0  d d d d 0 s s s
  {0,0x6208,0xf708,' ',2, OR, IREG_REG        },  //  OR [Rd], Rs               0 1 1 0 S 0 1 0  s s s s 1 d d d
@@ -424,7 +428,7 @@ struct xa_dis_entry disass_xa[]= {
  {0,0x7600,0xf708,' ',3,XOR, REG_DIRECT      },  // XOR Rd, direct             0 1 1 1 S 1 1 0  d d d d 0 x x x
  {0,0x9107,0xff0f,' ',3,XOR, REG_DATA8       },  // XOR Rd, #data8             1 0 0 1 0 0 0 1  d d d d 0 1 1 1
  {0,0x9907,0xff0f,' ',4,XOR, REG_DATA16      },  // XOR Rd, #data16            1 0 0 1 1 0 0 1  d d d d 0 1 1 1
- {0,0x9207,0xff8f,' ',3,XOR, IREG_DATA8      },   // XOR [Rd], #data8           1 0 0 1 0 0 1 0  0 d d d 0 1 1 1
+ {0,0x9207,0xff8f,' ',3,XOR, IREG_DATA8      },  // XOR [Rd], #data8           1 0 0 1 0 0 1 0  0 d d d 0 1 1 1
  {0,0x9a07,0xff8f,' ',4,XOR, IREG_DATA16     },  // XOR [Rd], #data16          1 0 0 1 1 0 1 0  0 d d d 0 1 1 1
  {0,0x9307,0xff8f,' ',3,XOR, IREGINC_DATA8   },  // XOR [Rd+], #data8          1 0 0 1 0 0 1 1  0 d d d 0 1 1 1
  {0,0x9b07,0xff8f,' ',4,XOR, IREGINC_DATA16  },  // XOR [Rd+], #data16         1 0 0 1 1 0 1 1  0 d d d 0 1 1 1

diff --git a/sim/ucsim/xa.src/glob.h b/sim/ucsim/xa.src/glob.h
index 5e992ec87299b18fb6654075587eeecd24a8d41d..9d731fe77609c61e600984650520b8ca7740fa1f 100644 (file)
--- a/sim/ucsim/xa.src/glob.h
+++ b/sim/ucsim/xa.src/glob.h
@@ -6,7 +6,7 @@
  * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
  * Other contributors include:
  *   Karl Bongers karl@turbobit.com,
- *   Johan Knol 
+ *   Johan Knol johan.knol@iduna.nl
  *
  */
 
@@ -151,6 +151,7 @@ enum op_operands {
   C_NOTBIT,
   DATA4,
   REG_DATA4,
+  REG_DATA5,
   IREG_DATA4,
   IREGINC_DATA4,
   IREGOFF8_DATA4,

diff --git a/sim/ucsim/xa.src/inst.cc b/sim/ucsim/xa.src/inst.cc
index f694396d72c20062dc2f801a6a60ced3e40f37ee..dc991e08650e3b964301006d1e101183cbfbe31b 100644 (file)
--- a/sim/ucsim/xa.src/inst.cc
+++ b/sim/ucsim/xa.src/inst.cc
@@ -6,7 +6,7 @@
  * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
  * Other contributors include:
  *   Karl Bongers karl@turbobit.com,
- *   Johan Knol 
+ *   Johan Knol johan.knol@iduna.nl
  *
  */
 
@@ -45,7 +45,7 @@ void cl_xa::store1(t_addr addr, unsigned char val)
   }
 }
 
-void cl_xa::store2(t_addr addr, unsigned char val)
+void cl_xa::store2(t_addr addr, unsigned short val)
 {
   if (addr < 0x2000) {
     set_idata2(addr, val);
@@ -689,8 +689,8 @@ int cl_xa::inst_POP(uint code, int operands)
     case RLIST:
     {
       unsigned char rlist = fetch();
-      if (code & 0x08) { // word op
-       if (code & 0x40) { // R8-R15
+      if (code & 0x0800) { // word op
+       if (code & 0x4000) { // R8-R15
          if (rlist&0x01) { set_reg2(8, get2(sp)); sp+=2; }
          if (rlist&0x02) { set_reg2(9, get2(sp)); sp+=2; }
          if (rlist&0x04) { set_reg2(10, get2(sp)); sp+=2; }
@@ -710,7 +710,7 @@ int cl_xa::inst_POP(uint code, int operands)
          if (rlist&0x80) { set_reg2(7, get2(sp)); sp+=2; }
        }
       } else { // byte op
-       if (code & 0x40) { // R4l-R7h
+       if (code & 0x4000) { // R4l-R7h
          if (rlist&0x01) { set_reg1(8, get1(sp)); sp+=2; }
          if (rlist&0x02) { set_reg1(9, get1(sp)); sp+=2; }
          if (rlist&0x04) { set_reg1(10, get1(sp)); sp+=2; }
@@ -758,8 +758,8 @@ int cl_xa::inst_PUSH(uint code, int operands)
     {
       unsigned short sp=get_sp();
       unsigned char rlist = fetch();
-      if (code & 0x08) { // word op
-       if (code & 0x40) { // R15-R8
+      if (code & 0x0800) { // word op
+       if (code & 0x4000) { // R15-R8
          if (rlist&0x80) { sp-=2; store2(sp, reg2(15)); }
          if (rlist&0x40) { sp-=2; store2(sp, reg2(14)); }
          if (rlist&0x20) { sp-=2; store2(sp, reg2(13)); }
@@ -779,24 +779,24 @@ int cl_xa::inst_PUSH(uint code, int operands)
          if (rlist&0x01) { sp-=2; store2(sp, reg2(0)); }
        }
       } else { // byte op
-       if (code & 0x40) { // R7h-R4l
-         if (rlist&0x80) { sp-=2; store2(sp, reg2(15)); }
-         if (rlist&0x40) { sp-=2; store2(sp, reg2(14)); }
-         if (rlist&0x20) { sp-=2; store2(sp, reg2(13)); }
-         if (rlist&0x10) { sp-=2; store2(sp, reg2(12)); }
-         if (rlist&0x08) { sp-=2; store2(sp, reg2(11)); }
-         if (rlist&0x04) { sp-=2; store2(sp, reg2(10)); }
-         if (rlist&0x02) { sp-=2; store2(sp, reg2(9)); }
-         if (rlist&0x01) { sp-=2; store2(sp, reg2(8)); }
+       if (code & 0x4000) { // R7h-R4l
+         if (rlist&0x80) { sp-=2; store2(sp, reg1(15)); }
+         if (rlist&0x40) { sp-=2; store2(sp, reg1(14)); }
+         if (rlist&0x20) { sp-=2; store2(sp, reg1(13)); }
+         if (rlist&0x10) { sp-=2; store2(sp, reg1(12)); }
+         if (rlist&0x08) { sp-=2; store2(sp, reg1(11)); }
+         if (rlist&0x04) { sp-=2; store2(sp, reg1(10)); }
+         if (rlist&0x02) { sp-=2; store2(sp, reg1(9)); }
+         if (rlist&0x01) { sp-=2; store2(sp, reg1(8)); }
        } else { // R3h-R0l
-         if (rlist&0x80) { sp-=2; store2(sp, reg2(7)); }
-         if (rlist&0x40) { sp-=2; store2(sp, reg2(6)); }
-         if (rlist&0x20) { sp-=2; store2(sp, reg2(5)); }
-         if (rlist&0x10) { sp-=2; store2(sp, reg2(4)); }
-         if (rlist&0x08) { sp-=2; store2(sp, reg2(3)); }
-         if (rlist&0x04) { sp-=2; store2(sp, reg2(2)); }
-         if (rlist&0x02) { sp-=2; store2(sp, reg2(1)); }
-         if (rlist&0x01) { sp-=2; store2(sp, reg2(0)); }
+         if (rlist&0x80) { sp-=2; store2(sp, reg1(7)); }
+         if (rlist&0x40) { sp-=2; store2(sp, reg1(6)); }
+         if (rlist&0x20) { sp-=2; store2(sp, reg1(5)); }
+         if (rlist&0x10) { sp-=2; store2(sp, reg1(4)); }
+         if (rlist&0x08) { sp-=2; store2(sp, reg1(3)); }
+         if (rlist&0x04) { sp-=2; store2(sp, reg1(2)); }
+         if (rlist&0x02) { sp-=2; store2(sp, reg1(1)); }
+         if (rlist&0x01) { sp-=2; store2(sp, reg1(0)); }
        }
       }
       set_sp(sp);
@@ -897,10 +897,26 @@ int cl_xa::inst_SUBB(uint code, int operands)
 #include "inst_gen.cc"
   return(resGO);
 }
+
 int cl_xa::inst_TRAP(uint code, int operands)
 {
+  // steal a few opcodes for simulator only putchar() and exit()
+  // functions.  Used in SDCC regression testing.
+  switch (code & 0x0f) {
+    case 0xe:
+      // implement a simulator putchar() routine
+      //printf("PUTCHAR-----> %xH\n", reg1(0));
+      putchar(reg1(0));
+      fflush(stdout);
+    break;
+
+    case 0xf:
+      ::exit(0);
+    break;
+  }
   return(resGO);
 }
+
 int cl_xa::inst_XCH(uint code, int operands)
 {
   return(resGO);

diff --git a/sim/ucsim/xa.src/inst_gen.cc b/sim/ucsim/xa.src/inst_gen.cc
index 3deab22bc0bbbb254848b6424053b6a68cc3ab1b..1165e4a5d3512aa3525319dfe04c2e8ebf67dbb4 100644 (file)
--- a/sim/ucsim/xa.src/inst_gen.cc
+++ b/sim/ucsim/xa.src/inst_gen.cc
@@ -89,19 +89,19 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA
     case IREGOFF16_REG :
     {
       int offset;
-      if (operands == REG_IREGOFF8) {
+      if (operands == IREGOFF8_REG) {
         offset = (int)((char) fetch());
       } else {
         offset = (int)((short)fetch2());
       }
       if (code & 0x0800) {  /* word op */
-        t_mem addr = reg2(RI_70) + offset;
+        t_mem addr = reg2(RI_07) + offset;
         unsigned short wtmp, wtotal;
         wtmp = get2(addr);
         wtotal = FUNC2( wtmp, reg2(RI_F0) );
         store2(addr, wtotal);
       } else {
-        t_mem addr = reg2(RI_70) + ((short) fetch2());
+        t_mem addr = reg2(RI_07) + ((short) fetch2());
         unsigned char total;
         total = FUNC1( get1(addr), reg1(RI_F0) );
         store1(addr, total);

diff --git a/sim/ucsim/xa.src/xa.cc b/sim/ucsim/xa.src/xa.cc
index 93b33cce74d5d80ed1ca19b2950538056614e290..26dceffaeaed2dceaff50e1ca25d594d59b2fb6f 100644 (file)
--- a/sim/ucsim/xa.src/xa.cc
+++ b/sim/ucsim/xa.src/xa.cc
@@ -478,6 +478,9 @@ cl_xa::disass(t_addr addr, char *sep)
     case REG_DATA4 :
       strcpy(parm_str, "REG_DATA4");
     break;
+    case REG_DATA5 :
+      strcpy(parm_str, "REG_DATA5");
+    break;
     case IREG_DATA4 :
       strcpy(parm_str, "IREG_DATA4");
     break;

diff --git a/sim/ucsim/xa.src/xacl.h b/sim/ucsim/xa.src/xacl.h
index 04d2120fc9445aaa70120cc6c23ffe6fdc8c7d68..6c6780d1990059e9f3c92b4b21e9db802271d553 100644 (file)
--- a/sim/ucsim/xa.src/xacl.h
+++ b/sim/ucsim/xa.src/xacl.h
@@ -3,9 +3,10 @@
  *
  * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
  *
- * Written by Karl Bongers karl@turbobit.com
- * 
  * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ * Other contributors include:
+ *   Karl Bongers karl@turbobit.com,
+ *   Johan Knol johan.knol@iduna.nl
  *
  */
 
@@ -87,7 +88,7 @@ public:
   virtual int get_reg(int word_flag, unsigned int index);
 
   virtual void store1(t_addr addr, unsigned char val);
-  virtual void store2(t_addr addr, unsigned char val);
+  virtual void store2(t_addr addr, unsigned short val);
   virtual unsigned char get1(t_addr addr);
   virtual unsigned short get2(t_addr addr);