* support/regression/tests/bug-477927.c: Added.

	* src/z80/peeph.def: Added minor rules.

	* src/z80/gen.c (genPlusIncr): Added an extra plusinc rule.

	* src/z80/peeph.def: Added jump optimisation modification.

git-svn-id: https://sdcc.svn.sourceforge.net/svnroot/sdcc/trunk/sdcc@1494 4a8a32a2-be11-0410-ad9d-d568d2c75423

diff --git a/ChangeLog b/ChangeLog
index 24dbd279a9639ed81f8c76be2a7aacce8487a288..6f3c08bb367df818c2cdd2e19acead0892c398ad 100644 (file)
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,3 +1,25 @@
+2001-11-03  Michael Hope  <michaelh@juju.net.nz>
+
+       * support/regression/tests/bug-477927.c: Added.
+
+       * src/z80/peeph.def: Added minor rules.
+
+       * src/z80/gen.c (genPlusIncr): Added an extra plusinc rule.
+
+       * src/z80/peeph.def: Added jump optimisation modification.
+
+2001-11-01  Michael Hope  <michaelh@juju.net.nz>
+
+       * src/SDCCmain.c (linkEdit): Added runtime path detection to the mcs51 port.
+
+2001-10-30  Michael Hope  <michaelh@juju.net.nz>
+
+       * support/regression/tests/funptrs.c: Added.
+
+2001-10-29  Michael Hope  <michaelh@juju.net.nz>
+
+       * src/z80/ralloc.c (packRegsForHLUse): Fixed up bad spill due to pushing one byte via HL.
+
 2001-10-28  Michael Hope  <michaelh@juju.net.nz>
 
        * src/z80/gen.c (genArrayInit): Made it work for on stack arrays.

diff --git a/src/z80/gen.c b/src/z80/gen.c
index d0c7f3a85d6eb1f03ff9115a396c52a6c586b704..6c5d5ae74ab3eecd5fd7db2e6b1e0692a6fced03 100644 (file)
--- a/src/z80/gen.c
+++ b/src/z80/gen.c
@@ -2887,6 +2887,18 @@ genPlusIncr (iCode * ic)
       AOP_SIZE (IC_LEFT (ic)) > 1)
     return FALSE;
 
+  /* If the result is in a register then we can load then increment.
+   */
+  if (AOP_TYPE (IC_RESULT (ic)) == AOP_REG)
+    {
+      aopPut (AOP (IC_RESULT (ic)), aopGet (AOP (IC_LEFT (ic)), LSB, FALSE), LSB);
+      while (icount--)
+        {
+          emit2 ("inc %s", aopGet (AOP (IC_RESULT (ic)), LSB, FALSE));
+        }
+      return TRUE;
+    }
+
   /* we can if the aops of the left & result match or
      if they are in registers and the registers are the
      same */
@@ -3995,7 +4007,7 @@ genCmpEq (iCode * ic, iCode * ifx)
   aopOp ((right = IC_RIGHT (ic)), ic, FALSE, FALSE);
   aopOp ((result = IC_RESULT (ic)), ic, TRUE, FALSE);
 
-  emitDebug ("; genCmpEq: left %u, right %u, result %u\n", AOP_SIZE(IC_LEFT(ic)), AOP_SIZE(IC_RIGHT(ic)), AOP_SIZE(IC_RESULT(ic)));
+  emitDebug ("; genCmpEq: left %u, right %u, result %u", AOP_SIZE(IC_LEFT(ic)), AOP_SIZE(IC_RIGHT(ic)), AOP_SIZE(IC_RESULT(ic)));
 
   /* Swap operands if it makes the operation easier. ie if:
      1.  Left is a literal.

diff --git a/src/z80/peeph-gbz80.def b/src/z80/peeph-gbz80.def
index 846e49c9a7b6e00c2393ee318fa64f73ac479ff3..01a465a23c2fb9fbcd21e3a31efbae4765136dc3 100644 (file)
--- a/src/z80/peeph-gbz80.def
+++ b/src/z80/peeph-gbz80.def
@@ -40,4 +40,33 @@ replace {
 } by {
        ld      [hl-],a
 }
-
+replace {
+       ld      (hl+),a
+       ld      (hl),d
+       dec     hl
+       ld      e,(hl)
+       inc     hl
+       ld      d,(hl)
+       ld      a,(de)
+} by {
+       ld      (hl+),a
+       ld      (hl),d
+       ld      e,a
+       ld      a,(de)
+}
+replace {
+       ld      (hl),a
+       ld      %1,(hl)
+} by {
+        ld      (hl),a
+        ld      %1,a
+}
+replace {
+       ld      (hl),%1
+       ld      a,%2
+       sub     a,(hl)
+} by {
+       ld      (hl),%1
+       ld      a,%2
+       sub     a,%1
+}

diff --git a/src/z80/peeph.def b/src/z80/peeph.def
index 5090d4b8f45c3d20fd4b3461426eab013995c83c..e29001de514754e985d6ad18aac44e2b04bb3b86 100644 (file)
--- a/src/z80/peeph.def
+++ b/src/z80/peeph.def
@@ -108,3 +108,14 @@ replace restart {
 } by {
         ld     %1,a
 }
+replace restart {
+       jp      %1,%2
+       jr      %3
+%2:
+       jp      %4
+} by {
+       jp      %1,%4
+       jr      %3
+%2:
+       jp      %4
+}

diff --git a/support/regression/tests/bug-477927.c b/support/regression/tests/bug-477927.c
new file mode 100644 (file)
index 0000000..b0ab6c3
--- /dev/null
+++ b/support/regression/tests/bug-477927.c
@@ -0,0 +1,48 @@
+/* Tests an uninitalised variable bug.
+   t is not initalised in all paths in the do loop, causing the while
+   conditional to fail unpredictably.
+
+   Doesn't actually test, is really an example.
+ */
+#include <testfwk.h>
+
+typedef unsigned char UBYTE;
+
+UBYTE
+randish(void)
+{
+  static int count;
+
+  if ((++count)&3) {
+    return 1;
+  }
+  else {
+    return 0;
+  }
+}
+
+void
+spoil(UBYTE ignored)
+{
+  UNUSED(ignored);
+}
+
+UBYTE accu[2];
+
+void 
+testLoopInit(void)
+{
+  UBYTE t, r;
+
+  do {
+    r = randish();
+
+    if(r != 1) {
+      t = ++accu[r];
+      spoil(t);
+    }
+  }
+  while(t != 3);
+}
+
+