work in progress

git-svn-id: https://sdcc.svn.sourceforge.net/svnroot/sdcc/trunk/sdcc@1895 4a8a32a2-be11-0410-ad9d-d568d2c75423

diff --git a/device/examples/xa51/hello.c b/device/examples/xa51/hello.c
index 49fa3328405ccfcdc4192d4c6adccceb4f2d17a0..ed9cabf76a5c38dee31573cf06b00c0415d8c839 100755 (executable)
--- a/device/examples/xa51/hello.c
+++ b/device/examples/xa51/hello.c
@@ -1,8 +1,8 @@
 #include <xa.h>
 
-bit b1, b2;
-data d1, d2;
-xdata x1, x2;
+bit b1, b2=1;
+data d1, d2=2;
+xdata x1, x2=3;
 
 #define        BAUD_RATE 9600
 #define        OSC 20000000L   /* Xtal frequency */

diff --git a/sim/ucsim/xa.src/inst.cc b/sim/ucsim/xa.src/inst.cc
index ec737aa83bd2d38e10cd059eed8574e881502c4f..f694396d72c20062dc2f801a6a60ced3e40f37ee 100644 (file)
--- a/sim/ucsim/xa.src/inst.cc
+++ b/sim/ucsim/xa.src/inst.cc
@@ -177,11 +177,19 @@ int cl_xa::inst_ASR(uint code, int operands)
 
 int cl_xa::inst_BCC(uint code, int operands)
 {
+  short jmpAddr = fetch1()*2;
+  if (!(get_psw() & BIT_C)) {
+    PC=(PC+jmpAddr)&0xfffffe;
+  }
   return(resGO);
 }
 
 int cl_xa::inst_BCS(uint code, int operands)
 {
+  short jmpAddr = fetch1()*2;
+  if (get_psw() & BIT_C) {
+    PC=(PC+jmpAddr)&0xfffffe;
+  }
   return(resGO);
 }
 
@@ -189,21 +197,39 @@ int cl_xa::inst_BEQ(uint code, int operands)
 {
   short jmpAddr = fetch1()*2;
   if (get_psw() & BIT_Z) {
-    PC=(PC+jmpAddr)&0xfffffffe;
+    PC=(PC+jmpAddr)&0xfffffe;
   }
   return(resGO);
 }
 
 int cl_xa::inst_BG(uint code, int operands)
 {
+  short jmpAddr = fetch1()*2;
+  short flags=get_psw();
+  bool Z=flags&BIT_Z, C=flags&BIT_C;
+  if (!(Z|C)) {
+    PC=(PC+jmpAddr)&0xfffffe;
+  }
   return(resGO);
 }
 int cl_xa::inst_BGE(uint code, int operands)
 {
+  short jmpAddr = fetch1()*2;
+  short flags=get_psw();
+  bool N=flags&BIT_N, V=flags&BIT_V;
+  if (!(N^V)) {
+    PC=(PC+jmpAddr)&0xfffffe;
+  }
   return(resGO);
 }
 int cl_xa::inst_BGT(uint code, int operands)
 {
+  short jmpAddr = fetch1()*2;
+  short flags=get_psw();
+  bool Z=flags&BIT_Z, N=flags&BIT_N, V=flags&BIT_V;
+  if (!((Z|N)^V)) {
+    PC=(PC+jmpAddr)&0xfffffe;
+  }
   return(resGO);
 }
 int cl_xa::inst_BKPT(uint code, int operands)
@@ -212,34 +238,72 @@ int cl_xa::inst_BKPT(uint code, int operands)
 }
 int cl_xa::inst_BL(uint code, int operands)
 {
+  short jmpAddr = fetch1()*2;
+  short flags=get_psw();
+  bool Z=flags&BIT_Z, C=flags&BIT_C;
+  if (Z|C) {
+    PC=(PC+jmpAddr)&0xfffffe;
+  }
   return(resGO);
 }
 int cl_xa::inst_BLE(uint code, int operands)
 {
+  short jmpAddr = fetch1()*2;
+  short flags=get_psw();
+  bool Z=flags&BIT_Z, N=flags&BIT_N, V=flags&BIT_V;
+  if ((Z|N)^V) {
+    PC=(PC+jmpAddr)&0xfffffe;
+  }
   return(resGO);
 }
 int cl_xa::inst_BLT(uint code, int operands)
 {
+  short jmpAddr = fetch1()*2;
+  short flags=get_psw();
+  bool N=flags&BIT_N, V=flags&BIT_V;
+  if (N^V) {
+    PC=(PC+jmpAddr)&0xfffffe;
+  }
   return(resGO);
 }
 int cl_xa::inst_BMI(uint code, int operands)
 {
+  short jmpAddr = fetch1()*2;
+  if (get_psw()&BIT_N) {
+    PC=(PC+jmpAddr)&0xfffffe;
+  }
   return(resGO);
 }
 int cl_xa::inst_BNE(uint code, int operands)
 {
+  short jmpAddr = fetch1()*2;
+  if (!(get_psw()&BIT_Z)) {
+    PC=(PC+jmpAddr)&0xfffffe;
+  }
   return(resGO);
 }
 int cl_xa::inst_BNV(uint code, int operands)
 {
+  short jmpAddr = fetch1()*2;
+  if (!(get_psw()&BIT_V)) {
+    PC=(PC+jmpAddr)&0xfffffe;
+  }
   return(resGO);
 }
 int cl_xa::inst_BOV(uint code, int operands)
 {
+  short jmpAddr = fetch1()*2;
+  if (get_psw()&BIT_V) {
+    PC=(PC+jmpAddr)&0xfffffe;
+  }
   return(resGO);
 }
 int cl_xa::inst_BPL(uint code, int operands)
 {
+  short jmpAddr = fetch1()*2;
+  if (!(get_psw()&BIT_N)) {
+    PC=(PC+jmpAddr)&0xfffffe;
+  }
   return(resGO);
 }
 
@@ -352,8 +416,7 @@ int cl_xa::inst_CJNE(uint code, int operands)
 int cl_xa::inst_CLR(uint code, int operands)
 {
   unsigned short bitAddr = (code&0x03 << 8) + fetch();
-  // fixme: implement
-  bitAddr=bitAddr;
+  set_bit (bitAddr, 0);
   return(resGO);
 }
 
@@ -608,13 +671,12 @@ int cl_xa::inst_ORL(uint code, int operands)
 
 int cl_xa::inst_POP(uint code, int operands)
 {
+  unsigned short sp=get_sp();
   switch(operands) {
     case DIRECT:
     {
-      unsigned short sp;
       unsigned short direct_addr = ((operands & 0x7) << 8) | fetch();
 
-      sp = get_sp();
       if (code & 0x0800) {  /* word op */
         set_word_direct(direct_addr, get2(sp) );
       } else {
@@ -625,9 +687,50 @@ int cl_xa::inst_POP(uint code, int operands)
     break;
 
     case RLIST:
-      // fixme: implement
+    {
       unsigned char rlist = fetch();
-      rlist = rlist; //shutup compiler
+      if (code & 0x08) { // word op
+       if (code & 0x40) { // R8-R15
+         if (rlist&0x01) { set_reg2(8, get2(sp)); sp+=2; }
+         if (rlist&0x02) { set_reg2(9, get2(sp)); sp+=2; }
+         if (rlist&0x04) { set_reg2(10, get2(sp)); sp+=2; }
+         if (rlist&0x08) { set_reg2(11, get2(sp)); sp+=2; }
+         if (rlist&0x10) { set_reg2(12, get2(sp)); sp+=2; }
+         if (rlist&0x20) { set_reg2(13, get2(sp)); sp+=2; }
+         if (rlist&0x40) { set_reg2(14, get2(sp)); sp+=2; }
+         if (rlist&0x80) { set_reg2(15, get2(sp)); sp+=2; }
+       } else { // R0-R7
+         if (rlist&0x01) { set_reg2(0, get2(sp)); sp+=2; }
+         if (rlist&0x02) { set_reg2(1, get2(sp)); sp+=2; }
+         if (rlist&0x04) { set_reg2(2, get2(sp)); sp+=2; }
+         if (rlist&0x08) { set_reg2(3, get2(sp)); sp+=2; }
+         if (rlist&0x10) { set_reg2(4, get2(sp)); sp+=2; }
+         if (rlist&0x20) { set_reg2(5, get2(sp)); sp+=2; }
+         if (rlist&0x40) { set_reg2(6, get2(sp)); sp+=2; }
+         if (rlist&0x80) { set_reg2(7, get2(sp)); sp+=2; }
+       }
+      } else { // byte op
+       if (code & 0x40) { // R4l-R7h
+         if (rlist&0x01) { set_reg1(8, get1(sp)); sp+=2; }
+         if (rlist&0x02) { set_reg1(9, get1(sp)); sp+=2; }
+         if (rlist&0x04) { set_reg1(10, get1(sp)); sp+=2; }
+         if (rlist&0x08) { set_reg1(11, get1(sp)); sp+=2; }
+         if (rlist&0x10) { set_reg1(12, get1(sp)); sp+=2; }
+         if (rlist&0x20) { set_reg1(13, get1(sp)); sp+=2; }
+         if (rlist&0x40) { set_reg1(14, get1(sp)); sp+=2; }
+         if (rlist&0x80) { set_reg1(15, get1(sp)); sp+=2; }
+       } else { // R0l-R3h
+         if (rlist&0x01) { set_reg1(0, get1(sp)); sp+=2; }
+         if (rlist&0x02) { set_reg1(1, get1(sp)); sp+=2; }
+         if (rlist&0x04) { set_reg1(2, get1(sp)); sp+=2; }
+         if (rlist&0x08) { set_reg1(3, get1(sp)); sp+=2; }
+         if (rlist&0x10) { set_reg1(4, get1(sp)); sp+=2; }
+         if (rlist&0x20) { set_reg1(5, get1(sp)); sp+=2; }
+         if (rlist&0x40) { set_reg1(6, get1(sp)); sp+=2; }
+         if (rlist&0x80) { set_reg1(7, get1(sp)); sp+=2; }
+       }
+      }
+    }
     break;
   }
   return(resGO);
@@ -652,12 +755,54 @@ int cl_xa::inst_PUSH(uint code, int operands)
     break;
 
     case RLIST:
-      // fixme: implement
+    {
+      unsigned short sp=get_sp();
       unsigned char rlist = fetch();
-      rlist = rlist; //shutup compiler
+      if (code & 0x08) { // word op
+       if (code & 0x40) { // R15-R8
+         if (rlist&0x80) { sp-=2; store2(sp, reg2(15)); }
+         if (rlist&0x40) { sp-=2; store2(sp, reg2(14)); }
+         if (rlist&0x20) { sp-=2; store2(sp, reg2(13)); }
+         if (rlist&0x10) { sp-=2; store2(sp, reg2(12)); }
+         if (rlist&0x08) { sp-=2; store2(sp, reg2(11)); }
+         if (rlist&0x04) { sp-=2; store2(sp, reg2(10)); }
+         if (rlist&0x02) { sp-=2; store2(sp, reg2(9)); }
+         if (rlist&0x01) { sp-=2; store2(sp, reg2(8)); }
+       } else { // R7-R0
+         if (rlist&0x80) { sp-=2; store2(sp, reg2(7)); }
+         if (rlist&0x40) { sp-=2; store2(sp, reg2(6)); }
+         if (rlist&0x20) { sp-=2; store2(sp, reg2(5)); }
+         if (rlist&0x10) { sp-=2; store2(sp, reg2(4)); }
+         if (rlist&0x08) { sp-=2; store2(sp, reg2(3)); }
+         if (rlist&0x04) { sp-=2; store2(sp, reg2(2)); }
+         if (rlist&0x02) { sp-=2; store2(sp, reg2(1)); }
+         if (rlist&0x01) { sp-=2; store2(sp, reg2(0)); }
+       }
+      } else { // byte op
+       if (code & 0x40) { // R7h-R4l
+         if (rlist&0x80) { sp-=2; store2(sp, reg2(15)); }
+         if (rlist&0x40) { sp-=2; store2(sp, reg2(14)); }
+         if (rlist&0x20) { sp-=2; store2(sp, reg2(13)); }
+         if (rlist&0x10) { sp-=2; store2(sp, reg2(12)); }
+         if (rlist&0x08) { sp-=2; store2(sp, reg2(11)); }
+         if (rlist&0x04) { sp-=2; store2(sp, reg2(10)); }
+         if (rlist&0x02) { sp-=2; store2(sp, reg2(9)); }
+         if (rlist&0x01) { sp-=2; store2(sp, reg2(8)); }
+       } else { // R3h-R0l
+         if (rlist&0x80) { sp-=2; store2(sp, reg2(7)); }
+         if (rlist&0x40) { sp-=2; store2(sp, reg2(6)); }
+         if (rlist&0x20) { sp-=2; store2(sp, reg2(5)); }
+         if (rlist&0x10) { sp-=2; store2(sp, reg2(4)); }
+         if (rlist&0x08) { sp-=2; store2(sp, reg2(3)); }
+         if (rlist&0x04) { sp-=2; store2(sp, reg2(2)); }
+         if (rlist&0x02) { sp-=2; store2(sp, reg2(1)); }
+         if (rlist&0x01) { sp-=2; store2(sp, reg2(0)); }
+       }
+      }
+      set_sp(sp);
+    }
     break;
   }
-  
   return(resGO);
 }
 int cl_xa::inst_RESET(uint code, int operands)
@@ -718,13 +863,18 @@ int cl_xa::inst_RRC(uint code, int operands)
 int cl_xa::inst_SETB(uint code, int operands)
 {
   unsigned short bitAddr = (code&0x03 << 8) + fetch();
-  // fixme: implement
-  bitAddr=bitAddr;
+  set_bit (bitAddr, 1);
   return(resGO);
 }
 
 int cl_xa::inst_SEXT(uint code, int operands)
 {
+  bool neg=get_psw()&BIT_N;
+  if (code & 0x0800) { // word op
+    set_reg2(RI_F0, neg ? 0xffff : 0);
+  } else {
+    set_reg1(RI_F0, neg ? 0xff : 0);
+  }
   return(resGO);
 }
 

diff --git a/sim/ucsim/xa.src/inst_gen.cc b/sim/ucsim/xa.src/inst_gen.cc
index 50e3d647a9246945fcd582f67154804815bcca8d..3deab22bc0bbbb254848b6424053b6a68cc3ab1b 100644 (file)
--- a/sim/ucsim/xa.src/inst_gen.cc
+++ b/sim/ucsim/xa.src/inst_gen.cc
@@ -126,7 +126,6 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA
                       )
                 );
       } else {
-        int offset = (int)((short)fetch2());
         set_reg1( RI_F0,
                   FUNC1( reg1(RI_F0),
                         get1(reg2(RI_07)+offset)

diff --git a/sim/ucsim/xa.src/regsxa.h b/sim/ucsim/xa.src/regsxa.h
index c59247254edabeb1c980a8aee40f6848391c4dea..363d16db63fb50912c70d7bacac9c342af4e51d2 100644 (file)
--- a/sim/ucsim/xa.src/regsxa.h
+++ b/sim/ucsim/xa.src/regsxa.h
@@ -28,8 +28,7 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA
 02111-1307, USA. */
 /*@1@*/
 
-#define REGS_OFFSET 0
-//#define REGS_OFFSET 0x400
+#define REGS_OFFSET 0x800
 
 #ifndef REGSAVR_HEADER
 #define REGSAVR_HEADER
@@ -73,18 +72,6 @@ struct t_regs
 #define get_xdata1(addr) ram->get((t_addr) (addr))
 #define get_xdata2(addr) (ram->get((t_addr) (addr)) | (ram->get((t_addr) (addr+1)) << 8) )
 
-#if 0
-  moved to inst.cc as functions
-/* store to ram */
-#define store2(addr, val) { ram->set((t_addr) (addr), (val) & 0xff); \
-                            ram->set((t_addr) (addr+1), ((val) >> 8) & 0xff); }
-#define store1(addr, val) ram->set((t_addr) (addr), val)
-
-/* get from ram */
-#define get1(addr) ram->get((t_addr) (addr))
-#define get2(addr) (ram->get((t_addr) (addr)) | (ram->get((t_addr) (addr+1)) << 8) )
-#endif
-
 /* get from code */
 #define getcode1(addr) rom->get((t_addr) (addr))
 #define getcode2(addr) (rom->get((t_addr) (addr)) | (rom->get((t_addr) (addr+1)) << 8) )
@@ -94,8 +81,8 @@ struct t_regs
 #define fetch1() fetch()
 
 /* get a 1 or 2 byte register */
-#define reg2(_index) get_reg(1, (_index<<1)) /* function in inst.cc */
-#define reg1(_index) (unsigned char)get_reg(0, (_index))
+#define reg2(_index) get_reg(1, REGS_OFFSET + (_index<<1)) /* function in inst.cc */
+#define reg1(_index) (unsigned char)get_reg(0, REGS_OFFSET + (_index))
 
 #define set_reg1(_index, _value) { \
   set_byte_direct((REGS_OFFSET+(_index)), _value); \

diff --git a/sim/ucsim/xa.src/xa.cc b/sim/ucsim/xa.src/xa.cc
index cf2811b9ecce2a02c05c559e6bc508c2c6cad439..93b33cce74d5d80ed1ca19b2950538056614e290 100644 (file)
--- a/sim/ucsim/xa.src/xa.cc
+++ b/sim/ucsim/xa.src/xa.cc
@@ -6,7 +6,7 @@
  * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
  * Other contributors include:
  *   Karl Bongers karl@turbobit.com,
- *   Johan Knol 
+ *   Johan Knol johan.knol@iduna.nl
  */
 
 /* This file is part of microcontroller simulator: ucsim.
@@ -323,21 +323,21 @@ cl_xa::disass(t_addr addr, char *sep)
               reg_strs[((code >> 4) & 0xf)] );
     break;
     case REG_IREGOFF8 :
-      sprintf(parm_str, "%s,[%s+%02d]",
+      sprintf(parm_str, "%s,[%s+%02x]",
               reg_strs[((code >> 4) & 0xf)],
               w_reg_strs[(code & 0x7)],
               get_mem(MEM_ROM, addr+immed_offset));
       ++immed_offset;
     break;
     case IREGOFF8_REG :
-      sprintf(parm_str, "[%s+%02d],%s",
+      sprintf(parm_str, "[%s+%02x],%s",
               w_reg_strs[(code & 0x7)],
               get_mem(MEM_ROM, addr+immed_offset),
               reg_strs[((code >> 4) & 0xf)] );
       ++immed_offset;
     break;
     case REG_IREGOFF16 :
-      sprintf(parm_str, "%s,[%s+%04d]",
+      sprintf(parm_str, "%s,[%s+%04x]",
               reg_strs[((code >> 4) & 0xf)],
               w_reg_strs[(code & 0x7)],
               (short)((get_mem(MEM_ROM, addr+immed_offset+1)) |
@@ -346,7 +346,7 @@ cl_xa::disass(t_addr addr, char *sep)
       ++immed_offset;
     break;
     case IREGOFF16_REG :
-      sprintf(parm_str, "[%s+%04d],%s",
+      sprintf(parm_str, "[%s+%04x],%s",
               w_reg_strs[(code & 0x7)],
               (short)((get_mem(MEM_ROM, addr+immed_offset+1)) |
                      (get_mem(MEM_ROM, addr+immed_offset)<<8)),
@@ -421,14 +421,14 @@ cl_xa::disass(t_addr addr, char *sep)
       ++immed_offset;
     break;
     case IREGOFF8_DATA8 :
-      sprintf(parm_str, "[%s+%02d], 0x%02x",
+      sprintf(parm_str, "[%s+%02x], 0x%02x",
               w_reg_strs[((code >> 4) & 0x7)],
               get_mem(MEM_ROM, addr+immed_offset),
               get_mem(MEM_ROM, addr+immed_offset+1) );
       immed_offset += 2;
     break;
     case IREGOFF8_DATA16 :
-      sprintf(parm_str, "[%s+%02d], 0x%04x",
+      sprintf(parm_str, "[%s+%02x], 0x%04x",
               w_reg_strs[((code >> 4) & 0x7)],
               get_mem(MEM_ROM, addr+immed_offset),
               (short)((get_mem(MEM_ROM, addr+immed_offset+2)) |
@@ -436,7 +436,7 @@ cl_xa::disass(t_addr addr, char *sep)
       immed_offset += 3;
     break;
     case IREGOFF16_DATA8 :
-      sprintf(parm_str, "[%s+%04d], 0x%02x",
+      sprintf(parm_str, "[%s+%04x], 0x%02x",
               w_reg_strs[((code >> 4) & 0x7)],
               (short)((get_mem(MEM_ROM, addr+immed_offset+1)) |
                      (get_mem(MEM_ROM, addr+immed_offset+0)<<8)),
@@ -444,7 +444,7 @@ cl_xa::disass(t_addr addr, char *sep)
       immed_offset += 3;
     break;
     case IREGOFF16_DATA16 :
-      sprintf(parm_str, "[%s+%04d], 0x%04x",
+      sprintf(parm_str, "[%s+%04x], 0x%04x",
               w_reg_strs[((code >> 4) & 0x7)],
               (short)((get_mem(MEM_ROM, addr+immed_offset+1)) |
                      (get_mem(MEM_ROM, addr+immed_offset+0)<<8)),
@@ -542,8 +542,53 @@ cl_xa::disass(t_addr addr, char *sep)
              ((signed short)((get_mem(MEM_ROM, addr+1)<<8) + get_mem(MEM_ROM, addr+2))*2+addr+len)&0xfffe);
     break;
 
-    case RLIST :
-      strcpy(parm_str, "RLIST");
+    case RLIST : {
+      /* TODO: the list should be comma reperated
+        and maybe for POP the list should be reversed */
+      unsigned char rlist=code&0xff;
+      parm_str[0]='\0';
+      if (code&0x0800) { // word list
+       if (code&0x4000) { // R8-R15
+         if (rlist&0x80) strcat (parm_str, "R15 ");
+         if (rlist&0x40) strcat (parm_str, "R14");
+         if (rlist&0x20) strcat (parm_str, "R13 ");
+         if (rlist&0x10) strcat (parm_str, "R12 ");
+         if (rlist&0x08) strcat (parm_str, "R11 ");
+         if (rlist&0x04) strcat (parm_str, "R10 ");
+         if (rlist&0x02) strcat (parm_str, "R9 ");
+         if (rlist&0x01) strcat (parm_str, "R8 ");
+       } else { // R7-R0
+         if (rlist&0x80) strcat (parm_str, "R7 ");
+         if (rlist&0x40) strcat (parm_str, "R6 ");
+         if (rlist&0x20) strcat (parm_str, "R5 ");
+         if (rlist&0x10) strcat (parm_str, "R4 ");
+         if (rlist&0x08) strcat (parm_str, "R3 ");
+         if (rlist&0x04) strcat (parm_str, "R2 ");
+         if (rlist&0x02) strcat (parm_str, "R1 ");
+         if (rlist&0x01) strcat (parm_str, "R0 ");
+       }
+      } else { // byte list
+       if (code&0x4000) { //R7h-R4l
+         if (rlist&0x80) strcat (parm_str, "R7h ");
+         if (rlist&0x40) strcat (parm_str, "R7l ");
+         if (rlist&0x20) strcat (parm_str, "R6h ");
+         if (rlist&0x10) strcat (parm_str, "R6l ");
+         if (rlist&0x08) strcat (parm_str, "R5h ");
+         if (rlist&0x04) strcat (parm_str, "R5l ");
+         if (rlist&0x02) strcat (parm_str, "R4h ");
+         if (rlist&0x01) strcat (parm_str, "R4l ");
+       } else { // R3h-R0l
+         if (rlist&0x80) strcat (parm_str, "R3h ");
+         if (rlist&0x40) strcat (parm_str, "R3l ");
+         if (rlist&0x20) strcat (parm_str, "R2h ");
+         if (rlist&0x10) strcat (parm_str, "R2l ");
+         if (rlist&0x08) strcat (parm_str, "R1h ");
+         if (rlist&0x04) strcat (parm_str, "R1l ");
+         if (rlist&0x02) strcat (parm_str, "R0h ");
+         if (rlist&0x01) strcat (parm_str, "R0l ");
+       }
+      }
+    }
     break;
 
     case REG_DIRECT_REL8 :
@@ -607,6 +652,7 @@ cl_xa::disass(t_addr addr, char *sep)
     buf= (char *)malloc(6+strlen(p)+1);
   else
     buf= (char *)malloc((p-work)+strlen(sep)+strlen(p)+1);
+
   for (p= work, b= buf; *p != ' '; p++, b++)
     *b= *p;
   p++;
@@ -632,18 +678,18 @@ cl_xa::print_regs(class cl_console *con)
   unsigned char flags;
 
   flags = get_psw();
-  con->dd_printf("CA---VNZ  Flags: %02x ", flags);
+  con->dd_printf("CA---VNZ | ", flags);
   con->dd_printf("R0:%04x R1:%04x R2:%04x R3:%04x\n",
                  reg2(0), reg2(1), reg2(2), reg2(3));
 
-  con->dd_printf("%c%c---%c%c%c            ",
+  con->dd_printf("%c%c---%c%c%c | ",
          (flags & BIT_C)?'1':'0',
          (flags & BIT_AC)?'1':'0',
          (flags & BIT_V)?'1':'0',
          (flags & BIT_N)?'1':'0',
          (flags & BIT_Z)?'1':'0');
 
-  con->dd_printf("R4:%04x R5:%04x R6:%04x R7(SP):%04x ES:%04x  DS:%04x\n",
+  con->dd_printf("R4:%04x R5:%04x R6:%04x SP:%04x ES:%04x  DS:%04x\n",
                  reg2(4), reg2(5), reg2(6), reg2(7), 0, 0);
 
   print_disass(PC, con);

diff --git a/src/xa51/gen.c b/src/xa51/gen.c
index fb73945827d967c6150321e2e52ae9be4eaf746d..ec4e935630ec18396faf23eca82084672758172d 100755 (executable)
--- a/src/xa51/gen.c
+++ b/src/xa51/gen.c
@@ -143,9 +143,7 @@ static void emitcode (char *inst, char *fmt,...) {
 
 char *getStackOffset(int stack) {
   static char gsoBuf[1024];
-  sprintf (gsoBuf, "r7+(%d%+d%+d%+d)", stack,
-          FUNC_ISISR(currFunc->type) ? 
-            port->stack.isr_overhead : port->stack.call_overhead,
+  sprintf (gsoBuf, "r7+(%d%+d%+d)", stack,
           currFunc->stack, _G.nRegsSaved);
   return gsoBuf;
 }

diff --git a/src/xa51/main.c b/src/xa51/main.c
index 05ba1c833400461919d8e0f7c75d39947e0ace1a..6db62f3cebc4bc1f45d9fa124f0ec8ff1acc67f3 100755 (executable)
--- a/src/xa51/main.c
+++ b/src/xa51/main.c
@@ -257,8 +257,8 @@ PORT xa51_port =
   {
     -1, // stack grows down
     0, // bank overhead NUY
-    6, // isr overhead
-    4, // function call overhead
+    4, // isr overhead, page zero mode
+    2, // function call overhead, page zero mode
     0, // reentrant overhead NUY
     0 // banked overhead NUY
   },