SBIT(B_6, 0xF0, 6); // Register B bit 6.\r
SBIT(B_7, 0xF0, 7); // Register B bit 7.\r
\r
+// PSD registers definition - by Jan Waclawek - wek at efton dot sk - May 2007\r
+// all defines here are with PSD_ prefix to identify them as PSD-related\r
+//\r
+// Based on uPSD33xx datasheet (preliminary) - Jan 2005, Table 79 at pages 145/146\r
+// and subsequent text\r
+\r
+// requires to have PSD_CSIOP defined to the base address of the PSD IO area,\r
+// as defined in PSDSoftExpress or CUPS\r
+#ifndef PSD_CSIOP\r
+#error PSD_CSIOP has to be #define-d (before #include-ing this file) to the base address of the PSD registers area, according to csiop setting in CUPS/PSDSoftExpress\r
+#else\r
+ // -- Port A not available on 52-pin uPSD33xx devices\r
+SFRX(PSD_DATAIN_A, PSD_CSIOP+0x00); // MCU I/O Mode Port A Data In Register\r
+ // reads 0 if pin is log.0, 1 if pin is log. 1\r
+ // READ only\r
+SFRX(PSD_DATAOUT_A, PSD_CSIOP+0x04); // MCU I/O Mode Port A Data Out Register \r
+ // write 0 to set pin to log. 0, 1 to set pin to log. 1 \r
+ // read back written value\r
+ // reset default = 00\r
+SFRX(PSD_DIRECTION_A, PSD_CSIOP+0x06); // MCU I/O Mode Port A Direction Register \r
+ // write 1 to set pin as output, 0 to set pin as input\r
+ // read back written value\r
+ // reset default = 00\r
+SFRX(PSD_DRIVE_A, PSD_CSIOP+0x08); // Select Open Drain or High Slew Rate for port A\r
+ // PA0-PA3: write 0 to select standard push-pull CMOS output, 1 to select High Slew Rate push-pull CMOS output\r
+ // PA4-PA7: write 0 to select standard push-pull CMOS output, 1 to select Open Drain output\r
+ // reset default = 00\r
+SFRX(PSD_CONTROL_A, PSD_CSIOP+0x02); // Selects MCU I/O or Latched Address Out mode for port A\r
+ // write 0 to select standard I/O pin, 1 to drive demultiplexed address signal on pin\r
+ // read back written value\r
+ // reset default = 00\r
+SFRX(PSD_OUTENABLE_A, PSD_CSIOP+0x0C); // Read state of Output Enable Logic on each I/O port driver of Port A\r
+ // 1 - driver output is enabled, 0 - driver is off (high impedance) \r
+ // READ only\r
+\r
+ // -- for comment on individual registers, see above Port A\r
+SFRX(PSD_DATAIN_B, PSD_CSIOP+0x01); // MCU I/O Mode Port B Data In Register\r
+SFRX(PSD_DATAOUT_B, PSD_CSIOP+0x05); // MCU I/O Mode Port B Data Out Register \r
+SFRX(PSD_DIRECTION_B, PSD_CSIOP+0x07); // MCU I/O Mode Port B Direction Register \r
+SFRX(PSD_DRIVE_B, PSD_CSIOP+0x09); // Select Open Drain or High Slew Rate for port B\r
+ // PB0-PB3: standard/High Slew Rate, PB4-PB7: standard/Open Drain\r
+SFRX(PSD_CONTROL_B, PSD_CSIOP+0x03); // Selects MCU I/O or Latched Address Out mode for port B\r
+SFRX(PSD_OUTENABLE_B, PSD_CSIOP+0x0D); // Read state of Output Enable Logic on each I/O port driver of Port B\r
+\r
+ // -- for comment on individual registers, see above Port A\r
+ // only pins PC2, PC3, PC4, PC7 available; other bits in registers are undefined\r
+SFRX(PSD_DATAIN_C, PSD_CSIOP+0x10); // MCU I/O Mode Port C Data In Register\r
+SFRX(PSD_DATAOUT_C, PSD_CSIOP+0x12); // MCU I/O Mode Port C Data Out Register \r
+SFRX(PSD_DIRECTION_C, PSD_CSIOP+0x14); // MCU I/O Mode Port C Direction Register \r
+SFRX(PSD_DRIVE_C, PSD_CSIOP+0x16); // Select Open Drain for port C\r
+SFRX(PSD_OUTENABLE_C, PSD_CSIOP+0x1A); // Read state of Output Enable Logic on each I/O port driver of Port C\r
+\r
+ // -- for comment on individual registers, see above Port A\r
+ // only pins PD1, PD2 available (PD2 not available on 52-pin package); other bits in registers are undefined\r
+SFRX(PSD_DATAIN_D, PSD_CSIOP+0x11); // MCU I/O Mode Port D Data In Register\r
+SFRX(PSD_DATAOUT_D, PSD_CSIOP+0x13); // MCU I/O Mode Port D Data Out Register \r
+SFRX(PSD_DIRECTION_D, PSD_CSIOP+0x15); // MCU I/O Mode Port D Direction Register \r
+SFRX(PSD_DRIVE_D, PSD_CSIOP+0x17); // Select High Slew Rate for port D\r
+SFRX(PSD_OUTENABLE_D, PSD_CSIOP+0x1B); // Read state of Output Enable Logic on each I/O port driver of Port D\r
+\r
+SFRX(PSD_IMC_A, PSD_CSIOP+0x0A); // Read to obtain logic state of Input Macrocells connected to Port A\r
+ // READ only\r
+SFRX(PSD_IMC_B, PSD_CSIOP+0x0B); // Read to obtain logic state of Input Macrocells connected to Port B\r
+SFRX(PSD_IMC_C, PSD_CSIOP+0x18); // Read to obtain logic state of Input Macrocells connected to Port C\r
+ // only pins PC2, PC3, PC4, PC7 available; other bits in register are undefined\r
+SFRX(PSD_OMC_AB, PSD_CSIOP+0x20); // Read logic state of macrocells AB. Write to load macrocell AB flip-flops.\r
+SFRX(PSD_OMC_BC, PSD_CSIOP+0x21); // Read logic state of macrocells BC. Write to load macrocell BC flip-flops.\r
+SFRX(PSD_OMCMASK_AB, PSD_CSIOP+0x22); // Write to set mask for macrocell AB. \r
+ // 1 blocks READs/WRITEs of OMF, 0 will pass OMF value\r
+ // Read back written value.\r
+SFRX(PSD_OMCMASK_BC, PSD_CSIOP+0x23); // Write to set mask for macrocell BC.\r
+\r
+// -- all three Power Management Register are set to 00 after PowerUp, but unchanged during reset (/RST)\r
+SFRX(PSD_PMMR0, PSD_CSIOP+0xB0); // -- Power Management Register 0 - write/read\r
+// bit 0 unused and should be set to 0\r
+#define PSD_APD_ENA 0x02 // 0 - Automatic Power Down (APD) counter is disabled, 1 - APD enabled\r
+// bit 2 unused and should be set to 0\r
+#define PSD_TURBO_DISA 0x08 // 0 - PSD Turbo mode enabled, 1 - Turbo mode off, saving power\r
+#define PSD_BLOCK_CLKIN_PLD 0x10 // 0 - CLKIN to PLD not blocked, 1 - no CLKIN to PLD Input Bus, saving power\r
+#define PSD_BLOCK_CLKIN_OMC 0x20 // 0 - CLKIN to Output Macrocells not blocked, 1 - blocked, saving power\r
+// bits 6 and 7 unused and should be set to 0\r
+\r
+SFRX(PSD_PMMR2, PSD_CSIOP+0xB4); // -- Power Management Register 2 - write/read\r
+// bits 0 and 1 unused and should be set to 0\r
+#define PSD_BLOCK_WR_PLD 0x04 // 0 - /WR from 8032 to PLD Input Bus not blocked, 1 - blocked, saving power\r
+#define PSD_BLOCK_RD_PLD 0x08 // 0 - /RD from 8032 to PLD Input Bus not blocked, 1 - blocked, saving power\r
+#define PSD_BLOCK_PSEN_PLD 0x10 // 0 - /PSEN from 8032 to PLD Input Bus not blocked, 1 - blocked, saving power\r
+#define PSD_BLOCK_ALE_PLD 0x20 // 0 - ALE from 8032 to PLD Input Bus not blocked, 1 - blocked, saving power\r
+#define PSD_BLOCK_PC7_PDL 0x40 // 0 - input from Port C pin 7 to PLD Input Bus not blocked, 1 - blocked, saving power\r
+// bit 7 unused and should be set to 0\r
+\r
+SFRX(PSD_PMMR3, PSD_CSIOP+0xC7); // -- Power Management Register 3 - write/read\r
+// bit 0 unused and should be set to 0\r
+#define PSD_FORCE_PD 0x02 // 0 - APD counter, if enabled, will cause powerdown, 1 - powerdown will be entered immediately\r
+ // - once set, cleared only by reset condition\r
+// bit 2 not defined by datasheet\r
+// bits 3 to 7 unused and should be set to 0\r
+\r
+SFRX(PSD_MAINPROTECT, PSD_CSIOP+0xC0); // -- Main Flash Memory Protection Definition\r
+ // bit 0 to bit 7 - sector 0 to sector 7 protection status\r
+ // - 1 - flash sector write protected, 0 - not write protected\r
+ // READ only\r
+SFRX(PSD_ALTPROTECT, PSD_CSIOP+0xC2); // -- Secondary Flash Memory Protection Definition\r
+ // bit 0 to bit 3 - sector 0 to sector 3 protection status\r
+ // - 1 - flash sector write protected, 0 - not write protected\r
+ // bit 7 - Security Bit\r
+ // - 1 - device is secured against external reading and writing, 0 - not secured\r
+ // READ only\r
+\r
+SFRX(PSD_PAGE, PSD_CSIOP+0xE0); // -- Memory Page Register\r
+\r
+SFRX(PSD_VM, PSD_CSIOP+0xE2); // -- Memory Mapping Register\r
+ // Places PSD Module memories into 8032 Program Address Space \r
+ // and/or 8032 XDATA Address Space\r
+ // Default value of bits 0 to 4 is loaded from Non-Volatile \r
+ // setting as specified from PSDsoft Express upon any reset \r
+ // or power-up condition. The default value of these bits \r
+ // can be overridden by 8032 at run-time.\r
+#define PSD_VM_SRAM_CODE 0x01 // 0 - SRAM not accessible as CODE (/PSEN) memory, 1 - SRAM accessible as CODE memory\r
+#define PSD_VM_ALT_CODE 0x02 // 0 - secondary FLASH not accessible as CODE (/PSEN) memory, 1 - secondary FLASH accessible as CODE memory\r
+#define PSD_VM_MAIN_CODE 0x04 // 0 - primary FLASH not accessible as CODE (/PSEN) memory, 1 - primary FLASH accessible as CODE memory\r
+#define PSD_VM_ALT_XDATA 0x08 // 0 - secondary FLASH not accessible as XDATA (/RD/WR) memory, 1 - secondary FLASH accessible as XDATA memory\r
+#define PSD_VM_MAIN_XDATA 0x10 // 0 - primary FLASH not accessible as XDATA (/RD/WR) memory, 1 - primary FLASH accessible as XDATA memory\r
+// bits 5 and 6 unused\r
+#define PSD_VM_PIO_EN 0x80 // 0 - disable, 1- enable peripheral I/O mode on Port A\r
+\r
+// another terminology for FLASH - MAIN/ALTERNATIVE -> PRIMARY/SECONDARY\r
+#define PSD_VM_PRI_CODE PSD_VM_MAIN_CODE\r
+#define PSD_VM_SEC_CODE PSD_VM_ALT_CODE\r
+#define PSD_VM_PRI_XDATA PSD_VM_MAIN_XDATA\r
+#define PSD_VM_SEC_XDATA PSD_VM_ALT_XDATA\r
+\r
+#endif\r
+\r
#endif //REG_UPSD33XX_H\r
projects / fw / sdcc / commitdiff