2 * Simulator of microcontrollers (uc52.cc)
4 * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
6 * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
10 /* This file is part of microcontroller simulator: ucsim.
12 UCSIM is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
17 UCSIM is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with UCSIM; see the file COPYING. If not, write to the Free
24 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
39 * Making an 8052 CPU object
42 t_uc52::t_uc52(int Itype, int Itech, class cl_sim *asim):
43 t_uc51(Itype, Itech, asim)
45 /*it_sources->add(new cl_it_src(bmET2, T2CON, bmTF2, 0x002b, false,
47 /*exf2it= new cl_it_src(bmET2, T2CON, bmEXF2, 0x002b, false,
49 it_sources->add(exf2it);*/
54 t_uc52::mk_hw_elements(void)
58 t_uc51::mk_hw_elements();
59 hws->add(h= new cl_timer2(this, 2, "timer2", t2_default|t2_down));
65 t_uc52::get_mem_size(enum mem_class type)
69 case MEM_IRAM: return(0x100);
70 default: return(t_uc51::get_mem_size(type));
77 * Calculating address of indirectly addressed IRAM cell
79 * If CPU is 8051 and addr is over 127, it must be illegal! But in 52
85 t_uc52::get_indirect(uchar addr, int *res)
88 return(iram->get_cell(addr));
95 * Calling inherited method to simulate timer #0 and #1 and then
96 * simulating timer #2.
101 t_uc52::do_extra_hw(int cycles)
112 t_uc52::do_timer2(int cycles)
114 bool nocount= DD_FALSE;
115 uint t2con= get_mem(MEM_SFR, T2CON);
118 if (!(t2con & bmTR2))
122 if (t2con & (bmRCLK | bmTCLK))
123 return(do_t2_baud(cycles));
125 // Determining nr of input clocks
126 if (!(t2con & bmTR2))
127 nocount= DD_TRUE; // Timer OFF
131 // Counter mode, falling edge on P1.0 (T2)
132 if ((prev_p1 & bmT2) &&
133 !(sfr->read(P1) & bmT2))
141 if (t2con & bmCP_RL2)
142 do_t2_capture(&cycles, nocount);
144 do_t2_reload(&cycles, nocount);
152 * Baud rate generator mode of Timer #2
156 t_uc52::do_t2_baud(int cycles)
158 t_mem t2con= sfr->get(T2CON);
159 //uint p1= get_mem(MEM_SFR, P1);
161 // Baud Rate Generator
162 if ((prev_p1 & bmT2EX) &&
163 !(sfr->read(P1) & bmT2EX) &&
165 mem(MEM_SFR)->set_bit1(T2CON, bmEXF2);
168 if ((prev_p1 & bmT2) &&
169 !(sfr->read(P1) & bmT2))
179 if (!sfr->add(TL2, 1))
180 if (!sfr->add(TH2, 1))
182 sfr->set(TH2, sfr->get(RCAP2H));
183 sfr->set(TL2, sfr->get(RCAP2L));
193 * Capture function of Timer #2
197 t_uc52::do_t2_capture(int *cycles, bool nocount)
199 //uint p1= get_mem(MEM_SFR, P1);
200 t_mem t2con= sfr->get(T2CON);
207 if (!sfr->add(TL2, 1))
209 if (!sfr->add(TH2, 1))
210 mem(MEM_SFR)->set_bit1(T2CON, bmTF2);
214 if ((prev_p1 & bmT2EX) &&
215 !(sfr->read(P1) & bmT2EX) &&
218 sfr->set(RCAP2H, sfr->get(TH2));
219 sfr->set(RCAP2L, sfr->get(TL2));
220 mem(MEM_SFR)->set_bit1(T2CON, bmEXF2);
221 prev_p1&= ~bmT2EX; // Falling edge has been handled
227 * Auto Reload mode of Timer #2, counting UP
231 t_uc52::do_t2_reload(int *cycles, bool nocount)
242 if (!sfr->add(TL2, 1))
244 if (!sfr->add(TH2, 1))
246 sfr->set_bit1(T2CON, bmTF2);
252 if ((prev_p1 & bmT2EX) &&
253 !(sfr->read(P1) & bmT2EX) &&
254 (sfr->get(T2CON) & bmEXEN2))
257 sfr->set_bit1(T2CON, bmEXF2);
258 prev_p1&= ~bmT2EX; // Falling edge has been handled
263 sfr->set(TH2, sfr->get(RCAP2H));
264 sfr->set(TL2, sfr->get(RCAP2L));
274 t_uc52::serial_bit_cnt(int mode)
277 int *tr_src= 0, *rec_src= 0;
284 rec_src= &s_rec_tick;
288 divby = (get_mem(MEM_SFR, PCON)&bmSMOD)?16:32;
289 tr_src = (get_mem(MEM_SFR, T2CON)&bmTCLK)?(&s_tr_t2):(&s_tr_t1);
290 rec_src= (get_mem(MEM_SFR, T2CON)&bmTCLK)?(&s_rec_t2):(&s_rec_t1);
293 divby = (get_mem(MEM_SFR, PCON)&bmSMOD)?16:32;
295 rec_src= &s_rec_tick;
300 while (*tr_src >= divby)
308 while (*rec_src >= divby)
318 /* End of s51.src/uc52.cc */