2 // Register Declarations for Microchip 16F676 Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTC_ADDR 0x0007
35 #define PCLATH_ADDR 0x000A
36 #define INTCON_ADDR 0x000B
37 #define PIR1_ADDR 0x000C
38 #define TMR1L_ADDR 0x000E
39 #define TMR1H_ADDR 0x000F
40 #define T1CON_ADDR 0x0010
41 #define CMCON_ADDR 0x0019
42 #define ADRESH_ADDR 0x001E
43 #define ADCON0_ADDR 0x001F
44 #define OPTION_REG_ADDR 0x0081
45 #define TRISA_ADDR 0x0085
46 #define TRISC_ADDR 0x0087
47 #define PIE1_ADDR 0x008C
48 #define PCON_ADDR 0x008E
49 #define OSCCAL_ADDR 0x0090
50 #define ANSEL_ADDR 0x0091
51 #define WPU_ADDR 0x0095
52 #define WPUA_ADDR 0x0095
53 #define IOC_ADDR 0x0096
54 #define IOCA_ADDR 0x0096
55 #define VRCON_ADDR 0x0099
56 #define EEDATA_ADDR 0x009A
57 #define EEDAT_ADDR 0x009A
58 #define EEADR_ADDR 0x009B
59 #define EECON1_ADDR 0x009C
60 #define EECON2_ADDR 0x009D
61 #define ADRESL_ADDR 0x009E
62 #define ADCON1_ADDR 0x009F
65 // Memory organization.
71 // P16F676.INC Standard Header File, Version 1.00 Microchip Technology, Inc.
74 // This header file defines configurations, registers, and other useful bits of
75 // information for the PIC16F676 microcontroller. These names are taken to match
76 // the data sheets as closely as possible.
78 // Note that the processor must be selected before this file is
79 // included. The processor may be selected the following ways:
81 // 1. Command line switch:
82 // C:\ MPASM MYFILE.ASM /PIC16F676
83 // 2. LIST directive in the source file
85 // 3. Processor Type entry in the MPASM full-screen interface
87 //==========================================================================
91 //==========================================================================
92 //1.00 05/13/02 Original
94 //==========================================================================
98 //==========================================================================
101 // MESSG "Processor-header file mismatch. Verify selected processor."
104 //==========================================================================
106 // Register Definitions
108 //==========================================================================
113 //----- Register Files------------------------------------------------------
115 extern __sfr __at (INDF_ADDR) INDF;
116 extern __sfr __at (TMR0_ADDR) TMR0;
117 extern __sfr __at (PCL_ADDR) PCL;
118 extern __sfr __at (STATUS_ADDR) STATUS;
119 extern __sfr __at (FSR_ADDR) FSR;
120 extern __sfr __at (PORTA_ADDR) PORTA;
122 extern __sfr __at (PORTC_ADDR) PORTC;
124 extern __sfr __at (PCLATH_ADDR) PCLATH;
125 extern __sfr __at (INTCON_ADDR) INTCON;
126 extern __sfr __at (PIR1_ADDR) PIR1;
128 extern __sfr __at (TMR1L_ADDR) TMR1L;
129 extern __sfr __at (TMR1H_ADDR) TMR1H;
130 extern __sfr __at (T1CON_ADDR) T1CON;
132 extern __sfr __at (CMCON_ADDR) CMCON;
134 extern __sfr __at (ADRESH_ADDR) ADRESH;
135 extern __sfr __at (ADCON0_ADDR) ADCON0;
138 extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
140 extern __sfr __at (TRISA_ADDR) TRISA;
141 extern __sfr __at (TRISC_ADDR) TRISC;
143 extern __sfr __at (PIE1_ADDR) PIE1;
145 extern __sfr __at (PCON_ADDR) PCON;
147 extern __sfr __at (OSCCAL_ADDR) OSCCAL;
148 extern __sfr __at (ANSEL_ADDR) ANSEL;
150 extern __sfr __at (WPU_ADDR) WPU;
151 extern __sfr __at (WPUA_ADDR) WPUA;
152 extern __sfr __at (IOC_ADDR) IOC;
153 extern __sfr __at (IOCA_ADDR) IOCA;
155 extern __sfr __at (VRCON_ADDR) VRCON;
156 extern __sfr __at (EEDATA_ADDR) EEDATA;
157 extern __sfr __at (EEDAT_ADDR) EEDAT;
158 extern __sfr __at (EEADR_ADDR) EEADR;
159 extern __sfr __at (EECON1_ADDR) EECON1;
160 extern __sfr __at (EECON2_ADDR) EECON2;
161 extern __sfr __at (ADRESL_ADDR) ADRESL;
162 extern __sfr __at (ADCON1_ADDR) ADCON1;
165 //----- STATUS Bits --------------------------------------------------------
168 //----- INTCON Bits --------------------------------------------------------
171 //----- PIR1 Bits ----------------------------------------------------------
174 //----- T1CON Bits ---------------------------------------------------------
177 //----- COMCON Bits --------------------------------------------------------
180 //----- ADCON0 Bits --------------------------------------------------------
183 //----- OPTION Bits --------------------------------------------------------
186 //----- PIE1 Bits ----------------------------------------------------------
189 //----- PCON Bits ----------------------------------------------------------
192 //----- OSCCAL Bits --------------------------------------------------------
195 //----- ANSEL --------------------------------------------------------------
198 //----- VRCON Bits ---------------------------------------------------------
201 //----- EECON1 -------------------------------------------------------------
204 //----- ADCON1 -------------------------------------------------------------
207 //==========================================================================
211 //==========================================================================
214 // __BADRAM H'06', H'08'-H'09', H'0D', H'11'-H'18', H'1A'-H'1D', H'60'-H'7F'
215 // __BADRAM H'86', H'88'-H'89', H'8D', H'8F', H'92'-H'94', H'97'-H'98', H'E0'-H'FF'
217 //==========================================================================
219 // Configuration Bits
221 //==========================================================================
224 #define _CPD_OFF 0x3FFF
226 #define _CP_OFF 0x3FFF
227 #define _BODEN 0x3FFF
228 #define _BODEN_OFF 0x3FBF
229 #define _MCLRE_ON 0x3FFF
230 #define _MCLRE_OFF 0x3FDF
231 #define _PWRTE_OFF 0x3FFF
232 #define _PWRTE_ON 0x3FEF
233 #define _WDT_ON 0x3FFF
234 #define _WDT_OFF 0x3FF7
235 #define _LP_OSC 0x3FF8
236 #define _XT_OSC 0x3FF9
237 #define _HS_OSC 0x3FFA
238 #define _EC_OSC 0x3FFB
239 #define _INTRC_OSC_NOCLKOUT 0x3FFC
240 #define _INTRC_OSC_CLKOUT 0x3FFD
241 #define _EXTRC_OSC_NOCLKOUT 0x3FFE
242 #define _EXTRC_OSC_CLKOUT 0x3FFF
246 // ----- ADCON0 bits --------------------
249 unsigned char ADON:1;
251 unsigned char CHS0:1;
252 unsigned char CHS1:1;
253 unsigned char CHS2:1;
255 unsigned char VCFG:1;
256 unsigned char ADFM:1;
260 unsigned char NOT_DONE:1;
270 unsigned char GO_DONE:1;
279 extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits;
281 #define ADON ADCON0_bits.ADON
282 #define GO ADCON0_bits.GO
283 #define NOT_DONE ADCON0_bits.NOT_DONE
284 #define GO_DONE ADCON0_bits.GO_DONE
285 #define CHS0 ADCON0_bits.CHS0
286 #define CHS1 ADCON0_bits.CHS1
287 #define CHS2 ADCON0_bits.CHS2
288 #define VCFG ADCON0_bits.VCFG
289 #define ADFM ADCON0_bits.ADFM
291 // ----- ADCON1 bits --------------------
298 unsigned char ADCS0:1;
299 unsigned char ADCS1:1;
300 unsigned char ADCS2:1;
304 extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits;
306 #define ADCS0 ADCON1_bits.ADCS0
307 #define ADCS1 ADCON1_bits.ADCS1
308 #define ADCS2 ADCON1_bits.ADCS2
310 // ----- ANSEL bits --------------------
313 unsigned char ANS0:1;
314 unsigned char ANS1:1;
315 unsigned char ANS2:1;
316 unsigned char ANS3:1;
317 unsigned char ANS4:1;
318 unsigned char ANS5:1;
319 unsigned char ANS6:1;
320 unsigned char ANS7:1;
323 extern volatile __ANSEL_bits_t __at(ANSEL_ADDR) ANSEL_bits;
325 #define ANS0 ANSEL_bits.ANS0
326 #define ANS1 ANSEL_bits.ANS1
327 #define ANS2 ANSEL_bits.ANS2
328 #define ANS3 ANSEL_bits.ANS3
329 #define ANS4 ANSEL_bits.ANS4
330 #define ANS5 ANSEL_bits.ANS5
331 #define ANS6 ANSEL_bits.ANS6
332 #define ANS7 ANSEL_bits.ANS7
334 // ----- CMCON bits --------------------
341 unsigned char CINV:1;
343 unsigned char COUT:1;
347 extern volatile __CMCON_bits_t __at(CMCON_ADDR) CMCON_bits;
349 #define CM0 CMCON_bits.CM0
350 #define CM1 CMCON_bits.CM1
351 #define CM2 CMCON_bits.CM2
352 #define CIS CMCON_bits.CIS
353 #define CINV CMCON_bits.CINV
354 #define COUT CMCON_bits.COUT
356 // ----- EECON1 bits --------------------
361 unsigned char WREN:1;
362 unsigned char WRERR:1;
369 extern volatile __EECON1_bits_t __at(EECON1_ADDR) EECON1_bits;
371 #define RD EECON1_bits.RD
372 #define WR EECON1_bits.WR
373 #define WREN EECON1_bits.WREN
374 #define WRERR EECON1_bits.WRERR
376 // ----- INTCON bits --------------------
379 unsigned char RAIF:1;
380 unsigned char INTF:1;
381 unsigned char T0IF:1;
382 unsigned char RAIE:1;
383 unsigned char INTE:1;
384 unsigned char T0IE:1;
385 unsigned char PEIE:1;
389 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
391 #define RAIF INTCON_bits.RAIF
392 #define INTF INTCON_bits.INTF
393 #define T0IF INTCON_bits.T0IF
394 #define RAIE INTCON_bits.RAIE
395 #define INTE INTCON_bits.INTE
396 #define T0IE INTCON_bits.T0IE
397 #define PEIE INTCON_bits.PEIE
398 #define GIE INTCON_bits.GIE
400 // ----- OPTION_REG bits --------------------
407 unsigned char T0SE:1;
408 unsigned char T0CS:1;
409 unsigned char INTEDG:1;
410 unsigned char NOT_GPPU:1;
420 unsigned char NOT_RAPU:1;
422 } __OPTION_REG_bits_t;
423 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
425 #define PS0 OPTION_REG_bits.PS0
426 #define PS1 OPTION_REG_bits.PS1
427 #define PS2 OPTION_REG_bits.PS2
428 #define PSA OPTION_REG_bits.PSA
429 #define T0SE OPTION_REG_bits.T0SE
430 #define T0CS OPTION_REG_bits.T0CS
431 #define INTEDG OPTION_REG_bits.INTEDG
432 #define NOT_GPPU OPTION_REG_bits.NOT_GPPU
433 #define NOT_RAPU OPTION_REG_bits.NOT_RAPU
435 // ----- OSCCAL bits --------------------
440 unsigned char CAL0:1;
441 unsigned char CAL1:1;
442 unsigned char CAL2:1;
443 unsigned char CAL3:1;
444 unsigned char CAL4:1;
445 unsigned char CAL5:1;
448 extern volatile __OSCCAL_bits_t __at(OSCCAL_ADDR) OSCCAL_bits;
450 #define CAL0 OSCCAL_bits.CAL0
451 #define CAL1 OSCCAL_bits.CAL1
452 #define CAL2 OSCCAL_bits.CAL2
453 #define CAL3 OSCCAL_bits.CAL3
454 #define CAL4 OSCCAL_bits.CAL4
455 #define CAL5 OSCCAL_bits.CAL5
457 // ----- PCON bits --------------------
460 unsigned char NOT_BOD:1;
461 unsigned char NOT_POR:1;
470 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
472 #define NOT_BOD PCON_bits.NOT_BOD
473 #define NOT_POR PCON_bits.NOT_POR
475 // ----- PIE1 bits --------------------
478 unsigned char T1IE:1;
481 unsigned char CMIE:1;
484 unsigned char ADIE:1;
485 unsigned char EEIE:1;
488 unsigned char TMR1IE:1;
498 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
500 #define T1IE PIE1_bits.T1IE
501 #define TMR1IE PIE1_bits.TMR1IE
502 #define CMIE PIE1_bits.CMIE
503 #define ADIE PIE1_bits.ADIE
504 #define EEIE PIE1_bits.EEIE
506 // ----- PIR1 bits --------------------
509 unsigned char T1IF:1;
512 unsigned char CMIF:1;
515 unsigned char ADIF:1;
516 unsigned char EEIF:1;
519 unsigned char TMR1IF:1;
529 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
531 #define T1IF PIR1_bits.T1IF
532 #define TMR1IF PIR1_bits.TMR1IF
533 #define CMIF PIR1_bits.CMIF
534 #define ADIF PIR1_bits.ADIF
535 #define EEIF PIR1_bits.EEIF
537 // ----- PORTA bits --------------------
550 extern volatile __PORTA_bits_t __at(PORTA_ADDR) PORTA_bits;
552 #define RA0 PORTA_bits.RA0
553 #define RA1 PORTA_bits.RA1
554 #define RA2 PORTA_bits.RA2
555 #define RA3 PORTA_bits.RA3
556 #define RA4 PORTA_bits.RA4
557 #define RA5 PORTA_bits.RA5
559 // ----- PORTC bits --------------------
572 extern volatile __PORTC_bits_t __at(PORTC_ADDR) PORTC_bits;
574 #define RC0 PORTC_bits.RC0
575 #define RC1 PORTC_bits.RC1
576 #define RC2 PORTC_bits.RC2
577 #define RC3 PORTC_bits.RC3
578 #define RC4 PORTC_bits.RC4
579 #define RC5 PORTC_bits.RC5
580 #define RC6 PORTC_bits.RC6
581 #define RC7 PORTC_bits.RC7
583 // ----- STATUS bits --------------------
589 unsigned char NOT_PD:1;
590 unsigned char NOT_TO:1;
596 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
598 #define C STATUS_bits.C
599 #define DC STATUS_bits.DC
600 #define Z STATUS_bits.Z
601 #define NOT_PD STATUS_bits.NOT_PD
602 #define NOT_TO STATUS_bits.NOT_TO
603 #define RP0 STATUS_bits.RP0
604 #define RP1 STATUS_bits.RP1
605 #define IRP STATUS_bits.IRP
607 // ----- T1CON bits --------------------
610 unsigned char TMR1ON:1;
611 unsigned char TMR1CS:1;
612 unsigned char NOT_T1SYNC:1;
613 unsigned char T1OSCEN:1;
614 unsigned char T1CKPS0:1;
615 unsigned char T1CKPS1:1;
616 unsigned char TMR1GE:1;
620 extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
622 #define TMR1ON T1CON_bits.TMR1ON
623 #define TMR1CS T1CON_bits.TMR1CS
624 #define NOT_T1SYNC T1CON_bits.NOT_T1SYNC
625 #define T1OSCEN T1CON_bits.T1OSCEN
626 #define T1CKPS0 T1CON_bits.T1CKPS0
627 #define T1CKPS1 T1CON_bits.T1CKPS1
628 #define TMR1GE T1CON_bits.TMR1GE
630 // ----- TRISA bits --------------------
633 unsigned char TRISA0:1;
634 unsigned char TRISA1:1;
635 unsigned char TRISA2:1;
636 unsigned char TRISA3:1;
637 unsigned char TRISA4:1;
638 unsigned char TRISA5:1;
643 extern volatile __TRISA_bits_t __at(TRISA_ADDR) TRISA_bits;
645 #define TRISA0 TRISA_bits.TRISA0
646 #define TRISA1 TRISA_bits.TRISA1
647 #define TRISA2 TRISA_bits.TRISA2
648 #define TRISA3 TRISA_bits.TRISA3
649 #define TRISA4 TRISA_bits.TRISA4
650 #define TRISA5 TRISA_bits.TRISA5
652 // ----- TRISC bits --------------------
655 unsigned char TRISC0:1;
656 unsigned char TRISC1:1;
657 unsigned char TRISC2:1;
658 unsigned char TRISC3:1;
659 unsigned char TRISC4:1;
660 unsigned char TRISC5:1;
661 unsigned char TRISC6:1;
662 unsigned char TRISC7:1;
665 extern volatile __TRISC_bits_t __at(TRISC_ADDR) TRISC_bits;
667 #define TRISC0 TRISC_bits.TRISC0
668 #define TRISC1 TRISC_bits.TRISC1
669 #define TRISC2 TRISC_bits.TRISC2
670 #define TRISC3 TRISC_bits.TRISC3
671 #define TRISC4 TRISC_bits.TRISC4
672 #define TRISC5 TRISC_bits.TRISC5
673 #define TRISC6 TRISC_bits.TRISC6
674 #define TRISC7 TRISC_bits.TRISC7
676 // ----- VRCON bits --------------------
686 unsigned char VREN:1;
689 extern volatile __VRCON_bits_t __at(VRCON_ADDR) VRCON_bits;
691 #define VR0 VRCON_bits.VR0
692 #define VR1 VRCON_bits.VR1
693 #define VR2 VRCON_bits.VR2
694 #define VR3 VRCON_bits.VR3
695 #define VRR VRCON_bits.VRR
696 #define VREN VRCON_bits.VREN