[fw/sdcc] / device / include / mcs51 / cc2510fx.h

/*-------------------------------------------------------------------------\r
   Register Declarations for Chipcon CC2510Fx/CC2511Fx\r
\r
   Written By -  Jesus Calvino-Fraga / jesusc at ece.ubc.ca (August 2006)\r
   (Based on CC2510Fx/CC2511Fx PRELIMINARY Data Sheet (Rev. 1.2) SWRS055A)\r
\r
   This library is free software; you can redistribute it and/or\r
   modify it under the terms of the GNU Lesser General Public\r
   License as published by the Free Software Foundation; either\r
   version 2.1 of the License, or (at your option) any later version.\r
\r
   This library is distributed in the hope that it will be useful,\r
   but WITHOUT ANY WARRANTY; without even the implied warranty of\r
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\r
   Lesser General Public License for more details.\r
\r
   You should have received a copy of the GNU Lesser General Public\r
   License along with this library; if not, write to the Free Software\r
   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA\r
\r
   In other words, you are welcome to use, share and improve this program.\r
   You are forbidden to forbid anyone else to use, share and improve\r
   what you give them.   Help stamp out software-hoarding!\r
-------------------------------------------------------------------------*/\r
\r
#ifndef REG_CC2510FX_H\r
#define REG_CC2510FX_H\r
\r
#include <compiler.h>\r
\r
// Interrupt Vectors\r
#define RFTXRX_VECTOR   0 // RF TX done / RX ready  \r
#define ADC_VECTOR      1 // ADC end of conversion  \r
#define URX0_VECTOR     2 // USART0 RX complete  \r
#define URX1_VECTOR     3 // USART1 RX complete (I2S RX complete)  \r
#define ENC_VECTOR      4 // AES encryption/decryption complete  \r
#define ST_VECTOR       5 // Sleep Timer compare \r
#define P2INT_VECTOR    6 // Port 2 inputs (Also used for USB on CC2511Fx) \r
#define UTX0_VECTOR     7 // USART0 TX complete \r
#define DMA_VECTOR      8 // DMA transfer complete \r
#define T1_VECTOR       9 // Timer 1 (16-bit) capture/Compare/overflow \r
#define T2_VECTOR      10 // Timer 2 (MAC Timer) overflow \r
#define T3_VECTOR      11 // Timer 3 (8-bit) capture/compare/overflow \r
#define T4_VECTOR      12 // Timer 4 (8-bit) capture/compare/overflow \r
#define P0INT_VECTOR   13 // Port 0 inputs (Note: USB Resume from suspend interrupt on P0_7 on CC2511Fx ) \r
#define UTX1_VECTOR    14 // USART1 TX complete (I2S TX complete) \r
#define P1INT_VECTOR   15 // Port 1 inputs \r
#define RF_VECTOR      16 // RF general interrupts \r
#define WDT_VECTOR     17 // Watchdog overflow in timer mode \r
\r
//Shared Interrupt Vectors (I2S and USB)\r
#define I2SRX_VECTOR    3 //I2S RX complete \r
#define I2STX_VECTOR   14 //I2S TX complete \r
#define USB_VECTOR      6 //USB Interrupt pending ( CC2511Fx ) \r
\r
// SFR Registers and BITs\r
\r
SFR(P0,       0x80); // Port 0 \r
   SBIT(P0_0,     0x80, 0); // Port 0 bit 0\r
   SBIT(P0_1,     0x80, 1); // Port 0 bit 1\r
   SBIT(P0_2,     0x80, 2); // Port 0 bit 2\r
   SBIT(P0_3,     0x80, 3); // Port 0 bit 3\r
   SBIT(P0_4,     0x80, 4); // Port 0 bit 4\r
   SBIT(P0_5,     0x80, 5); // Port 0 bit 5\r
   SBIT(P0_6,     0x80, 6); // Port 0 bit 6\r
   SBIT(P0_7,     0x80, 7); // Port 0 bit 7\r
SFR(SP,       0x81); // Stack Pointer \r
SFR(DPL0,     0x82); // Data Pointer 0 Low Byte\r
SFR(DPH0,     0x83); // Data Pointer 0 High Byte\r
SFR(DPL1,     0x84); // Data Pointer 1 Low Byte\r
SFR(DPH1,     0x85); // Data Pointer 1 High Byte\r
SFR(U0CSR,    0x86); // USART 0 Control and Status \r
SFR(PCON,     0x87); // Power Mode Control \r
SFR(TCON,     0x88); // Interrupt Flag \r
   SBIT(IT0,      0x88, 0); // reserved (must always be set to 1) \r
   SBIT(RFTXRXIF, 0x88, 1); // RF TX/RX FIFO Interrupt Flag \r
   SBIT(IT1,      0x88, 2); // reserved (must always be set to 1) \r
   SBIT(URX0IF,   0x88, 3); // USART0 RX Interrupt Flag \r
   SBIT(ADCIF,    0x88, 5); // ADC Interrupt Flag \r
   SBIT(URX1IF,   0x88, 7); // USART1 RX Interrupt Flag \r
   SBIT(I2SRXIF,  0x88, 7); // I2S RX interrupt flag (same loc as URX1IF) \r
SFR(P0IFG,    0x89); // Port 0 Interrupt Status Flag \r
SFR(P1IFG,    0x8A); // Port 1 Interrupt Status Flag \r
SFR(P2IFG,    0x8B); // Port 2 Interrupt Status Flag\r
SFR(PICTL,    0x8C); // Port Interrupt Control\r
SFR(P1IEN,    0x8D); // Port 1 Interrupt Mask \r
SFR(P0INP,    0x8F); // Port 0 Input Mode \r
SFR(P1,       0x90); // Port 1 \r
   SBIT(P1_0,     0x90, 0); // Port 1 bit 0\r
   SBIT(P1_1,     0x90, 1); // Port 1 bit 1\r
   SBIT(P1_2,     0x90, 2); // Port 1 bit 2\r
   SBIT(P1_3,     0x90, 3); // Port 1 bit 3\r
   SBIT(P1_4,     0x90, 4); // Port 1 bit 4\r
   SBIT(P1_5,     0x90, 5); // Port 1 bit 5\r
   SBIT(P1_6,     0x90, 6); // Port 1 bit 6\r
   SBIT(P1_7,     0x90, 7); // Port 1 bit 7\r
SFR(RFIM,     0x91); // RF Interrupt Mask\r
SFR(DPS,      0x92); // Data Pointer Select \r
SFR(MPAGE,    0x93); // Memory Page Select \r
SFR(ENDIAN,   0x95); // USB Endianess Control (CC2511Fx) \r
SFR(S0CON,    0x98); // Interrupt Flag 2\r
   SBIT(ENCIF_0,  0x98, 0); // AES Interrupt Flag 0 \r
   SBIT(ENCIF_1,  0x98, 1); // AES Interrupt Flag 1 \r
SFR(IEN2,     0x9A); // Interrupt Enable 2 Register\r
SFR(S1CON,    0x9B); // Interrupt Flag 3 \r
SFR(T2CT,     0x9C); // Timer 2 Count\r
SFR(T2PR,     0x9D); // Timer 2 Prescaler\r
SFR(T2CTL,    0x9E); // Timer 2 Control \r
SFR(P2,       0xA0); // Port 2\r
   SBIT(P2_0,     0xA0, 0); // Port 2 bit 0\r
   SBIT(P2_1,     0xA0, 1); // Port 2 bit 1\r
   SBIT(P2_2,     0xA0, 2); // Port 2 bit 2\r
   SBIT(P2_3,     0xA0, 3); // Port 2 bit 3\r
   SBIT(P2_4,     0xA0, 4); // Port 2 bit 4\r
   SBIT(P2_5,     0xA0, 5); // Port 2 bit 5\r
   SBIT(P2_6,     0xA0, 6); // Port 2 bit 6\r
   SBIT(P2_7,     0xA0, 7); // Port 2 bit 7\r
SFR(WORIRQ,   0xA1); // Sleep Timer Interrupt Control\r
SFR(WORCTL,   0xA2); // Sleep Timer Control\r
SFR(WORCTRL,  0xA2); // Sleep Timer Control (typo in datasheet?)\r
SFR(WOREVT0,  0xA3); // Sleep Timer Event0 Timeout Low\r
SFR(WOREVT1,  0xA4); // Sleep Timer Event0 Timeout High \r
SFR(WORTIME0, 0xA5); // Sleep Timer Low Byte \r
SFR(WORTIME1, 0xA6); // Sleep Timer High Byte \r
SFR(IEN0,     0xA8); // Interrupt Enable 0 Register\r
   SBIT(RFTXRXIE, 0xA8, 0); // RF TX/RX done interrupt enable \r
   SBIT(ADCIE,    0xA8, 1); // ADC Interrupt Enable \r
   SBIT(URX0IE,   0xA8, 2); // USART0 RX Interrupt Enable \r
   SBIT(URX1IE,   0xA8, 3); // USART1 RX Interrupt Enable\r
   SBIT(I2SRXIE,  0xA8, 3); // I2S RX interrupt enable (Same loc as URX1IE)\r
   SBIT(ENCIE,    0xA8, 4); // AES Encryption/Decryption Interrupt Enable \r
   SBIT(STIE,     0xA8, 5); // Sleep Timer Interrupt Enable \r
   SBIT(EA,       0xA8, 7); // Global Interrupt Enable \r
SFR(IP0,      0xA9); // Interrupt Priority 0\r
SFR(FWT,      0xAB); // Flash Write Timing\r
SFR(FADDRL,   0xAC); // Flash Address Low Byte \r
SFR(FADDRH,   0xAD); // Flash Address High Byte \r
SFR(FCTL,     0xAE); // Flash Control \r
SFR(FWDATA,   0xAF); // Flash Write Data\r
SFR(ENCDI,    0xB1); // Encryption Input Data\r
SFR(ENCDO,    0xB2); // Encryption Output Data\r
SFR(ENCCS,    0xB3); // Encryption Control and Status \r
SFR(ADCCON1,  0xB4); // ADC Control 1 \r
SFR(ADCCON2,  0xB5); // ADC Control 2 \r
SFR(ADCCON3,  0xB6); // ADC Control 3 \r
SFR(IEN1,     0xB8); // Interrupt Enable 1 Register\r
   SBIT(DMAIE,    0xB8, 0); // DMA Transfer Interrupt Enable \r
   SBIT(T1IE,     0xB8, 1); // Timer 1 Interrupt Enable \r
   SBIT(T2IE,     0xB8, 2); // Timer 2 Interrupt Enable \r
   SBIT(T3IE,     0xB8, 3); // Timer 3 Interrupt Enable \r
   SBIT(T4IE,     0xB8, 4); // Timer 4 Interrupt Enable \r
   SBIT(P0IE,     0xB8, 5); // Port 0 Interrupt Enable \r
SFR(IP1,      0xB9); // Interrupt Priority 1 \r
SFR(ADCL,     0xBA); // ADC Data Low\r
SFR(ADCH,     0xBB); // ADC Data High\r
SFR(RNDL,     0xBC); // Random Number Generator Data Low Byte \r
SFR(RNDH,     0xBD); // Random Number Generator Data High Byte\r
SFR(SLEEP,    0xBE); // Sleep Mode Control \r
SFR(IRCON,    0xC0); // Interrupt Flag 4 \r
   SBIT(DMAIF,    0xC0, 0); // DMA Complete Interrupt Flag \r
   SBIT(T1IF,     0xC0, 1); // Timer 1 Interrupt Flag \r
   SBIT(T2IF,     0xC0, 2); // Timer 2 Interrupt Flag \r
   SBIT(T3IF,     0xC0, 3); // Timer 3 Interrupt Flag \r
   SBIT(T4IF,     0xC0, 4); // Timer 4 Interrupt Flag \r
   SBIT(P0IF,     0xC0, 5); // Port 0 Interrupt Flag \r
   SBIT(STIF,     0xC0, 7); // Sleep Timer Interrupt Flag \r
SFR(U0DBUF,   0xC1); // USART 0 Receive/Transmit Data Buffer\r
SFR(U0BAUD,   0xC2); // USART 0 Baud Rate Control\r
SFR(U0UCR,    0xC4); // USART 0 UART Control \r
SFR(U0GCR,    0xC5); // USART 0 Generic Control\r
SFR(CLKCON,   0xC6); // Clock Control\r
SFR(MEMCTR,   0xC7); // Memory Arbiter Control\r
SFR(WDCTL,    0xC9); // Watchdog Timer Control \r
SFR(T3CNT,    0xCA); // Timer 3 Counter\r
SFR(T3CTL,    0xCB); // Timer 3 Control \r
SFR(T3CCTL0,  0xCC); // Timer 3 Channel 0 Capture/Compare Control\r
SFR(T3CC0,    0xCD); // Timer 3 Channel 0 Capture/Compare Value \r
SFR(T3CCTL1,  0xCE); // Timer 3 Channel 1 Capture/Compare Control \r
SFR(T3CC1,    0xCF); // Timer 3 Channel 1 Capture/Compare Value\r
SFR(PSW,      0xD0); // Program Status Word\r
   SBIT(P,        0xD0, 0); // Parity Flag \r
   SBIT(F1,       0xD0, 1); // User-Defined Flag\r
   SBIT(OV,       0xD0, 2); // Overflow Flag \r
   SBIT(RS0,      0xD0, 3); // Register Bank Select 0 \r
   SBIT(RS1,      0xD0, 4); // Register Bank Select 1 \r
   SBIT(F0,       0xD0, 5); // User-Defined Flag\r
   SBIT(AC,       0xD0, 6); // Auxiliary Carry Flag \r
   SBIT(CY,       0xD0, 7); // Carry Flag \r
SFR(DMAIRQ,   0xD1); // DMA Interrupt Flag\r
SFR(DMA1CFGL, 0xD2); // DMA Channel 1-4 Configuration Address Low Byte\r
SFR(DMA1CFGH, 0xD3); // DMA Channel 1-4 Configuration Address High Byte\r
SFR(DMA0CFGL, 0xD4); // DMA Channel 0 Configuration Address Low Byte \r
SFR(DMA0CFGH, 0xD5); // DMA Channel 0 Configuration Address High Byte \r
SFR(DMAARM,   0xD6); // DMA Channel Arm \r
SFR(DMAREQ,   0xD7); // DMA Channel Start Request and Status\r
SFR(TIMIF,    0xD8); // Timers 1/3/4 Interrupt Mask/Flag \r
   SBIT(T3OVFIF,  0xD8, 0); // Timer 3 overflow interrupt flag 0:no pending 1:pending\r
   SBIT(T3CH0IF,  0xD8, 1); // Timer 3 channel 0 interrupt flag 0:no pending 1:pending\r
   SBIT(T3CH1IF,  0xD8, 2); // Timer 3 channel 1 interrupt flag 0:no pending 1:pending\r
   SBIT(T4OVFIF,  0xD8, 3); // Timer 4 overflow interrupt flag 0:no pending 1:pending\r
   SBIT(T4CH0IF,  0xD8, 4); // Timer 4 channel 0 interrupt flag 0:no pending 1:pending\r
   SBIT(T4CH1IF,  0xD8, 5); // Timer 4 channel 1 interrupt flag 0:no pending 1:pending\r
   SBIT(OVFIM,    0xD8, 6); // Timer 1 overflow interrupt mask\r
SFR(RFD,      0xD9); // RF Data\r
SFR(T1CC0L,   0xDA); // Timer 1 Channel 0 Capture/Compare Value Low\r
SFR(T1CC0H,   0xDB); // Timer 1 Channel 0 Capture/Compare Value High \r
SFR(T1CC1L,   0xDC); // Timer 1 Channel 1 Capture/Compare Value Low \r
SFR(T1CC1H,   0xDD); // Timer 1 Channel 1 Capture/Compare Value High \r
SFR(T1CC2L,   0xDE); // Timer 1 Channel 2 Capture/Compare Value Low\r
SFR(T1CC2H,   0xDF); // Timer 1 Channel 2 Capture/Compare Value High\r
SFR(ACC,      0xE0); // Accumulator\r
   SBIT(ACC_0,    0xE0, 0); // Accumulator bit 0\r
   SBIT(ACC_1,    0xE0, 1); // Accumulator bit 1\r
   SBIT(ACC_2,    0xE0, 2); // Accumulator bit 2\r
   SBIT(ACC_3,    0xE0, 3); // Accumulator bit 3\r
   SBIT(ACC_4,    0xE0, 4); // Accumulator bit 4\r
   SBIT(ACC_5,    0xE0, 5); // Accumulator bit 5\r
   SBIT(ACC_6,    0xE0, 6); // Accumulator bit 6\r
   SBIT(ACC_7,    0xE0, 7); // Accumulator bit 7\r
SFR(RFST,     0xE1); // RF Strobe Commands\r
SFR(T1CNTL,   0xE2); // Timer 1 Counter Low \r
SFR(T1CNTH,   0xE3); // Timer 1 Counter High \r
SFR(T1CTL,    0xE4); // Timer 1 Control and Status\r
SFR(T1CCTL0,  0xE5); // Timer 1 Channel 0 Capture/Compare Control\r
SFR(T1CCTL1,  0xE6); // Timer 1 Channel 1 Capture/Compare Control\r
SFR(T1CCTL2,  0xE7); // Timer 1 Channel 2 Capture/Compare Control\r
SFR(IRCON2,   0xE8); // Interrupt Flag 5 \r
   SBIT(P2IF,     0xE8, 0); // Port 2 Interrupt Flag \r
   SBIT(USBIF,    0xE8, 0); // USB Interrupt Flag (same bit as P2IF)\r
   SBIT(UTX0IF,   0xE8, 1); // USART0 TX Interrupt Flag \r
   SBIT(UTX1IF,   0xE8, 2); // USART1 TX Interrupt Flag \r
   SBIT(I2STXIF,  0xE8, 2); // I2S TX Interrupt Flag (same bit as UTX1FIF)\r
   SBIT(P1IF,     0xE8, 3); // Port 1 Interrupt Flag \r
   SBIT(WDTIF,    0xE8, 4); // Watchdog Timer Interrupt Flag \r
SFR(RFIF,     0xE9); // RF Interrupt Flags \r
SFR(T4CNT,    0xEA); // Timer 4 Counter \r
SFR(T4CTL,    0xEB); // Timer 4 Control \r
SFR(T4CCTL0,  0xEC); // Timer 4 Channel 0 Capture/Compare Control \r
SFR(T4CC0,    0xED); // Timer 4 Channel 0 Capture/Compare Value \r
SFR(T4CCTL1,  0xEE); // Timer 4 Channel 1 Capture/Compare Control \r
SFR(T4CC1,    0xEF); // Timer 4 Channel 1 Capture/Compare Value \r
SFR(B,        0xF0); // B Register \r
   SBIT(B_0,      0xF0, 0); // Register B bit 0\r
   SBIT(B_1,      0xF0, 1); // Register B bit 1\r
   SBIT(B_2,      0xF0, 2); // Register B bit 2\r
   SBIT(B_3,      0xF0, 3); // Register B bit 3\r
   SBIT(B_4,      0xF0, 4); // Register B bit 4\r
   SBIT(B_5,      0xF0, 5); // Register B bit 5\r
   SBIT(B_6,      0xF0, 6); // Register B bit 6\r
   SBIT(B_7,      0xF0, 7); // Register B bit 7\r
SFR(PERCFG,   0xF1); // Peripheral Control \r
SFR(ADCCFG,   0xF2); // ADC Input Configuration\r
SFR(P0SEL,    0xF3); // Port 0 Function Select \r
SFR(P1SEL,    0xF4); // Port 1 Function Select \r
SFR(P2SEL,    0xF5); // Port 2 Function Select \r
SFR(P1INP,    0xF6); // Port 1 Input Mode \r
SFR(P2INP,    0xF7); // Port 2 Input Mode \r
SFR(U1CSR,    0xF8); // USART 1 Control and Status\r
   SBIT(ACTIVE,   0xF8, 0); // USART transmit/receive active status 0:idle 1:busy\r
   SBIT(TX_BYTE,  0xF8, 1); // Transmit byte status 0:Byte not transmitted 1:Last byte transmitted\r
   SBIT(RX_BYTE,  0xF8, 2); // Receive byte status 0:No byte received 1:Received byte ready\r
   SBIT(ERR,      0xF8, 3); // UART parity error status 0:No error 1:parity error\r
   SBIT(FE,       0xF8, 4); // UART framing error status 0:No error 1:incorrect stop bit level\r
   SBIT(SLAVE,    0xF8, 5); // SPI master or slave mode select 0:master 1:slave\r
   SBIT(RE,       0xF8, 6); // UART receiver enable 0:disabled 1:enabled\r
   SBIT(MODE,     0xF8, 7); // USART mode select 0:SPI 1:UART\r
SFR(U1DBUF,   0xF9); // USART 1 Receive/Transmit Data Buffer \r
SFR(U1BAUD,   0xFA); // USART 1 Baud Rate Control \r
SFR(U1UCR,    0xFB); // USART 1 UART Control \r
SFR(U1GCR,    0xFC); // USART 1 Generic Control\r
SFR(P0DIR,    0xFD); // Port 0 Direction \r
SFR(P1DIR,    0xFE); // Port 1 Direction\r
SFR(P2DIR,    0xFF); // Port 2 Direction \r
\r
// From table 68: xdata RF registers\r
\r
SFRX(SYNC1,      0xDF00); // Sync word, high byte \r
SFRX(SYNC0,      0xDF01); // Sync word, low byte \r
SFRX(PKTLEN,     0xDF02); // Packet length \r
SFRX(PKTCTRL1,   0xDF03); // Packet automation control \r
SFRX(PKTCTRL0,   0xDF04); // Packet automation control \r
SFRX(ADDR,       0xDF05); // Device address \r
SFRX(CHANNR,     0xDF06); // Channel number \r
SFRX(FSCTRL1,    0xDF07); // Frequency synthesizer control \r
SFRX(FSCTRL0,    0xDF08); // Frequency synthesizer control \r
SFRX(FREQ2,      0xDF09); // Frequency control word, high byte \r
SFRX(FREQ1,      0xDF0A); // Frequency control word, middle byte \r
SFRX(FREQ0,      0xDF0B); // Frequency control word, low byte \r
SFRX(MDMCFG4,    0xDF0C); // Modem configuration \r
SFRX(MDMCFG3,    0xDF0D); // Modem configuration \r
SFRX(MDMCFG2,    0xDF0E); // Modem configuration \r
SFRX(MDMCFG1,    0xDF0F); // Modem configuration \r
SFRX(MDMCFG0,    0xDF10); // Modem configuration \r
SFRX(DEVIATN,    0xDF11); // Modem deviation setting \r
SFRX(MCSM2,      0xDF12); // Main Radio Control State Machine configuration \r
SFRX(MCSM1,      0xDF13); // Main Radio Control State Machine configuration \r
SFRX(MCSM0,      0xDF14); // Main Radio Control State Machine configuration \r
SFRX(FOCCFG,     0xDF15); // Frequency Offset Compensation configuration \r
SFRX(BSCFG,      0xDF16); // Bit Synchronization configuration \r
SFRX(AGCCTRL2,   0xDF17); // AGC control \r
SFRX(AGCCTRL1,   0xDF18); // AGC control \r
SFRX(AGCCTRL0,   0xDF19); // AGC control \r
SFRX(FREND1,     0xDF1A); // Front end RX configuration \r
SFRX(FREND0,     0xDF1B); // Front end TX configuration \r
SFRX(FSCAL3,     0xDF1C); // Frequency synthesizer calibration \r
SFRX(FSCAL2,     0xDF1D); // Frequency synthesizer calibration \r
SFRX(FSCAL1,     0xDF1E); // Frequency synthesizer calibration \r
SFRX(FSCAL0,     0xDF1F); // Frequency synthesizer calibration \r
SFRX(PA_TABLE7,  0xDF27); // PA output power setting \r
SFRX(PA_TABLE6,  0xDF28); // PA output power setting \r
SFRX(PA_TABLE5,  0xDF29); // PA output power setting \r
SFRX(PA_TABLE4,  0xDF2A); // PA output power setting \r
SFRX(PA_TABLE3,  0xDF2B); // PA output power setting \r
SFRX(PA_TABLE2,  0xDF2C); // PA output power setting \r
SFRX(PA_TABLE1,  0xDF2D); // PA output power setting \r
SFRX(PA_TABLE0,  0xDF2E); // PA output power setting \r
SFRX(IOCFG2,     0xDF2F); // GDO2 output pin configuration \r
SFRX(IOCFG1,     0xDF30); // GDO1 output pin configuration \r
SFRX(IOCFG0,     0xDF31); // GDO0 output pin configuration \r
SFRX(PARTNUM,    0xDF36); // Chip Identifier \r
SFRX(VERSION,    0xDF37); // Configuration \r
SFRX(FREQEST,    0xDF38); // Frequency Offset Estimate \r
SFRX(LQI,        0xDF39); // Link Quality Indicator \r
SFRX(RSSI,       0xDF3A); // Received Signal Strength Indication \r
SFRX(MARCSTATE,  0xDF3B); // Main Radio Control State \r
SFRX(PKTSTATUS,  0xDF3C); // Packet status \r
SFRX(VCO_VC_DAC, 0xDF3D); // PLL calibration current \r
\r
// I2S Registers\r
\r
SFRX(I2SCFG0,  0xDF40); // I2S Configuration Register 0 \r
SFRX(I2SCFG1,  0xDF41); // I2S Configuration Register 1 \r
SFRX(I2SDATL,  0xDF42); // I2S Data Low Byte \r
SFRX(I2SDATH,  0xDF43); // I2S Data High Byte \r
SFRX(I2SWCNT,  0xDF44); // I2S Word Count Register \r
SFRX(I2SSTAT,  0xDF45); // I2S Status Register \r
SFRX(I2SCLKF0, 0xDF46); // I2S Clock Configuration Register 0 \r
SFRX(I2SCLKF1, 0xDF47); // I2S Clock Configuration Register 1 \r
SFRX(I2SCLKF2, 0xDF48); // I2S Clock Configuration Register 2\r
\r
// Common USB Registers\r
\r
SFRX(USBADDR,  0xDE00); // Function Address\r
SFRX(USBPOW,   0xDE01); // Power/Control Register\r
SFRX(USBIIF,   0xDE02); // IN Endpoints and EP0 Interrupt Flags\r
SFRX(USBOIF,   0xDE04); // OUT Endpoints Interrupt Flags\r
SFRX(USBCIF,   0xDE06); // Common USB Interrupt Flags\r
SFRX(USBIIE,   0xDE07); // IN Endpoints and EP0 Interrupt Enable Mask\r
SFRX(USBOIE,   0xDE09); // Out Endpoints Interrupt Enable Mask\r
SFRX(USBCIE,   0xDE0B); // Common USB Interrupt Enable Mask\r
SFRX(USBFRML,  0xDE0C); // Current Frame Number (Low byte)\r
SFRX(USBFRMH,  0xDE0D); // Current Frame Number (High byte)\r
SFRX(USBINDEX, 0xDE0E); // Selects current endpoint.\r
\r
// Indexed Endpoint Registers\r
\r
SFRX(USBMAXI, 0xDE10); // Max. packet size for IN endpoint\r
SFRX(USBCS0,  0xDE11); // EP0 Control and Status (USBINDEX = 0)\r
SFRX(USBCSIL, 0xDE11); // IN EP{1-5} Control and Status Low\r
SFRX(USBCSIH, 0xDE12); // IN EP{1-5} Control and Status High\r
SFRX(USBMAXO, 0xDE13); // Max. packet size for OUT endpoint\r
SFRX(USBCSOL, 0xDE14); // OUT EP{1-5} Control and Status Low\r
SFRX(USBCSOH, 0xDE15); // OUT EP{1-5} Control and Status High\r
SFRX(USBCNT0, 0xDE16); // Number of received bytes in EP0 FIFO (USBINDEX = 0)\r
SFRX(USBCNTL, 0xDE16); // Number of bytes in OUT FIFO Low\r
SFRX(USBCNTH, 0xDE17); // Number of bytes in OUT FIFO High\r
\r
// Endpoint FIFO Registers\r
\r
SFRX(USBF0, 0xDE20); //  Endpoint 0 FIFO\r
SFRX(USBF1, 0xDE22); //  Endpoint 1 FIFO\r
SFRX(USBF2, 0xDE24); //  Endpoint 2 FIFO\r
SFRX(USBF3, 0xDE26); //  Endpoint 3 FIFO\r
SFRX(USBF4, 0xDE28); //  Endpoint 4 FIFO\r
SFRX(USBF5, 0xDE2A); //  Endpoint 5 FIFO\r
\r
// SFRs also accesible through XDATA space\r
\r
SFRX(X_U0CSR,    0xDF86); // USART 0 Control and Status\r
SFRX(X_P0IFG,    0xDF89); // Port 0 Interrupt Status Flag\r
SFRX(X_P1IFG,    0xDF8A); // Port 1 Interrupt Status Flag\r
SFRX(X_P2IFG,    0xDF8B); // Port 2 Interrupt Status Flag\r
SFRX(X_PICTL,    0xDF8C); // Port Pins Interrupt Mask and Edge\r
SFRX(X_P1IEN,    0xDF8D); // Port 1 Interrupt Mask\r
SFRX(X_P0INP,    0xDF8F); // Port 0 Input Mode\r
SFRX(X_RFIM,     0xDF91); // RF Interrupt Mask\r
SFRX(X_MPAGE,    0xDF93); // Memory Page Select \r
SFRX(X_T2CT,     0xDF9C); // Timer 2 Control\r
SFRX(X_T2PR,     0xDF9D); // Timer 2 Prescaler\r
SFRX(X_T2CTL,    0xDF9E); // Timer 2 Control\r
SFRX(X_WORIRQ,   0xDFA1); // Timer Sleep Timer Interrupts\r
SFRX(X_WORCTL,   0xDFA2); // Sleep Timer Control \r
SFRX(X_WOREVT0,  0xDFA3); // Timer Sleep Timer Event 0 Timeout Low Byte\r
SFRX(X_WOREVT1,  0xDFA4); // Timer Sleep Timer Event 0 Timeout High Byte\r
SFRX(X_WORTIME0, 0xDFA5); // Sleep Timer Value 0 \r
SFRX(X_WORTIME1, 0xDFA6); // Sleep Timer Value 1 \r
SFRX(X_FWT,      0xDFAB); // Flash Write Timing\r
SFRX(X_FADDRL,   0xDFAC); // Flash Address Low\r
SFRX(X_FADDRH,   0xDFAD); // Flash Address High\r
SFRX(X_FCTL,     0xDFAE); // Flash Control\r
SFRX(X_FWDATA,   0xDFAF); // Flash Write Data\r
SFRX(X_ENCDI,    0xDFB1); // Encryption/Decryption Input Data\r
SFRX(X_ENCDO,    0xDFB2); // Encryption/Decryption Output Data\r
SFRX(X_ENCCS,    0xDFB3); // Encryption/Decryption Control and Status\r
SFRX(X_ADCCON1,  0xDFB4); // ADC Control 1\r
SFRX(X_ADCCON2,  0xDFB5); // ADC Control 2\r
SFRX(X_ADCCON3,  0xDFB6); // ADC Control 3\r
SFRX(X_ADCL,     0xDFBA); // ADC Data Low\r
SFRX(X_ADCH,     0xDFBB); // ADC Data High\r
SFRX(X_RNDL,     0xDFBC); // Random Number Generator Data Low\r
SFRX(X_RNDH,     0xDFBD); // Random Number Generator Data High\r
SFRX(X_SLEEP,    0xDFBE); // Flash Write Timing\r
SFRX(X_U0DBUF,   0xDFC1); // USART 0 Receive/Transmit Data Buffer\r
SFRX(X_U0BAUD,   0xDFC2); // USART 0 Baud Rate Control\r
SFRX(X_U0UCR,    0xDFC4); // USART 0 UART Control\r
SFRX(X_U0GCR,    0xDFC5); // USART 0 Generic Control\r
SFRX(X_CLKCON,   0xDFC6); // Clock Control\r
SFRX(X_MEMCTR,   0xDFC7); // Memory System Control\r
SFRX(X_WDCTL,    0xDFC9); // Watchdog Timer Control\r
SFRX(X_T3CNT,    0xDFCA); // Timer 3 Counter\r
SFRX(X_T3CTL,    0xDFCB); // Timer 3 Control\r
SFRX(X_T3CCTL0,  0xDFCC); // Timer 3 Channel 0 Capture/Compare Control\r
SFRX(X_T3CC0,    0xDFCD); // Timer 3 Channel 0 Capture/Compare Value\r
SFRX(X_T3CCTL1,  0xDFCE); // Timer 3 Channel 1 Capture/Compare Control\r
SFRX(X_T3CC1,    0xDFCF); // Timer 3 Channel 1 Capture/Compare Value\r
SFRX(X_DMAIRQ,   0xDFD1); // DMA Interrupt Flag\r
SFRX(X_DMA1CFGL, 0xDFD2); // DMA Channel 1-4 Configuration Address Low Byte\r
SFRX(X_DMA1CFGH, 0xDFD3); // DMA Channel 1-4 Configuration Address High Byte\r
SFRX(X_DMA0CFGL, 0xDFD4); // DMA Channel 0 Configuration Address Low Byte\r
SFRX(X_DMA0CFGH, 0xDFD5); // DMA Channel 0 Configuration Address High Byte\r
SFRX(X_DMAARM,   0xDFD6); // DMA Channel Arm\r
SFRX(X_DMAREQ,   0xDFD7); // DMA Channel Start Request and Status\r
SFRX(X_TIMIF,    0xDFD8); // Timers 1/3/4 Joint Interrupt Mask/Flags\r
SFRX(X_RFD,      0xDFD9); // RF Data\r
SFRX(X_T1CC0L,   0xDFDA); // Timer 1 Channel 0 Capture/Compare Value Low\r
SFRX(X_T1CC0H,   0xDFDB); // Timer 1 Channel 0 Capture/Compare Value High\r
SFRX(X_T1CC1L,   0xDFDC); // Timer 1 Channel 1 Capture/Compare Value Low\r
SFRX(X_T1CC1H,   0xDFDD); // Timer 1 Channel 1 Capture/Compare Value High\r
SFRX(X_T1CC2L,   0xDFDE); // Timer 1 Channel 2 Capture/Compare Value Low\r
SFRX(X_T1CC2H,   0xDFDF); // Timer 1 Channel 2 Capture/Compare Value High\r
SFRX(X_RFST,     0xDFE1); // RF Strobe Commands\r
SFRX(X_T1CNTL,   0xDFE2); // Timer 1 Counter Low\r
SFRX(X_T1CNTH,   0xDFE3); // Timer 1 Counter High\r
SFRX(X_T1CTL,    0xDFE4); // Timer 1 Control and Status\r
SFRX(X_T1CCTL0,  0xDFE5); // Timer 1 Channel 0 Capture/Compare Control\r
SFRX(X_T1CCTL1,  0xDFE6); // Timer 1 Channel 1 Capture/Compare Control\r
SFRX(X_T1CCTL2,  0xDFE7); // Timer 1 Channel 2 Capture/Compare Control\r
SFRX(X_RFIF,     0xDFE9); // RF Interrupt flags\r
SFRX(X_T4CNT,    0xDFEA); // Timer 4 Counter\r
SFRX(X_T4CTL,    0xDFEB); // Timer 4 Control\r
SFRX(X_T4CCTL0,  0xDFEC); // Timer 4 Channel 0 Capture/Compare Control\r
SFRX(X_T4CC0,    0xDFED); // Timer 4 Channel 0 Capture/Compare Value\r
SFRX(X_T4CCTL1,  0xDFEE); // Timer 4 Channel 1 Capture/Compare Control\r
SFRX(X_T4CC1,    0xDFEF); // Timer 4 Channel 1 Capture/Compare Value\r
SFRX(X_PERCFG,   0xDFF1); // Peripheral I/O Control\r
SFRX(X_ADCCFG,   0xDFF2); // ADC Input Configuration\r
SFRX(X_P0SEL,    0xDFF3); // Port 0 Function Select\r
SFRX(X_P1SEL,    0xDFF4); // Port 1 Function Select\r
SFRX(X_P2SEL,    0xDFF5); // Port 2 Function Select\r
SFRX(X_P1INP,    0xDFF6); // Port 1 Input Mode\r
SFRX(X_P2INP,    0xDFF7); // Port 2 Input Mode\r
SFRX(X_U1CSR,    0xDFF8); // USART 1 Control and Status\r
SFRX(X_U1DBUF,   0xDFF9); // USART 1 Receive/Transmit Data Buffer\r
SFRX(X_U1BAUD,   0xDFFA); // USART 1 Baud Rate Control\r
SFRX(X_U1UCR,    0xDFFB); // USART 1 UART Control\r
SFRX(X_U1GCR,    0xDFFC); // USART 1 Generic Control\r
SFRX(X_P0DIR,    0xDFFD); // Port 0 Direction\r
SFRX(X_P1DIR,    0xDFFE); // Port 1 Direction\r
SFRX(X_P2DIR,    0xDFFF); // Port 2 Direction\r
\r
#endif //REG_CC2510FX_H\r
\r