1 /*-------------------------------------------------------------------------
2 Register Declarations for Chipcon CC2510Fx/CC2511Fx
4 Written By - Jesus Calvino-Fraga / jesusc at ece.ubc.ca (August 2006)
5 (Based on CC2510Fx/CC2511Fx PRELIMINARY Data Sheet (Rev. 1.2) SWRS055A)
7 This library is free software; you can redistribute it and/or
8 modify it under the terms of the GNU Lesser General Public
9 License as published by the Free Software Foundation; either
10 version 2.1 of the License, or (at your option) any later version.
12 This library is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 Lesser General Public License for more details.
17 You should have received a copy of the GNU Lesser General Public
18 License along with this library; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 In other words, you are welcome to use, share and improve this program.
22 You are forbidden to forbid anyone else to use, share and improve
23 what you give them. Help stamp out software-hoarding!
24 -------------------------------------------------------------------------*/
26 #ifndef REG_CC2510FX_H
27 #define REG_CC2510FX_H
32 #define RFTXRX_VECTOR 0 // RF TX done / RX ready
33 #define ADC_VECTOR 1 // ADC end of conversion
34 #define URX0_VECTOR 2 // USART0 RX complete
35 #define URX1_VECTOR 3 // USART1 RX complete (I2S RX complete)
36 #define ENC_VECTOR 4 // AES encryption/decryption complete
37 #define ST_VECTOR 5 // Sleep Timer compare
38 #define P2INT_VECTOR 6 // Port 2 inputs (Also used for USB on CC2511Fx)
39 #define UTX0_VECTOR 7 // USART0 TX complete
40 #define DMA_VECTOR 8 // DMA transfer complete
41 #define T1_VECTOR 9 // Timer 1 (16-bit) capture/Compare/overflow
42 #define T2_VECTOR 10 // Timer 2 (MAC Timer) overflow
43 #define T3_VECTOR 11 // Timer 3 (8-bit) capture/compare/overflow
44 #define T4_VECTOR 12 // Timer 4 (8-bit) capture/compare/overflow
45 #define P0INT_VECTOR 13 // Port 0 inputs (Note: USB Resume from suspend interrupt on P0_7 on CC2511Fx )
46 #define UTX1_VECTOR 14 // USART1 TX complete (I2S TX complete)
47 #define P1INT_VECTOR 15 // Port 1 inputs
48 #define RF_VECTOR 16 // RF general interrupts
49 #define WDT_VECTOR 17 // Watchdog overflow in timer mode
51 //Shared Interrupt Vectors (I2S and USB)
52 #define I2SRX_VECTOR 3 //I2S RX complete
53 #define I2STX_VECTOR 14 //I2S TX complete
54 #define USB_VECTOR 6 //USB Interrupt pending ( CC2511Fx )
56 // SFR Registers and BITs
58 SFR(P0, 0x80); // Port 0
59 SBIT(P0_0, 0x80, 0); // Port 0 bit 0
60 SBIT(P0_1, 0x80, 1); // Port 0 bit 1
61 SBIT(P0_2, 0x80, 2); // Port 0 bit 2
62 SBIT(P0_3, 0x80, 3); // Port 0 bit 3
63 SBIT(P0_4, 0x80, 4); // Port 0 bit 4
64 SBIT(P0_5, 0x80, 5); // Port 0 bit 5
65 SBIT(P0_6, 0x80, 6); // Port 0 bit 6
66 SBIT(P0_7, 0x80, 7); // Port 0 bit 7
67 SFR(SP, 0x81); // Stack Pointer
68 SFR(DPL0, 0x82); // Data Pointer 0 Low Byte
69 SFR(DPH0, 0x83); // Data Pointer 0 High Byte
70 SFR(DPL1, 0x84); // Data Pointer 1 Low Byte
71 SFR(DPH1, 0x85); // Data Pointer 1 High Byte
72 SFR(U0CSR, 0x86); // USART 0 Control and Status
73 SFR(PCON, 0x87); // Power Mode Control
74 SFR(TCON, 0x88); // Interrupt Flag
75 SBIT(IT0, 0x88, 0); // reserved (must always be set to 1)
76 SBIT(RFTXRXIF, 0x88, 1); // RF TX/RX FIFO Interrupt Flag
77 SBIT(IT1, 0x88, 2); // reserved (must always be set to 1)
78 SBIT(URX0IF, 0x88, 3); // USART0 RX Interrupt Flag
79 SBIT(ADCIF, 0x88, 5); // ADC Interrupt Flag
80 SBIT(URX1IF, 0x88, 7); // USART1 RX Interrupt Flag
81 SBIT(I2SRXIF, 0x88, 7); // I2S RX interrupt flag (same loc as URX1IF)
82 SFR(P0IFG, 0x89); // Port 0 Interrupt Status Flag
83 SFR(P1IFG, 0x8A); // Port 1 Interrupt Status Flag
84 SFR(P2IFG, 0x8B); // Port 2 Interrupt Status Flag
85 SFR(PICTL, 0x8C); // Port Interrupt Control
86 SFR(P1IEN, 0x8D); // Port 1 Interrupt Mask
87 SFR(P0INP, 0x8F); // Port 0 Input Mode
88 SFR(P1, 0x90); // Port 1
89 SBIT(P1_0, 0x90, 0); // Port 1 bit 0
90 SBIT(P1_1, 0x90, 1); // Port 1 bit 1
91 SBIT(P1_2, 0x90, 2); // Port 1 bit 2
92 SBIT(P1_3, 0x90, 3); // Port 1 bit 3
93 SBIT(P1_4, 0x90, 4); // Port 1 bit 4
94 SBIT(P1_5, 0x90, 5); // Port 1 bit 5
95 SBIT(P1_6, 0x90, 6); // Port 1 bit 6
96 SBIT(P1_7, 0x90, 7); // Port 1 bit 7
97 SFR(RFIM, 0x91); // RF Interrupt Mask
98 SFR(DPS, 0x92); // Data Pointer Select
99 SFR(MPAGE, 0x93); // Memory Page Select
100 SFR(ENDIAN, 0x95); // USB Endianess Control (CC2511Fx)
101 SFR(S0CON, 0x98); // Interrupt Flag 2
102 SBIT(ENCIF_0, 0x98, 0); // AES Interrupt Flag 0
103 SBIT(ENCIF_1, 0x98, 1); // AES Interrupt Flag 1
104 SFR(IEN2, 0x9A); // Interrupt Enable 2 Register
105 SFR(S1CON, 0x9B); // Interrupt Flag 3
106 SFR(T2CT, 0x9C); // Timer 2 Count
107 SFR(T2PR, 0x9D); // Timer 2 Prescaler
108 SFR(T2CTL, 0x9E); // Timer 2 Control
109 SFR(P2, 0xA0); // Port 2
110 SBIT(P2_0, 0xA0, 0); // Port 2 bit 0
111 SBIT(P2_1, 0xA0, 1); // Port 2 bit 1
112 SBIT(P2_2, 0xA0, 2); // Port 2 bit 2
113 SBIT(P2_3, 0xA0, 3); // Port 2 bit 3
114 SBIT(P2_4, 0xA0, 4); // Port 2 bit 4
115 SBIT(P2_5, 0xA0, 5); // Port 2 bit 5
116 SBIT(P2_6, 0xA0, 6); // Port 2 bit 6
117 SBIT(P2_7, 0xA0, 7); // Port 2 bit 7
118 SFR(WORIRQ, 0xA1); // Sleep Timer Interrupt Control
119 SFR(WORCTL, 0xA2); // Sleep Timer Control
120 SFR(WORCTRL, 0xA2); // Sleep Timer Control (typo in datasheet?)
121 SFR(WOREVT0, 0xA3); // Sleep Timer Event0 Timeout Low
122 SFR(WOREVT1, 0xA4); // Sleep Timer Event0 Timeout High
123 SFR(WORTIME0, 0xA5); // Sleep Timer Low Byte
124 SFR(WORTIME1, 0xA6); // Sleep Timer High Byte
125 SFR(IEN0, 0xA8); // Interrupt Enable 0 Register
126 SBIT(RFTXRXIE, 0xA8, 0); // RF TX/RX done interrupt enable
127 SBIT(ADCIE, 0xA8, 1); // ADC Interrupt Enable
128 SBIT(URX0IE, 0xA8, 2); // USART0 RX Interrupt Enable
129 SBIT(URX1IE, 0xA8, 3); // USART1 RX Interrupt Enable
130 SBIT(I2SRXIE, 0xA8, 3); // I2S RX interrupt enable (Same loc as URX1IE)
131 SBIT(ENCIE, 0xA8, 4); // AES Encryption/Decryption Interrupt Enable
132 SBIT(STIE, 0xA8, 5); // Sleep Timer Interrupt Enable
133 SBIT(EA, 0xA8, 7); // Global Interrupt Enable
134 SFR(IP0, 0xA9); // Interrupt Priority 0
135 SFR(FWT, 0xAB); // Flash Write Timing
136 SFR(FADDRL, 0xAC); // Flash Address Low Byte
137 SFR(FADDRH, 0xAD); // Flash Address High Byte
138 SFR(FCTL, 0xAE); // Flash Control
139 SFR(FWDATA, 0xAF); // Flash Write Data
140 SFR(ENCDI, 0xB1); // Encryption Input Data
141 SFR(ENCDO, 0xB2); // Encryption Output Data
142 SFR(ENCCS, 0xB3); // Encryption Control and Status
143 SFR(ADCCON1, 0xB4); // ADC Control 1
144 SFR(ADCCON2, 0xB5); // ADC Control 2
145 SFR(ADCCON3, 0xB6); // ADC Control 3
146 SFR(IEN1, 0xB8); // Interrupt Enable 1 Register
147 SBIT(DMAIE, 0xB8, 0); // DMA Transfer Interrupt Enable
148 SBIT(T1IE, 0xB8, 1); // Timer 1 Interrupt Enable
149 SBIT(T2IE, 0xB8, 2); // Timer 2 Interrupt Enable
150 SBIT(T3IE, 0xB8, 3); // Timer 3 Interrupt Enable
151 SBIT(T4IE, 0xB8, 4); // Timer 4 Interrupt Enable
152 SBIT(P0IE, 0xB8, 5); // Port 0 Interrupt Enable
153 SFR(IP1, 0xB9); // Interrupt Priority 1
154 SFR(ADCL, 0xBA); // ADC Data Low
155 SFR(ADCH, 0xBB); // ADC Data High
156 SFR(RNDL, 0xBC); // Random Number Generator Data Low Byte
157 SFR(RNDH, 0xBD); // Random Number Generator Data High Byte
158 SFR(SLEEP, 0xBE); // Sleep Mode Control
159 SFR(IRCON, 0xC0); // Interrupt Flag 4
160 SBIT(DMAIF, 0xC0, 0); // DMA Complete Interrupt Flag
161 SBIT(T1IF, 0xC0, 1); // Timer 1 Interrupt Flag
162 SBIT(T2IF, 0xC0, 2); // Timer 2 Interrupt Flag
163 SBIT(T3IF, 0xC0, 3); // Timer 3 Interrupt Flag
164 SBIT(T4IF, 0xC0, 4); // Timer 4 Interrupt Flag
165 SBIT(P0IF, 0xC0, 5); // Port 0 Interrupt Flag
166 SBIT(STIF, 0xC0, 7); // Sleep Timer Interrupt Flag
167 SFR(U0DBUF, 0xC1); // USART 0 Receive/Transmit Data Buffer
168 SFR(U0BAUD, 0xC2); // USART 0 Baud Rate Control
169 SFR(U0UCR, 0xC4); // USART 0 UART Control
170 SFR(U0GCR, 0xC5); // USART 0 Generic Control
171 SFR(CLKCON, 0xC6); // Clock Control
172 SFR(MEMCTR, 0xC7); // Memory Arbiter Control
173 SFR(WDCTL, 0xC9); // Watchdog Timer Control
174 SFR(T3CNT, 0xCA); // Timer 3 Counter
175 SFR(T3CTL, 0xCB); // Timer 3 Control
176 SFR(T3CCTL0, 0xCC); // Timer 3 Channel 0 Capture/Compare Control
177 SFR(T3CC0, 0xCD); // Timer 3 Channel 0 Capture/Compare Value
178 SFR(T3CCTL1, 0xCE); // Timer 3 Channel 1 Capture/Compare Control
179 SFR(T3CC1, 0xCF); // Timer 3 Channel 1 Capture/Compare Value
180 SFR(PSW, 0xD0); // Program Status Word
181 SBIT(P, 0xD0, 0); // Parity Flag
182 SBIT(F1, 0xD0, 1); // User-Defined Flag
183 SBIT(OV, 0xD0, 2); // Overflow Flag
184 SBIT(RS0, 0xD0, 3); // Register Bank Select 0
185 SBIT(RS1, 0xD0, 4); // Register Bank Select 1
186 SBIT(F0, 0xD0, 5); // User-Defined Flag
187 SBIT(AC, 0xD0, 6); // Auxiliary Carry Flag
188 SBIT(CY, 0xD0, 7); // Carry Flag
189 SFR(DMAIRQ, 0xD1); // DMA Interrupt Flag
190 SFR(DMA1CFGL, 0xD2); // DMA Channel 1-4 Configuration Address Low Byte
191 SFR(DMA1CFGH, 0xD3); // DMA Channel 1-4 Configuration Address High Byte
192 SFR(DMA0CFGL, 0xD4); // DMA Channel 0 Configuration Address Low Byte
193 SFR(DMA0CFGH, 0xD5); // DMA Channel 0 Configuration Address High Byte
194 SFR(DMAARM, 0xD6); // DMA Channel Arm
195 SFR(DMAREQ, 0xD7); // DMA Channel Start Request and Status
196 SFR(TIMIF, 0xD8); // Timers 1/3/4 Interrupt Mask/Flag
197 SBIT(T3OVFIF, 0xD8, 0); // Timer 3 overflow interrupt flag 0:no pending 1:pending
198 SBIT(T3CH0IF, 0xD8, 1); // Timer 3 channel 0 interrupt flag 0:no pending 1:pending
199 SBIT(T3CH1IF, 0xD8, 2); // Timer 3 channel 1 interrupt flag 0:no pending 1:pending
200 SBIT(T4OVFIF, 0xD8, 3); // Timer 4 overflow interrupt flag 0:no pending 1:pending
201 SBIT(T4CH0IF, 0xD8, 4); // Timer 4 channel 0 interrupt flag 0:no pending 1:pending
202 SBIT(T4CH1IF, 0xD8, 5); // Timer 4 channel 1 interrupt flag 0:no pending 1:pending
203 SBIT(OVFIM, 0xD8, 6); // Timer 1 overflow interrupt mask
204 SFR(RFD, 0xD9); // RF Data
205 SFR(T1CC0L, 0xDA); // Timer 1 Channel 0 Capture/Compare Value Low
206 SFR(T1CC0H, 0xDB); // Timer 1 Channel 0 Capture/Compare Value High
207 SFR(T1CC1L, 0xDC); // Timer 1 Channel 1 Capture/Compare Value Low
208 SFR(T1CC1H, 0xDD); // Timer 1 Channel 1 Capture/Compare Value High
209 SFR(T1CC2L, 0xDE); // Timer 1 Channel 2 Capture/Compare Value Low
210 SFR(T1CC2H, 0xDF); // Timer 1 Channel 2 Capture/Compare Value High
211 SFR(ACC, 0xE0); // Accumulator
212 SBIT(ACC_0, 0xE0, 0); // Accumulator bit 0
213 SBIT(ACC_1, 0xE0, 1); // Accumulator bit 1
214 SBIT(ACC_2, 0xE0, 2); // Accumulator bit 2
215 SBIT(ACC_3, 0xE0, 3); // Accumulator bit 3
216 SBIT(ACC_4, 0xE0, 4); // Accumulator bit 4
217 SBIT(ACC_5, 0xE0, 5); // Accumulator bit 5
218 SBIT(ACC_6, 0xE0, 6); // Accumulator bit 6
219 SBIT(ACC_7, 0xE0, 7); // Accumulator bit 7
220 SFR(RFST, 0xE1); // RF Strobe Commands
221 SFR(T1CNTL, 0xE2); // Timer 1 Counter Low
222 SFR(T1CNTH, 0xE3); // Timer 1 Counter High
223 SFR(T1CTL, 0xE4); // Timer 1 Control and Status
224 SFR(T1CCTL0, 0xE5); // Timer 1 Channel 0 Capture/Compare Control
225 SFR(T1CCTL1, 0xE6); // Timer 1 Channel 1 Capture/Compare Control
226 SFR(T1CCTL2, 0xE7); // Timer 1 Channel 2 Capture/Compare Control
227 SFR(IRCON2, 0xE8); // Interrupt Flag 5
228 SBIT(P2IF, 0xE8, 0); // Port 2 Interrupt Flag
229 SBIT(USBIF, 0xE8, 0); // USB Interrupt Flag (same bit as P2IF)
230 SBIT(UTX0IF, 0xE8, 1); // USART0 TX Interrupt Flag
231 SBIT(UTX1IF, 0xE8, 2); // USART1 TX Interrupt Flag
232 SBIT(I2STXIF, 0xE8, 2); // I2S TX Interrupt Flag (same bit as UTX1FIF)
233 SBIT(P1IF, 0xE8, 3); // Port 1 Interrupt Flag
234 SBIT(WDTIF, 0xE8, 4); // Watchdog Timer Interrupt Flag
235 SFR(RFIF, 0xE9); // RF Interrupt Flags
236 SFR(T4CNT, 0xEA); // Timer 4 Counter
237 SFR(T4CTL, 0xEB); // Timer 4 Control
238 SFR(T4CCTL0, 0xEC); // Timer 4 Channel 0 Capture/Compare Control
239 SFR(T4CC0, 0xED); // Timer 4 Channel 0 Capture/Compare Value
240 SFR(T4CCTL1, 0xEE); // Timer 4 Channel 1 Capture/Compare Control
241 SFR(T4CC1, 0xEF); // Timer 4 Channel 1 Capture/Compare Value
242 SFR(B, 0xF0); // B Register
243 SBIT(B_0, 0xF0, 0); // Register B bit 0
244 SBIT(B_1, 0xF0, 1); // Register B bit 1
245 SBIT(B_2, 0xF0, 2); // Register B bit 2
246 SBIT(B_3, 0xF0, 3); // Register B bit 3
247 SBIT(B_4, 0xF0, 4); // Register B bit 4
248 SBIT(B_5, 0xF0, 5); // Register B bit 5
249 SBIT(B_6, 0xF0, 6); // Register B bit 6
250 SBIT(B_7, 0xF0, 7); // Register B bit 7
251 SFR(PERCFG, 0xF1); // Peripheral Control
252 SFR(ADCCFG, 0xF2); // ADC Input Configuration
253 SFR(P0SEL, 0xF3); // Port 0 Function Select
254 SFR(P1SEL, 0xF4); // Port 1 Function Select
255 SFR(P2SEL, 0xF5); // Port 2 Function Select
256 SFR(P1INP, 0xF6); // Port 1 Input Mode
257 SFR(P2INP, 0xF7); // Port 2 Input Mode
258 SFR(U1CSR, 0xF8); // USART 1 Control and Status
259 SBIT(ACTIVE, 0xF8, 0); // USART transmit/receive active status 0:idle 1:busy
260 SBIT(TX_BYTE, 0xF8, 1); // Transmit byte status 0:Byte not transmitted 1:Last byte transmitted
261 SBIT(RX_BYTE, 0xF8, 2); // Receive byte status 0:No byte received 1:Received byte ready
262 SBIT(ERR, 0xF8, 3); // UART parity error status 0:No error 1:parity error
263 SBIT(FE, 0xF8, 4); // UART framing error status 0:No error 1:incorrect stop bit level
264 SBIT(SLAVE, 0xF8, 5); // SPI master or slave mode select 0:master 1:slave
265 SBIT(RE, 0xF8, 6); // UART receiver enable 0:disabled 1:enabled
266 SBIT(MODE, 0xF8, 7); // USART mode select 0:SPI 1:UART
267 SFR(U1DBUF, 0xF9); // USART 1 Receive/Transmit Data Buffer
268 SFR(U1BAUD, 0xFA); // USART 1 Baud Rate Control
269 SFR(U1UCR, 0xFB); // USART 1 UART Control
270 SFR(U1GCR, 0xFC); // USART 1 Generic Control
271 SFR(P0DIR, 0xFD); // Port 0 Direction
272 SFR(P1DIR, 0xFE); // Port 1 Direction
273 SFR(P2DIR, 0xFF); // Port 2 Direction
275 // From table 68: xdata RF registers
277 SFRX(SYNC1, 0xDF00); // Sync word, high byte
278 SFRX(SYNC0, 0xDF01); // Sync word, low byte
279 SFRX(PKTLEN, 0xDF02); // Packet length
280 SFRX(PKTCTRL1, 0xDF03); // Packet automation control
281 SFRX(PKTCTRL0, 0xDF04); // Packet automation control
282 SFRX(ADDR, 0xDF05); // Device address
283 SFRX(CHANNR, 0xDF06); // Channel number
284 SFRX(FSCTRL1, 0xDF07); // Frequency synthesizer control
285 SFRX(FSCTRL0, 0xDF08); // Frequency synthesizer control
286 SFRX(FREQ2, 0xDF09); // Frequency control word, high byte
287 SFRX(FREQ1, 0xDF0A); // Frequency control word, middle byte
288 SFRX(FREQ0, 0xDF0B); // Frequency control word, low byte
289 SFRX(MDMCFG4, 0xDF0C); // Modem configuration
290 SFRX(MDMCFG3, 0xDF0D); // Modem configuration
291 SFRX(MDMCFG2, 0xDF0E); // Modem configuration
292 SFRX(MDMCFG1, 0xDF0F); // Modem configuration
293 SFRX(MDMCFG0, 0xDF10); // Modem configuration
294 SFRX(DEVIATN, 0xDF11); // Modem deviation setting
295 SFRX(MCSM2, 0xDF12); // Main Radio Control State Machine configuration
296 SFRX(MCSM1, 0xDF13); // Main Radio Control State Machine configuration
297 SFRX(MCSM0, 0xDF14); // Main Radio Control State Machine configuration
298 SFRX(FOCCFG, 0xDF15); // Frequency Offset Compensation configuration
299 SFRX(BSCFG, 0xDF16); // Bit Synchronization configuration
300 SFRX(AGCCTRL2, 0xDF17); // AGC control
301 SFRX(AGCCTRL1, 0xDF18); // AGC control
302 SFRX(AGCCTRL0, 0xDF19); // AGC control
303 SFRX(FREND1, 0xDF1A); // Front end RX configuration
304 SFRX(FREND0, 0xDF1B); // Front end TX configuration
305 SFRX(FSCAL3, 0xDF1C); // Frequency synthesizer calibration
306 SFRX(FSCAL2, 0xDF1D); // Frequency synthesizer calibration
307 SFRX(FSCAL1, 0xDF1E); // Frequency synthesizer calibration
308 SFRX(FSCAL0, 0xDF1F); // Frequency synthesizer calibration
309 SFRX(PA_TABLE7, 0xDF27); // PA output power setting
310 SFRX(PA_TABLE6, 0xDF28); // PA output power setting
311 SFRX(PA_TABLE5, 0xDF29); // PA output power setting
312 SFRX(PA_TABLE4, 0xDF2A); // PA output power setting
313 SFRX(PA_TABLE3, 0xDF2B); // PA output power setting
314 SFRX(PA_TABLE2, 0xDF2C); // PA output power setting
315 SFRX(PA_TABLE1, 0xDF2D); // PA output power setting
316 SFRX(PA_TABLE0, 0xDF2E); // PA output power setting
317 SFRX(IOCFG2, 0xDF2F); // GDO2 output pin configuration
318 SFRX(IOCFG1, 0xDF30); // GDO1 output pin configuration
319 SFRX(IOCFG0, 0xDF31); // GDO0 output pin configuration
320 SFRX(PARTNUM, 0xDF36); // Chip Identifier
321 SFRX(VERSION, 0xDF37); // Configuration
322 SFRX(FREQEST, 0xDF38); // Frequency Offset Estimate
323 SFRX(LQI, 0xDF39); // Link Quality Indicator
324 SFRX(RSSI, 0xDF3A); // Received Signal Strength Indication
325 SFRX(MARCSTATE, 0xDF3B); // Main Radio Control State
326 SFRX(PKTSTATUS, 0xDF3C); // Packet status
327 SFRX(VCO_VC_DAC, 0xDF3D); // PLL calibration current
331 SFRX(I2SCFG0, 0xDF40); // I2S Configuration Register 0
332 SFRX(I2SCFG1, 0xDF41); // I2S Configuration Register 1
333 SFRX(I2SDATL, 0xDF42); // I2S Data Low Byte
334 SFRX(I2SDATH, 0xDF43); // I2S Data High Byte
335 SFRX(I2SWCNT, 0xDF44); // I2S Word Count Register
336 SFRX(I2SSTAT, 0xDF45); // I2S Status Register
337 SFRX(I2SCLKF0, 0xDF46); // I2S Clock Configuration Register 0
338 SFRX(I2SCLKF1, 0xDF47); // I2S Clock Configuration Register 1
339 SFRX(I2SCLKF2, 0xDF48); // I2S Clock Configuration Register 2
341 // Common USB Registers
343 SFRX(USBADDR, 0xDE00); // Function Address
344 SFRX(USBPOW, 0xDE01); // Power/Control Register
345 SFRX(USBIIF, 0xDE02); // IN Endpoints and EP0 Interrupt Flags
346 SFRX(USBOIF, 0xDE04); // OUT Endpoints Interrupt Flags
347 SFRX(USBCIF, 0xDE06); // Common USB Interrupt Flags
348 SFRX(USBIIE, 0xDE07); // IN Endpoints and EP0 Interrupt Enable Mask
349 SFRX(USBOIE, 0xDE09); // Out Endpoints Interrupt Enable Mask
350 SFRX(USBCIE, 0xDE0B); // Common USB Interrupt Enable Mask
351 SFRX(USBFRML, 0xDE0C); // Current Frame Number (Low byte)
352 SFRX(USBFRMH, 0xDE0D); // Current Frame Number (High byte)
353 SFRX(USBINDEX, 0xDE0E); // Selects current endpoint.
355 // Indexed Endpoint Registers
357 SFRX(USBMAXI, 0xDE10); // Max. packet size for IN endpoint
358 SFRX(USBCS0, 0xDE11); // EP0 Control and Status (USBINDEX = 0)
359 SFRX(USBCSIL, 0xDE11); // IN EP{1-5} Control and Status Low
360 SFRX(USBCSIH, 0xDE12); // IN EP{1-5} Control and Status High
361 SFRX(USBMAXO, 0xDE13); // Max. packet size for OUT endpoint
362 SFRX(USBCSOL, 0xDE14); // OUT EP{1-5} Control and Status Low
363 SFRX(USBCSOH, 0xDE15); // OUT EP{1-5} Control and Status High
364 SFRX(USBCNT0, 0xDE16); // Number of received bytes in EP0 FIFO (USBINDEX = 0)
365 SFRX(USBCNTL, 0xDE16); // Number of bytes in OUT FIFO Low
366 SFRX(USBCNTH, 0xDE17); // Number of bytes in OUT FIFO High
368 // Endpoint FIFO Registers
370 SFRX(USBF0, 0xDE20); // Endpoint 0 FIFO
371 SFRX(USBF1, 0xDE22); // Endpoint 1 FIFO
372 SFRX(USBF2, 0xDE24); // Endpoint 2 FIFO
373 SFRX(USBF3, 0xDE26); // Endpoint 3 FIFO
374 SFRX(USBF4, 0xDE28); // Endpoint 4 FIFO
375 SFRX(USBF5, 0xDE2A); // Endpoint 5 FIFO
377 // SFRs also accesible through XDATA space
379 SFRX(X_U0CSR, 0xDF86); // USART 0 Control and Status
380 SFRX(X_P0IFG, 0xDF89); // Port 0 Interrupt Status Flag
381 SFRX(X_P1IFG, 0xDF8A); // Port 1 Interrupt Status Flag
382 SFRX(X_P2IFG, 0xDF8B); // Port 2 Interrupt Status Flag
383 SFRX(X_PICTL, 0xDF8C); // Port Pins Interrupt Mask and Edge
384 SFRX(X_P1IEN, 0xDF8D); // Port 1 Interrupt Mask
385 SFRX(X_P0INP, 0xDF8F); // Port 0 Input Mode
386 SFRX(X_RFIM, 0xDF91); // RF Interrupt Mask
387 SFRX(X_MPAGE, 0xDF93); // Memory Page Select
388 SFRX(X_T2CT, 0xDF9C); // Timer 2 Control
389 SFRX(X_T2PR, 0xDF9D); // Timer 2 Prescaler
390 SFRX(X_T2CTL, 0xDF9E); // Timer 2 Control
391 SFRX(X_WORIRQ, 0xDFA1); // Timer Sleep Timer Interrupts
392 SFRX(X_WORCTL, 0xDFA2); // Sleep Timer Control
393 SFRX(X_WOREVT0, 0xDFA3); // Timer Sleep Timer Event 0 Timeout Low Byte
394 SFRX(X_WOREVT1, 0xDFA4); // Timer Sleep Timer Event 0 Timeout High Byte
395 SFRX(X_WORTIME0, 0xDFA5); // Sleep Timer Value 0
396 SFRX(X_WORTIME1, 0xDFA6); // Sleep Timer Value 1
397 SFRX(X_FWT, 0xDFAB); // Flash Write Timing
398 SFRX(X_FADDRL, 0xDFAC); // Flash Address Low
399 SFRX(X_FADDRH, 0xDFAD); // Flash Address High
400 SFRX(X_FCTL, 0xDFAE); // Flash Control
401 SFRX(X_FWDATA, 0xDFAF); // Flash Write Data
402 SFRX(X_ENCDI, 0xDFB1); // Encryption/Decryption Input Data
403 SFRX(X_ENCDO, 0xDFB2); // Encryption/Decryption Output Data
404 SFRX(X_ENCCS, 0xDFB3); // Encryption/Decryption Control and Status
405 SFRX(X_ADCCON1, 0xDFB4); // ADC Control 1
406 SFRX(X_ADCCON2, 0xDFB5); // ADC Control 2
407 SFRX(X_ADCCON3, 0xDFB6); // ADC Control 3
408 SFRX(X_ADCL, 0xDFBA); // ADC Data Low
409 SFRX(X_ADCH, 0xDFBB); // ADC Data High
410 SFRX(X_RNDL, 0xDFBC); // Random Number Generator Data Low
411 SFRX(X_RNDH, 0xDFBD); // Random Number Generator Data High
412 SFRX(X_SLEEP, 0xDFBE); // Flash Write Timing
413 SFRX(X_U0DBUF, 0xDFC1); // USART 0 Receive/Transmit Data Buffer
414 SFRX(X_U0BAUD, 0xDFC2); // USART 0 Baud Rate Control
415 SFRX(X_U0UCR, 0xDFC4); // USART 0 UART Control
416 SFRX(X_U0GCR, 0xDFC5); // USART 0 Generic Control
417 SFRX(X_CLKCON, 0xDFC6); // Clock Control
418 SFRX(X_MEMCTR, 0xDFC7); // Memory System Control
419 SFRX(X_WDCTL, 0xDFC9); // Watchdog Timer Control
420 SFRX(X_T3CNT, 0xDFCA); // Timer 3 Counter
421 SFRX(X_T3CTL, 0xDFCB); // Timer 3 Control
422 SFRX(X_T3CCTL0, 0xDFCC); // Timer 3 Channel 0 Capture/Compare Control
423 SFRX(X_T3CC0, 0xDFCD); // Timer 3 Channel 0 Capture/Compare Value
424 SFRX(X_T3CCTL1, 0xDFCE); // Timer 3 Channel 1 Capture/Compare Control
425 SFRX(X_T3CC1, 0xDFCF); // Timer 3 Channel 1 Capture/Compare Value
426 SFRX(X_DMAIRQ, 0xDFD1); // DMA Interrupt Flag
427 SFRX(X_DMA1CFGL, 0xDFD2); // DMA Channel 1-4 Configuration Address Low Byte
428 SFRX(X_DMA1CFGH, 0xDFD3); // DMA Channel 1-4 Configuration Address High Byte
429 SFRX(X_DMA0CFGL, 0xDFD4); // DMA Channel 0 Configuration Address Low Byte
430 SFRX(X_DMA0CFGH, 0xDFD5); // DMA Channel 0 Configuration Address High Byte
431 SFRX(X_DMAARM, 0xDFD6); // DMA Channel Arm
432 SFRX(X_DMAREQ, 0xDFD7); // DMA Channel Start Request and Status
433 SFRX(X_TIMIF, 0xDFD8); // Timers 1/3/4 Joint Interrupt Mask/Flags
434 SFRX(X_RFD, 0xDFD9); // RF Data
435 SFRX(X_T1CC0L, 0xDFDA); // Timer 1 Channel 0 Capture/Compare Value Low
436 SFRX(X_T1CC0H, 0xDFDB); // Timer 1 Channel 0 Capture/Compare Value High
437 SFRX(X_T1CC1L, 0xDFDC); // Timer 1 Channel 1 Capture/Compare Value Low
438 SFRX(X_T1CC1H, 0xDFDD); // Timer 1 Channel 1 Capture/Compare Value High
439 SFRX(X_T1CC2L, 0xDFDE); // Timer 1 Channel 2 Capture/Compare Value Low
440 SFRX(X_T1CC2H, 0xDFDF); // Timer 1 Channel 2 Capture/Compare Value High
441 SFRX(X_RFST, 0xDFE1); // RF Strobe Commands
442 SFRX(X_T1CNTL, 0xDFE2); // Timer 1 Counter Low
443 SFRX(X_T1CNTH, 0xDFE3); // Timer 1 Counter High
444 SFRX(X_T1CTL, 0xDFE4); // Timer 1 Control and Status
445 SFRX(X_T1CCTL0, 0xDFE5); // Timer 1 Channel 0 Capture/Compare Control
446 SFRX(X_T1CCTL1, 0xDFE6); // Timer 1 Channel 1 Capture/Compare Control
447 SFRX(X_T1CCTL2, 0xDFE7); // Timer 1 Channel 2 Capture/Compare Control
448 SFRX(X_RFIF, 0xDFE9); // RF Interrupt flags
449 SFRX(X_T4CNT, 0xDFEA); // Timer 4 Counter
450 SFRX(X_T4CTL, 0xDFEB); // Timer 4 Control
451 SFRX(X_T4CCTL0, 0xDFEC); // Timer 4 Channel 0 Capture/Compare Control
452 SFRX(X_T4CC0, 0xDFED); // Timer 4 Channel 0 Capture/Compare Value
453 SFRX(X_T4CCTL1, 0xDFEE); // Timer 4 Channel 1 Capture/Compare Control
454 SFRX(X_T4CC1, 0xDFEF); // Timer 4 Channel 1 Capture/Compare Value
455 SFRX(X_PERCFG, 0xDFF1); // Peripheral I/O Control
456 SFRX(X_ADCCFG, 0xDFF2); // ADC Input Configuration
457 SFRX(X_P0SEL, 0xDFF3); // Port 0 Function Select
458 SFRX(X_P1SEL, 0xDFF4); // Port 1 Function Select
459 SFRX(X_P2SEL, 0xDFF5); // Port 2 Function Select
460 SFRX(X_P1INP, 0xDFF6); // Port 1 Input Mode
461 SFRX(X_P2INP, 0xDFF7); // Port 2 Input Mode
462 SFRX(X_U1CSR, 0xDFF8); // USART 1 Control and Status
463 SFRX(X_U1DBUF, 0xDFF9); // USART 1 Receive/Transmit Data Buffer
464 SFRX(X_U1BAUD, 0xDFFA); // USART 1 Baud Rate Control
465 SFRX(X_U1UCR, 0xDFFB); // USART 1 UART Control
466 SFRX(X_U1GCR, 0xDFFC); // USART 1 Generic Control
467 SFRX(X_P0DIR, 0xDFFD); // Port 0 Direction
468 SFRX(X_P1DIR, 0xDFFE); // Port 1 Direction
469 SFRX(X_P2DIR, 0xDFFF); // Port 2 Direction
471 #endif //REG_CC2510FX_H
projects / fw / sdcc / blob