1 /*-------------------------------------------------------------------------
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2 Register Declarations for Chipcon CC2430
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4 Written By - Jesus Calvino-Fraga / jesusc at ece.ubc.ca (December 2006)
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5 (Based on CC2430 PRELIMINARY Data Sheet (rev. 1.03) SWRS036A)
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7 This library is free software; you can redistribute it and/or
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8 modify it under the terms of the GNU Lesser General Public
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9 License as published by the Free Software Foundation; either
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10 version 2.1 of the License, or (at your option) any later version.
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12 This library is distributed in the hope that it will be useful,
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13 but WITHOUT ANY WARRANTY; without even the implied warranty of
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14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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15 Lesser General Public License for more details.
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17 You should have received a copy of the GNU Lesser General Public
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18 License along with this library; if not, write to the Free Software
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19 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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21 In other words, you are welcome to use, share and improve this program.
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22 You are forbidden to forbid anyone else to use, share and improve
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23 what you give them. Help stamp out software-hoarding!
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24 -------------------------------------------------------------------------*/
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26 #ifndef REG_CC2430_H
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27 #define REG_CC2430_H
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29 #include <compiler.h>
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31 // Interrupt Vectors
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33 #define RFERR_VECTOR 0 // RF TX FIFO underflow and RX FIFO overflow.
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34 #define ADC_VECTOR 1 // ADC end of conversion
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35 #define URX0_VECTOR 2 // USART0 RX complete
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36 #define URX1_VECTOR 3 // USART1 RX complete
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37 #define ENC_VECTOR 4 // AES encryption/decryption complete
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38 #define ST_VECTOR 5 // Sleep Timer compare
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39 #define P2INT_VECTOR 6 // Port 2 inputs
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40 #define UTX0_VECTOR 7 // USART0 TX complete
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41 #define DMA_VECTOR 8 // DMA transfer complete
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42 #define T1_VECTOR 9 // Timer 1 (16-bit) capture/compare/overflow
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43 #define T2_VECTOR 10 // Timer 2 (MAC Timer)
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44 #define T3_VECTOR 11 // Timer 3 (8-bit) capture/compare/overflow
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45 #define T4_VECTOR 12 // Timer 4 (8-bit) capture/compare/overflow
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46 #define P0INT_VECTOR 13 // Port 0 inputs
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47 #define UTX1_VECTOR 14 // USART1 TX complete
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48 #define P1INT_VECTOR 15 // Port 1 inputs
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49 #define RF_VECTOR 16 // RF general interrupts
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50 #define WDT_VECTOR 17 // Watchdog overflow in timer mode
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52 // SFR Registers and BITs
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54 SFR(P0, 0x80); // Port 0
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55 SBIT(P0_0, 0x80, 0); // Port 0 bit 0
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56 SBIT(P0_1, 0x80, 1); // Port 0 bit 1
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57 SBIT(P0_2, 0x80, 2); // Port 0 bit 2
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58 SBIT(P0_3, 0x80, 3); // Port 0 bit 3
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59 SBIT(P0_4, 0x80, 4); // Port 0 bit 4
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60 SBIT(P0_5, 0x80, 5); // Port 0 bit 5
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61 SBIT(P0_6, 0x80, 6); // Port 0 bit 6
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62 SBIT(P0_7, 0x80, 7); // Port 0 bit 7
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63 SFR(SP, 0x81); // Stack Pointer
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64 SFR(DPL0, 0x82); // Data Pointer 0 Low Byte
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65 SFR(DPH0, 0x83); // Data Pointer 0 High Byte
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66 SFR(DPL1, 0x84); // Data Pointer 1 Low Byte
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67 SFR(DPH1, 0x85); // Data Pointer 1 High Byte
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68 SFR(U0CSR, 0x86); // USART 0 Control and Status
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69 SFR(PCON, 0x87); // Power Mode Control
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70 SFR(TCON, 0x88); // Interrupt Flags
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71 SBIT(IT0, 0x88, 0); // reserved (must always be set to 1)
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72 SBIT(RFERRIF, 0x88, 1); // RFERR
\96 RF TX/RX FIFO interrupt flag
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73 SBIT(IT1, 0x88, 2); // reserved (must always be set to 1)
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74 SBIT(URX0IF, 0x88, 3); // USART0 RX Interrupt Flag
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75 SBIT(ADCIF, 0x88, 5); // ADC Interrupt Flag
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76 SBIT(URX1IF, 0x88, 7); // USART1 RX Interrupt Flag
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77 SFR(P0IFG, 0x89); // Port 0 Interrupt Status Flag
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78 SFR(P1IFG, 0x8A); // Port 1 Interrupt Status Flag
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79 SFR(P2IFG, 0x8B); // Port 2 Interrupt Status Flag
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80 SFR(PICTL, 0x8C); // Port Interrupt Control
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81 SFR(P1IEN, 0x8D); // Port 1 Interrupt Mask
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82 SFR(P0INP, 0x8F); // Port 0 Input Mode
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83 SFR(P1, 0x90); // Port 1
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84 SBIT(P1_0, 0x90, 0); // Port 1 bit 0
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85 SBIT(P1_1, 0x90, 1); // Port 1 bit 1
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86 SBIT(P1_2, 0x90, 2); // Port 1 bit 2
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87 SBIT(P1_3, 0x90, 3); // Port 1 bit 3
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88 SBIT(P1_4, 0x90, 4); // Port 1 bit 4
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89 SBIT(P1_5, 0x90, 5); // Port 1 bit 5
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90 SBIT(P1_6, 0x90, 6); // Port 1 bit 6
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91 SBIT(P1_7, 0x90, 7); // Port 1 bit 7
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92 SFR(RFIM, 0x91); // RF Interrupt Mask
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93 SFR(DPS, 0x92); // Data Pointer Select
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94 SFR(MPAGE, 0x93); // Memory Page Select
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95 SFR(_XPAGE, 0x93); // Memory Page Select under the name SDCC needs it
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96 SFR(T2CMP, 0x94); // Timer 2 Compare Value
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97 SFR(ST0, 0x95); // Sleep Timer 0
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98 SFR(ST1, 0x96); // Sleep Timer 1
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99 SFR(ST2, 0x97); // Sleep Timer 2
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100 SFR(S0CON, 0x98); // Interrupt Flags 2
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101 SBIT(ENCIF_0, 0x98, 0); // AES Interrupt Flag 0
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102 SBIT(ENCIF_1, 0x98, 1); // AES Interrupt Flag 1
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103 SFR(IEN2, 0x9A); // Interrupt Enable 2
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104 SFR(S1CON, 0x9B); // Interrupt Flags 3
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105 SFR(T2PEROF0, 0x9C); // Timer 2 Overflow Capture/Compare 0
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106 SFR(T2PEROF1, 0x9D); // Timer 2 Overflow Capture/Compare 1
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107 SFR(T2PEROF2, 0x9E); // Timer 2 Overflow Capture/Compare 2
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108 SFR(P2, 0xA0); // Port 2
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109 SBIT(P2_0, 0xA0, 0); // Port 2 bit 0
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110 SBIT(P2_1, 0xA0, 1); // Port 2 bit 1
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111 SBIT(P2_2, 0xA0, 2); // Port 2 bit 2
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112 SBIT(P2_3, 0xA0, 3); // Port 2 bit 3
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113 SBIT(P2_4, 0xA0, 4); // Port 2 bit 4
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114 SBIT(P2_5, 0xA0, 5); // Port 2 bit 5
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115 SBIT(P2_6, 0xA0, 6); // Port 2 bit 6
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116 SBIT(P2_7, 0xA0, 7); // Port 2 bit 7
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117 SFR(T2OF0, 0xA1); // Timer 2 Overflow Count 0
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118 SFR(T2OF1, 0xA2); // Timer 2 Overflow Count 1
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119 SFR(T2OF2, 0xA3); // Timer 2 Overflow Count 2
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120 SFR(T2CAPLPL, 0xA4); // Timer 2 Period Low Byte
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121 SFR(T2CAPHPH, 0xA5); // Timer 2 Period High Byte
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122 SFR(T2TLD, 0xA6); // Timer 2 Timer Value Low Byte
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123 SFR(T2THD, 0xA7); // Timer 2 Timer Value High Byte
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124 SFR(IEN0, 0xA8); // Interrupt Enable 0
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125 SBIT(RFERRIE, 0xA8, 0); // RF TX/RX FIFO interrupt enable
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126 SBIT(ADCIE, 0xA8, 1); // ADC Interrupt Enable
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127 SBIT(URX0IE, 0xA8, 2); // USART0 RX Interrupt Enable
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128 SBIT(URX1IE, 0xA8, 3); // USART1 RX Interrupt Enable
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129 SBIT(ENCIE, 0xA8, 4); // AES Encryption/Decryption Interrupt Enable
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130 SBIT(STIE, 0xA8, 5); // Sleep Timer Interrupt Enable
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131 SBIT(EA, 0xA8, 7); // Global Interrupt Enable
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132 SFR(IP0, 0xA9); // Interrupt Priority 0
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133 SFR(FWT, 0xAB); // Flash Write Timing
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134 SFR(FADDRL, 0xAC); // Flash Address Low Byte
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135 SFR(FADDRH, 0xAD); // Flash Address High Byte
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136 SFR(FCTL, 0xAE); // Flash Control
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137 SFR(FWDATA, 0xAF); // Flash Write Data
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138 SFR(ENCDI, 0xB1); // Encryption Input Data
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139 SFR(ENCDO, 0xB2); // Encryption Output Data
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140 SFR(ENCCS, 0xB3); // Encryption Control and Status
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141 SFR(ADCCON1, 0xB4); // ADC Control 1
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142 SFR(ADCCON2, 0xB5); // ADC Control 2
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143 SFR(ADCCON3, 0xB6); // ADC Control 3
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144 SFR(IEN1, 0xB8); // Interrupt Enable 1
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145 SBIT(DMAIE, 0xB8, 0); // DMA Transfer Interrupt Enable
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146 SBIT(T1IE, 0xB8, 1); // Timer 1 Interrupt Enable
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147 SBIT(T2IE, 0xB8, 2); // Timer 2 Interrupt Enable
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148 SBIT(T3IE, 0xB8, 3); // Timer 3 Interrupt Enable
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149 SBIT(T4IE, 0xB8, 4); // Timer 4 Interrupt Enable
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150 SBIT(P0IE, 0xB8, 5); // Port 0 Interrupt Enable
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151 SFR(IP1, 0xB9); // Interrupt Priority 1
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152 SFR(ADCL, 0xBA); // ADC Data Low
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153 SFR(ADCH, 0xBB); // ADC Data High
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154 SFR(RNDL, 0xBC); // Random Number Generator Data Low Byte
\r
155 SFR(RNDH, 0xBD); // Random Number Generator Data High Byte
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156 SFR(SLEEP, 0xBE); // Sleep Mode Control
\r
157 SFR(IRCON, 0xC0); // Interrupt Flags 4
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158 SBIT(DMAIF, 0xC0, 0); // DMA Complete Interrupt Flag
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159 SBIT(T1IF, 0xC0, 1); // Timer 1 Interrupt Flag
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160 SBIT(T2IF, 0xC0, 2); // Timer 2 Interrupt Flag
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161 SBIT(T3IF, 0xC0, 3); // Timer 3 Interrupt Flag
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162 SBIT(T4IF, 0xC0, 4); // Timer 4 Interrupt Flag
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163 SBIT(P0IF, 0xC0, 5); // Port 0 Interrupt Flag
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164 SBIT(STIF, 0xC0, 7); // Sleep Timer Interrupt Flag
\r
165 SFR(U0DBUF, 0xC1); // USART 0 Receive/Transmit Data Buffer
\r
166 SFR(U0BAUD, 0xC2); // USART 0 Baud Rate Control
\r
167 SFR(T2CNF, 0xC3); // Timer 2 Configuration
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168 SFR(U0UCR, 0xC4); // USART 0 UART Control
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169 SFR(U0GCR, 0xC5); // USART 0 Generic Control
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170 SFR(CLKCON, 0xC6); // Clock Control
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171 SFR(MEMCTR, 0xC7); // Memory Arbiter Control
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172 SFR(WDCTL, 0xC9); // Watchdog Timer Control
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173 SFR(T3CNT, 0xCA); // Timer 3 Counter
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174 SFR(T3CTL, 0xCB); // Timer 3 Control
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175 SFR(T3CCTL0, 0xCC); // Timer 3 Channel 0 Capture/Compare Control
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176 SFR(T3CC0, 0xCD); // Timer 3 Channel 0 Capture/Compare Value
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177 SFR(T3CCTL1, 0xCE); // Timer 3 Channel 1 Capture/Compare Control
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178 SFR(T3CC1, 0xCF); // Timer 3 Channel 1 Capture/Compare Value
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179 SFR(PSW, 0xD0); // Program Status Word
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180 SBIT(P, 0xD0, 0); // Parity Flag
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181 SBIT(F1, 0xD0, 1); // User-Defined Flag
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182 SBIT(OV, 0xD0, 2); // Overflow Flag
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183 SBIT(RS0, 0xD0, 3); // Register Bank Select 0
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184 SBIT(RS1, 0xD0, 4); // Register Bank Select 1
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185 SBIT(F0, 0xD0, 5); // User-Defined Flag
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186 SBIT(AC, 0xD0, 6); // Auxiliary Carry Flag
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187 SBIT(CY, 0xD0, 7); // Carry Flag
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188 SFR(DMAIRQ, 0xD1); // DMA Interrupt Flag
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189 SFR(DMA1CFGL, 0xD2); // DMA Channel 1-4 Configuration Address Low Byte
\r
190 SFR(DMA1CFGH, 0xD3); // DMA Channel 1-4 Configuration Address High Byte
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191 SFR(DMA0CFGL, 0xD4); // DMA Channel 0 Configuration Address Low Byte
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192 SFR(DMA0CFGH, 0xD5); // DMA Channel 0 Configuration Address High Byte
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193 SFR(DMAARM, 0xD6); // DMA Channel Arm
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194 SFR(DMAREQ, 0xD7); // DMA Channel Start Request and Status
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195 SFR(TIMIF, 0xD8); // Timers 1/3/4 Interrupt Mask/Flag
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196 SBIT(T3OVFIF, 0xD8, 0); // Timer 3 overflow interrupt flag 0:no pending 1:pending
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197 SBIT(T3CH0IF, 0xD8, 1); // Timer 3 channel 0 interrupt flag 0:no pending 1:pending
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198 SBIT(T3CH1IF, 0xD8, 2); // Timer 3 channel 1 interrupt flag 0:no pending 1:pending
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199 SBIT(T4OVFIF, 0xD8, 3); // Timer 4 overflow interrupt flag 0:no pending 1:pending
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200 SBIT(T4CH0IF, 0xD8, 4); // Timer 4 channel 0 interrupt flag 0:no pending 1:pending
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201 SBIT(T4CH1IF, 0xD8, 5); // Timer 4 channel 1 interrupt flag 0:no pending 1:pending
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202 SBIT(OVFIM, 0xD8, 6); // Timer 1 overflow interrupt mask
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203 SFR(RFD, 0xD9); // RF Data
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204 SFR(T1CC0L, 0xDA); // Timer 1 Channel 0 Capture/Compare Value Low
\r
205 SFR(T1CC0H, 0xDB); // Timer 1 Channel 0 Capture/Compare Value High
\r
206 SFR(T1CC1L, 0xDC); // Timer 1 Channel 1 Capture/Compare Value Low
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207 SFR(T1CC1H, 0xDD); // Timer 1 Channel 1 Capture/Compare Value High
\r
208 SFR(T1CC2L, 0xDE); // Timer 1 Channel 2 Capture/Compare Value Low
\r
209 SFR(T1CC2H, 0xDF); // Timer 1 Channel 2 Capture/Compare Value High
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210 SFR(ACC, 0xE0); // Accumulator
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211 SBIT(ACC_0, 0xE0, 0); // Accumulator bit 0
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212 SBIT(ACC_1, 0xE0, 1); // Accumulator bit 1
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213 SBIT(ACC_2, 0xE0, 2); // Accumulator bit 2
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214 SBIT(ACC_3, 0xE0, 3); // Accumulator bit 3
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215 SBIT(ACC_4, 0xE0, 4); // Accumulator bit 4
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216 SBIT(ACC_5, 0xE0, 5); // Accumulator bit 5
\r
217 SBIT(ACC_6, 0xE0, 6); // Accumulator bit 6
\r
218 SBIT(ACC_7, 0xE0, 7); // Accumulator bit 7
\r
219 SFR(RFST, 0xE1); // RF CSMA-CA / Strobe Processor
\r
220 SFR(T1CNTL, 0xE2); // Timer 1 Counter Low
\r
221 SFR(T1CNTH, 0xE3); // Timer 1 Counter High
\r
222 SFR(T1CTL, 0xE4); // Timer 1 Control and Status
\r
223 SFR(T1CCTL0, 0xE5); // Timer 1 Channel 0 Capture/Compare Control
\r
224 SFR(T1CCTL1, 0xE6); // Timer 1 Channel 1 Capture/Compare Control
\r
225 SFR(T1CCTL2, 0xE7); // Timer 1 Channel 2 Capture/Compare Control
\r
226 SFR(IRCON2, 0xE8); // Interrupt Flags 5
\r
227 SBIT(P2IF, 0xE8, 0); // Port 2 Interrupt Flag
\r
228 SBIT(UTX0IF, 0xE8, 1); // USART0 TX Interrupt Flag
\r
229 SBIT(UTX1IF, 0xE8, 2); // USART1 TX Interrupt Flag
\r
230 SBIT(P1IF, 0xE8, 3); // Port 1 Interrupt Flag
\r
231 SBIT(WDTIF, 0xE8, 4); // Watchdog Timer Interrupt Flag
\r
232 SFR(RFIF, 0xE9); // RF Interrupt Flags
\r
233 SFR(T4CNT, 0xEA); // Timer 4 Counter
\r
234 SFR(T4CTL, 0xEB); // Timer 4 Control
\r
235 SFR(T4CCTL0, 0xEC); // Timer 4 Channel 0 Capture/Compare Control
\r
236 SFR(T4CC0, 0xED); // Timer 4 Channel 0 Capture/Compare Value
\r
237 SFR(T4CCTL1, 0xEE); // Timer 4 Channel 1 Capture/Compare Control
\r
238 SFR(T4CC1, 0xEF); // Timer 4 Channel 1 Capture/Compare Value
\r
239 SFR(B, 0xF0); // B Register
\r
240 SBIT(B_0, 0xF0, 0); // Register B bit 0
\r
241 SBIT(B_1, 0xF0, 1); // Register B bit 1
\r
242 SBIT(B_2, 0xF0, 2); // Register B bit 2
\r
243 SBIT(B_3, 0xF0, 3); // Register B bit 3
\r
244 SBIT(B_4, 0xF0, 4); // Register B bit 4
\r
245 SBIT(B_5, 0xF0, 5); // Register B bit 5
\r
246 SBIT(B_6, 0xF0, 6); // Register B bit 6
\r
247 SBIT(B_7, 0xF0, 7); // Register B bit 7
\r
248 SFR(PERCFG, 0xF1); // Peripheral Control
\r
249 SFR(ADCCFG, 0xF2); // ADC Input Configuration
\r
250 SFR(P0SEL, 0xF3); // Port 0 Function Select
\r
251 SFR(P1SEL, 0xF4); // Port 1 Function Select
\r
252 SFR(P2SEL, 0xF5); // Port 2 Function Select
\r
253 SFR(P1INP, 0xF6); // Port 1 Input Mode
\r
254 SFR(P2INP, 0xF7); // Port 2 Input Mode
\r
255 SFR(U1CSR, 0xF8); // USART 1 Control and Status
\r
256 SBIT(ACTIVE, 0xF8, 0); // USART transmit/receive active status 0:idle 1:busy
\r
257 SBIT(TX_BYTE, 0xF8, 1); // Transmit byte status 0:Byte not transmitted 1:Last byte transmitted
\r
258 SBIT(RX_BYTE, 0xF8, 2); // Receive byte status 0:No byte received 1:Received byte ready
\r
259 SBIT(ERR, 0xF8, 3); // UART parity error status 0:No error 1:parity error
\r
260 SBIT(FE, 0xF8, 4); // UART framing error status 0:No error 1:incorrect stop bit level
\r
261 SBIT(SLAVE, 0xF8, 5); // SPI master or slave mode select 0:master 1:slave
\r
262 SBIT(RE, 0xF8, 6); // UART receiver enable 0:disabled 1:enabled
\r
263 SBIT(MODE, 0xF8, 7); // USART mode select 0:SPI 1:UART
\r
264 SFR(U1DBUF, 0xF9); // USART 1 Receive/Transmit Data Buffer
\r
265 SFR(U1BAUD, 0xFA); // USART 1 Baud Rate Control
\r
266 SFR(U1UCR, 0xFB); // USART 1 UART Control
\r
267 SFR(U1GCR, 0xFC); // USART 1 Generic Control
\r
268 SFR(P0DIR, 0xFD); // Port 0 Direction
\r
269 SFR(P1DIR, 0xFE); // Port 1 Direction
\r
270 SFR(P2DIR, 0xFF); // Port 2 Direction
\r
272 // From Table 45 : Overview of RF registers
\r
274 SFRX(MDMCTRL0H, 0xDF02); // Modem Control 0, high
\r
275 SFRX(MDMCTRL0L, 0xDF03); // Modem Control 0, low
\r
276 SFRX(MDMCTRL1H, 0xDF04); // Modem Control 1, high
\r
277 SFRX(MDMCTRL1L, 0xDF05); // Modem Control 1, low
\r
278 SFRX(RSSIH, 0xDF06); // RSSI and CCA Status and Control, high
\r
279 SFRX(RSSIL, 0xDF07); // RSSI and CCA Status and Control, low
\r
280 SFRX(SYNCWORDH, 0xDF08); // Synchronisation Word Control, high
\r
281 SFRX(SYNCWORDL, 0xDF09); // Synchronisation Word Control, low
\r
282 SFRX(TXCTRLH, 0xDF0A); // Transmit Control, high
\r
283 SFRX(TXCTRLL, 0xDF0B); // Transmit Control, low
\r
284 SFRX(RXCTRL0H, 0xDF0C); // Receive Control 0, high
\r
285 SFRX(RXCTRL0L, 0xDF0D); // Receive Control 0, low
\r
286 SFRX(RXCTRL1H, 0xDF0E); // Receive Control 1, high
\r
287 SFRX(RXCTRL1L, 0xDF0F); // Receive Control 1, low
\r
288 SFRX(FSCTRLH, 0xDF10); // Frequency Synthesizer Control and Status, high
\r
289 SFRX(FSCTRLL, 0xDF11); // Frequency Synthesizer Control and Status, low
\r
290 SFRX(CSPX, 0xDF12); // CSP X Data
\r
291 SFRX(CSPY, 0xDF13); // CSP Y Data
\r
292 SFRX(CSPZ, 0xDF14); // CSP Z Data
\r
293 SFRX(CSPCTRL, 0xDF15); // CSP Control
\r
294 SFRX(CSPT, 0xDF16); // CSP T Data
\r
295 SFRX(RFPWR, 0xDF17); // RF Power Control
\r
296 SFRX(FSMTCH, 0xDF20); // Finite State Machine Time Constants, high
\r
297 SFRX(FSMTCL, 0xDF21); // Finite State Machine Time Constants, low
\r
298 SFRX(MANANDH, 0xDF22); // Manual AND Override, high
\r
299 SFRX(MANANDL, 0xDF23); // Manual AND Override, low
\r
300 SFRX(MANORH, 0xDF24); // Manual OR Override, high
\r
301 SFRX(MANORL, 0xDF25); // Manual OR Override, low
\r
302 SFRX(AGCCTRLH, 0xDF26); // AGC Control, high
\r
303 SFRX(AGCCTRLL, 0xDF27); // AGC Control, low
\r
304 SFRX(FSMSTATE, 0xDF39); // Finite State Machine State Status
\r
305 SFRX(ADCTSTH, 0xDF3A); // ADC Test, high
\r
306 SFRX(ADCTSTL, 0xDF3B); // ADC Test, low
\r
307 SFRX(DACTSTH, 0xDF3C); // DAC Test, high
\r
308 SFRX(DACTSTL, 0xDF3D); // DAC Test, low
\r
309 SFRX(IEEE_ADDR0, 0xDF43); // IEEE Address 0
\r
310 SFRX(IEEE_ADDR1, 0xDF44); // IEEE Address 1
\r
311 SFRX(IEEE_ADDR2, 0xDF45); // IEEE Address 2
\r
312 SFRX(IEEE_ADDR3, 0xDF46); // IEEE Address 3
\r
313 SFRX(IEEE_ADDR4, 0xDF47); // IEEE Address 4
\r
314 SFRX(IEEE_ADDR5, 0xDF48); // IEEE Address 5
\r
315 SFRX(IEEE_ADDR6, 0xDF49); // IEEE Address 6
\r
316 SFRX(IEEE_ADDR7, 0xDF4A); // IEEE Address 7
\r
317 SFRX(PANIDH, 0xDF4B); // PAN Identifier, high
\r
318 SFRX(PANIDL, 0xDF4C); // PAN Identifier, low
\r
319 SFRX(SHORTADDRH, 0xDF4D); // Short Address, high
\r
320 SFRX(SHORTADDRL, 0xDF4E); // Short Address, low
\r
321 SFRX(IOCFG0, 0xDF4F); // I/O Configuration 0
\r
322 SFRX(IOCFG1, 0xDF50); // I/O Configuration 1
\r
323 SFRX(IOCFG2, 0xDF51); // I/O Configuration 2
\r
324 SFRX(IOCFG3, 0xDF52); // I/O Configuration 3
\r
325 SFRX(RXFIFOCNT, 0xDF53); // RX FIFO Count
\r
326 SFRX(FSMTC1, 0xDF54); // Finite State Machine Control
\r
327 SFRX(CHVER, 0xDF60); // Chip Version
\r
328 SFRX(CHIPID, 0xDF61); // Chip Identification
\r
329 SFRX(RFSTATUS, 0xDF62); // RF Status
\r
331 // SFRs also accesible through XDATA space
\r
333 SFRX(X_U0CSR, 0xDF86); // USART 0 Control and Status
\r
334 SFRX(X_P0IFG, 0xDF89); // Port 0 Interrupt Status Flag
\r
335 SFRX(X_P1IFG, 0xDF8A); // Port 1 Interrupt Status Flag
\r
336 SFRX(X_P2IFG, 0xDF8B); // Port 2 Interrupt Status Flag
\r
337 SFRX(X_PICTL, 0xDF8C); // Port Interrupt Control
\r
338 SFRX(X_P1IEN, 0xDF8D); // Port 1 Interrupt Mask
\r
339 SFRX(X_P0INP, 0xDF8F); // Port 0 Input Mode
\r
340 SFRX(X_RFIM, 0xDF91); // RF Interrupt Mask
\r
341 SFRX(X_MPAGE, 0xDF93); // Memory Page Select
\r
342 SFRX(X_T2CMP, 0xDF94); // Timer 2 Compare Value
\r
343 SFRX(X_ST0, 0xDF95); // Sleep Timer 0
\r
344 SFRX(X_ST1, 0xDF96); // Sleep Timer 1
\r
345 SFRX(X_ST2, 0xDF97); // Sleep Timer 2
\r
346 SFRX(X_T2PEROF0, 0xDF9C); // Timer 2 Overflow Capture/Compare 0
\r
347 SFRX(X_T2PEROF1, 0xDF9D); // Timer 2 Overflow Capture/Compare 1
\r
348 SFRX(X_T2PEROF2, 0xDF9E); // Timer 2 Overflow Capture/Compare 2
\r
349 SFRX(X_T2OF0, 0xDFA1); // Timer 2 Overflow Count 0
\r
350 SFRX(X_T2OF1, 0xDFA2); // Timer 2 Overflow Count 1
\r
351 SFRX(X_T2OF2, 0xDFA3); // Timer 2 Overflow Count 2
\r
352 SFRX(X_T2CAPLPL, 0xDFA4); // Timer 2 Period Low Byte
\r
353 SFRX(X_T2CAPHPH, 0xDFA5); // Timer 2 Period High Byte
\r
354 SFRX(X_T2TLD, 0xDFA6); // Timer 2 Timer Value Low Byte
\r
355 SFRX(X_T2THD, 0xDFA7); // Timer 2 Timer Value High Byte
\r
356 SFRX(X_FWT, 0xDFAB); // Flash Write Timing
\r
357 SFRX(X_FADDRL, 0xDFAC); // Flash Address Low Byte
\r
358 SFRX(X_FADDRH, 0xDFAD); // Flash Address High Byte
\r
359 SFRX(X_FCTL, 0xDFAE); // Flash Control
\r
360 SFRX(X_FWDATA, 0xDFAF); // Flash Write Data
\r
361 SFRX(X_ENCDI, 0xDFB1); // Encryption Input Data
\r
362 SFRX(X_ENCDO, 0xDFB2); // Encryption Output Data
\r
363 SFRX(X_ENCCS, 0xDFB3); // Encryption Control and Status
\r
364 SFRX(X_ADCCON1, 0xDFB4); // ADC Control 1
\r
365 SFRX(X_ADCCON2, 0xDFB5); // ADC Control 2
\r
366 SFRX(X_ADCCON3, 0xDFB6); // ADC Control 3
\r
367 SFRX(X_ADCL, 0xDFBA); // ADC Data Low
\r
368 SFRX(X_ADCH, 0xDFBB); // ADC Data High
\r
369 SFRX(X_RNDL, 0xDFBC); // Random Number Generator Data Low Byte
\r
370 SFRX(X_RNDH, 0xDFBD); // Random Number Generator Data High Byte
\r
371 SFRX(X_SLEEP, 0xDFBE); // Sleep Mode Control
\r
372 SFRX(X_U0DBUF, 0xDFC1); // USART 0 Receive/Transmit Data Buffer
\r
373 SFRX(X_U0BAUD, 0xDFC2); // USART 0 Baud Rate Control
\r
374 SFRX(X_T2CNF, 0xDFC3); // Timer 2 Configuration
\r
375 SFRX(X_U0UCR, 0xDFC4); // USART 0 UART Control
\r
376 SFRX(X_U0GCR, 0xDFC5); // USART 0 Generic Control
\r
377 SFRX(X_CLKCON, 0xDFC6); // Clock Control
\r
378 SFRX(X_MEMCTR, 0xDFC7); // Memory Arbiter Control
\r
379 SFRX(X_WDCTL, 0xDFC9); // Watchdog Timer Control
\r
380 SFRX(X_T3CNT, 0xDFCA); // Timer 3 Counter
\r
381 SFRX(X_T3CTL, 0xDFCB); // Timer 3 Control
\r
382 SFRX(X_T3CCTL0, 0xDFCC); // Timer 3 Channel 0 Capture/Compare Control
\r
383 SFRX(X_T3CC0, 0xDFCD); // Timer 3 Channel 0 Capture/Compare Value
\r
384 SFRX(X_T3CCTL1, 0xDFCE); // Timer 3 Channel 1 Capture/Compare Control
\r
385 SFRX(X_T3CC1, 0xDFCF); // Timer 3 Channel 1 Capture/Compare Value
\r
386 SFRX(X_DMAIRQ, 0xDFD1); // DMA Interrupt Flag
\r
387 SFRX(X_DMA1CFGL, 0xDFD2); // DMA Channel 1-4 Configuration Address Low Byte
\r
388 SFRX(X_DMA1CFGH, 0xDFD3); // DMA Channel 1-4 Configuration Address High Byte
\r
389 SFRX(X_DMA0CFGL, 0xDFD4); // DMA Channel 0 Configuration Address Low Byte
\r
390 SFRX(X_DMA0CFGH, 0xDFD5); // DMA Channel 0 Configuration Address High Byte
\r
391 SFRX(X_DMAARM, 0xDFD6); // DMA Channel Arm
\r
392 SFRX(X_DMAREQ, 0xDFD7); // DMA Channel Start Request and Status
\r
393 SFRX(X_TIMIF, 0xDFD8); // Timers 1/3/4 Interrupt Mask/Flag
\r
394 SFRX(X_RFD, 0xDFD9); // RF Data
\r
395 SFRX(X_T1CC0L, 0xDFDA); // Timer 1 Channel 0 Capture/Compare Value Low
\r
396 SFRX(X_T1CC0H, 0xDFDB); // Timer 1 Channel 0 Capture/Compare Value High
\r
397 SFRX(X_T1CC1L, 0xDFDC); // Timer 1 Channel 1 Capture/Compare Value Low
\r
398 SFRX(X_T1CC1H, 0xDFDD); // Timer 1 Channel 1 Capture/Compare Value High
\r
399 SFRX(X_T1CC2L, 0xDFDE); // Timer 1 Channel 2 Capture/Compare Value Low
\r
400 SFRX(X_T1CC2H, 0xDFDF); // Timer 1 Channel 2 Capture/Compare Value High
\r
401 SFRX(X_RFST, 0xDFE1); // RF CSMA-CA / Strobe Processor
\r
402 SFRX(X_T1CNTL, 0xDFE2); // Timer 1 Counter Low
\r
403 SFRX(X_T1CNTH, 0xDFE3); // Timer 1 Counter High
\r
404 SFRX(X_T1CTL, 0xDFE4); // Timer 1 Control and Status
\r
405 SFRX(X_T1CCTL0, 0xDFE5); // Timer 1 Channel 0 Capture/Compare Control
\r
406 SFRX(X_T1CCTL1, 0xDFE6); // Timer 1 Channel 1 Capture/Compare Control
\r
407 SFRX(X_T1CCTL2, 0xDFE7); // Timer 1 Channel 2 Capture/Compare Control
\r
408 SFRX(X_RFIF, 0xDFE9); // RF Interrupt Flags
\r
409 SFRX(X_T4CNT, 0xDFEA); // Timer 4 Counter
\r
410 SFRX(X_T4CTL, 0xDFEB); // Timer 4 Control
\r
411 SFRX(X_T4CCTL0, 0xDFEC); // Timer 4 Channel 0 Capture/Compare Control
\r
412 SFRX(X_T4CC0, 0xDFED); // Timer 4 Channel 0 Capture/Compare Value
\r
413 SFRX(X_T4CCTL1, 0xDFEE); // Timer 4 Channel 1 Capture/Compare Control
\r
414 SFRX(X_T4CC1, 0xDFEF); // Timer 4 Channel 1 Capture/Compare Value
\r
415 SFRX(X_PERCFG, 0xDFF1); // Peripheral Control
\r
416 SFRX(X_ADCCFG, 0xDFF2); // ADC Input Configuration
\r
417 SFRX(X_P0SEL, 0xDFF3); // Port 0 Function Select
\r
418 SFRX(X_P1SEL, 0xDFF4); // Port 1 Function Select
\r
419 SFRX(X_P2SEL, 0xDFF5); // Port 2 Function Select
\r
420 SFRX(X_P1INP, 0xDFF6); // Port 1 Input Mode
\r
421 SFRX(X_P2INP, 0xDFF7); // Port 2 Input Mode
\r
422 SFRX(X_U1CSR, 0xDFF8); // USART 1 Control and Status
\r
423 SFRX(X_U1DBUF, 0xDFF9); // USART 1 Receive/Transmit Data Buffer
\r
424 SFRX(X_U1BAUD, 0xDFFA); // USART 1 Baud Rate Control
\r
425 SFRX(X_U1UCR, 0xDFFB); // USART 1 UART Control
\r
426 SFRX(X_U1GCR, 0xDFFC); // USART 1 Generic Control
\r
427 SFRX(X_P0DIR, 0xDFFD); // Port 0 Direction
\r
428 SFRX(X_P1DIR, 0xDFFE); // Port 1 Direction
\r
429 SFRX(X_P2DIR, 0xDFFF); // Port 2 Direction
\r
431 #endif //REG_CC2430_H
\r
projects / fw / sdcc / blob