1 /*--------------------------------------------------------------------------
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4 This header allows to use the microcontroler Philips P89c51RD2
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5 with the compiler SDCC.
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7 Copyright (c) 2005 Omar Espinosa--e-mail: opiedrahita2003 AT yahoo.com.
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9 This library is free software; you can redistribute it and/or
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10 modify it under the terms of the GNU Lesser General Public
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11 License as published by the Free Software Foundation; either
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12 version 2.1 of the License, or (at your option) any later version.
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14 This library is distributed in the hope that it will be useful,
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15 but WITHOUT ANY WARRANTY; without even the implied warranty of
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16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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17 Lesser General Public License for more details.
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19 You should have received a copy of the GNU Lesser General Public
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20 License along with this library; if not, write to the Free Software
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21 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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24 Archivo encabezador para el ucontrolador Philips P89c51RD2.
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25 Derechos de copy (DC) 2005. OMAR ESPINOSA P. E-mail: opiedrahita2003 AT yahoo.com
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27 --------------------------------------------------------------------------*/
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29 #ifndef __P89c51RD2_H__
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30 #define __P89c51RD2_H__
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32 /* BYTE Registers */
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33 __sfr __at (0x80) P0 ;
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34 __sfr __at (0x90) P1 ;
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35 __sfr __at (0xA0) P2 ;
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36 __sfr __at (0xB0) P3 ;
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37 __sfr __at (0xD0) PSW ;
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38 __sfr __at (0xE0) ACC ;
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39 __sfr __at (0xF0) B ;
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40 __sfr __at (0x81) SP ;
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41 __sfr __at (0x82) DPL ;
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42 __sfr __at (0x83) DPH ;
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43 __sfr __at (0x87) PCON ;
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44 __sfr __at (0x88) TCON ;
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45 __sfr __at (0x89) TMOD ;
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46 __sfr __at (0x8A) TL0 ;
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47 __sfr __at (0x8B) TL1 ;
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48 __sfr __at (0x8C) TH0 ;
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49 __sfr __at (0x8D) TH1 ;
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50 __sfr __at (0xA8) IE ;
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51 __sfr __at (0xB8) IP ;
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52 __sfr __at (0x98) SCON ;
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53 __sfr __at (0x99) SBUF ;
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55 /* 80C51Fx/Rx Extensions */
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56 __sfr __at (0x8E) AUXR ;
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57 __sfr __at (0xA2) AUXR1 ;
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58 __sfr __at (0xA9) SADDR ;
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59 __sfr __at (0xB7) IPH ;
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60 __sfr __at (0xB9) SADEN ;
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61 __sfr __at (0xC8) T2CON ;
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62 __sfr __at (0xC9) T2MOD ;
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63 __sfr __at (0xCA) RCAP2L ;
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64 __sfr __at (0xCB) RCAP2H ;
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65 __sfr __at (0xCC) TL2 ;
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66 __sfr __at (0xCD) TH2 ;
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67 __sfr __at (0xD8) CCON ;
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68 __sfr __at (0xD9) CMOD ;
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69 __sfr __at (0xDA) CCAPM0 ;
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70 __sfr __at (0xDB) CCAPM1 ;
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71 __sfr __at (0xDC) CCAPM2 ;
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72 __sfr __at (0xDD) CCAPM3 ;
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73 __sfr __at (0xDE) CCAPM4 ;
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74 __sfr __at (0xE9) CL ;
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75 __sfr __at (0xEA) CCAP0L ;
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76 __sfr __at (0xEB) CCAP1L ;
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77 __sfr __at (0xEC) CCAP2L ;
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78 __sfr __at (0xED) CCAP3L ;
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79 __sfr __at (0xEE) CCAP4L ;
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80 __sfr __at (0xF9) CH ;
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81 __sfr __at (0xFA) CCAP0H ;
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82 __sfr __at (0xFB) CCAP1H ;
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83 __sfr __at (0xFC) CCAP2H ;
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84 __sfr __at (0xFD) CCAP3H ;
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85 __sfr __at (0xFE) CCAP4H ;
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91 __sbit __at (0xD7) PSW_7;
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92 __sbit __at (0xD6) PSW_6;
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93 __sbit __at (0xD5) PSW_5;
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94 __sbit __at (0xD4) PSW_4;
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95 __sbit __at (0xD3) PSW_3;
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96 __sbit __at (0xD2) PSW_2;
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97 __sbit __at (0xD0) PSW_0;
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108 __sbit __at (0x8F) TCON_7;
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109 __sbit __at (0x8E) TCON_6;
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110 __sbit __at (0x8D) TCON_5;
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111 __sbit __at (0x8C) TCON_4;
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112 __sbit __at (0x8B) TCON_3;
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113 __sbit __at (0x8A) TCON_2;
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114 __sbit __at (0x89) TCON_1;
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115 __sbit __at (0x88) TCON_0;
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127 __sbit __at (0xAF) IE_7;
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128 __sbit __at (0xAE) IE_6;
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129 __sbit __at (0xAD) IE_5;
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130 __sbit __at (0xAC) IE_4;
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131 __sbit __at (0xAB) IE_3;
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132 __sbit __at (0xAA) IE_2;
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133 __sbit __at (0xA9) IE_1;
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134 __sbit __at (0xA8) IE_0;
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146 __sbit __at (0xBE) IP_6;
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147 __sbit __at (0xBD) IP_5;
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148 __sbit __at (0xBC) IP_4;
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149 __sbit __at (0xBB) IP_3;
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150 __sbit __at (0xBA) IP_2;
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151 __sbit __at (0xB9) IP_1;
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152 __sbit __at (0xB8) IP_0;
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163 __sbit __at (0xB7) P3_7;
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164 __sbit __at (0xB6) P3_6;
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165 __sbit __at (0xB5) P3_5;
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166 __sbit __at (0xB4) P3_4;
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167 __sbit __at (0xB3) P3_3;
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168 __sbit __at (0xB2) P3_2;
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169 __sbit __at (0xB1) P3_1;
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170 __sbit __at (0xB0) P3_0;
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182 __sbit __at (0x9F) SCON_7; // alternatively "FE"
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183 __sbit __at (0x9E) SCON_6;
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184 __sbit __at (0x9D) SCON_5;
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185 __sbit __at (0x9C) SCON_4;
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186 __sbit __at (0x9B) SCON_3;
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187 __sbit __at (0x9A) SCON_2;
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188 __sbit __at (0x99) SCON_1;
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189 __sbit __at (0x98) SCON_0;
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191 #define SM0 SCON_7 // alternatively "FE"
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202 __sbit __at (0x97) P1_7;
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203 __sbit __at (0x96) P1_6;
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204 __sbit __at (0x95) P1_5;
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205 __sbit __at (0x94) P1_4;
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206 __sbit __at (0x93) P1_3;
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207 __sbit __at (0x92) P1_2;
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208 __sbit __at (0x91) P1_1;
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209 __sbit __at (0x90) P1_0;
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221 __sbit __at (0xCF) T2CON_7;
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222 __sbit __at (0xCE) T2CON_6;
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223 __sbit __at (0xCD) T2CON_5;
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224 __sbit __at (0xCC) T2CON_4;
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225 __sbit __at (0xCB) T2CON_3;
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226 __sbit __at (0xCA) T2CON_2;
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227 __sbit __at (0xC9) T2CON_1;
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228 __sbit __at (0xC8) T2CON_0;
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230 #define TF2 T2CON_7
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231 #define EXF2 T2CON_6
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232 #define RCLK T2CON_5
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233 #define TCLK T2CON_4
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234 #define EXEN2 T2CON_3
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235 #define TR2 T2CON_2
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236 #define C_T2 T2CON_1
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237 #define CP_RL2 T2CON_0
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240 __sbit __at (0xDF) CCON_7;
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241 __sbit __at (0xDE) CCON_6;
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242 __sbit __at (0xDC) CCON_4;
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243 __sbit __at (0xDB) CCON_3;
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244 __sbit __at (0xDA) CCON_2;
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245 __sbit __at (0xD9) CCON_1;
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246 __sbit __at (0xD8) CCON_0;
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250 #define CCF4 CCON_4
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251 #define CCF3 CCON_3
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252 #define CCF2 CCON_2
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253 #define CCF1 CCON_1
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254 #define CCF0 CCON_0
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projects / fw / sdcc / blob