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target/riscv: Update with latest encoding from riscv-opcodes
2022-08-27 Tim Newsometarget/riscv: Update with latest encoding from riscv...
Signed-off-by: Tim Newsome <tim@sifive.com>
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2022-08-15 Tim Newsometarget/riscv: Update debug_defines.h.
Signed-off-by: Tim Newsome <tim@sifive.com>
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2022-05-27 Tim NewsomeGive each SMP group a unique number.
Signed-off-by: Tim Newsome <tim@sifive.com>
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2022-02-14 Tim NewsomeFix small memory leak.
Signed-off-by: Tim Newsome <tim@sifive.com>
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2022-02-14 Tim Newsometarget/riscv: revive 'riscv resume_order'
Signed-off-by: Tim Newsome <tim@sifive.com>
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2022-01-29 Tim NewsomeCombine register lists of smp targets.
Signed-off-by: Tim Newsome <tim@sifive.com>
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2021-12-24 Tim NewsomeDocument how vector registers are exposed to gdb.
Signed-off-by: Tim Newsome <tim@sifive.com>
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2021-12-24 Tim Newsometarget/riscv: calloc() memory per register.
Signed-off-by: Tim Newsome <tim@sifive.com>
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2021-12-03 Tim Newsomeflash/nor/fespi: algorithm, large address, errors
Signed-off-by: Tim Newsome <tim@sifive.com>
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2021-11-20 Tim Newsometarget: Use target_addr_t for algorithm addresses.
Signed-off-by: Tim Newsome <tim@sifive.com>
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2021-11-20 Tim Newsomeriscv: Clear type 6 triggers on connecting.
Signed-off-by: Tim Newsome <tim@sifive.com>
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2021-11-05 Tim Newsomertos: use struct member names instead of comments
Signed-off-by: Tim Newsome <tim@sifive.com>
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2021-10-25 Tim NewsomeUpstream a whole host of RISC-V changes.
Signed-off-by: Tim Newsome <tim@sifive.com>
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2021-10-02 Tim Newsomeuint64_t->target_addr_t for stack pointers.
Signed-off-by: Tim Newsome <tim@sifive.com>
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2021-09-25 Tim NewsomeSpeed up remote bitbang.
Signed-off-by: Tim Newsome <tim@sifive.com>
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2021-09-11 Tim NewsomeIn SMP config, replicate watchpoints on each core
Signed-off-by: Tim Newsome <tim@sifive.com>
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2021-07-31 Tim NewsomeCall poll at a fixed interval.
Signed-off-by: Tim Newsome <tim@sifive.com>
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2021-07-02 Tim NewsomeAdd RTOS memory read/write functions.
Signed-off-by: Tim Newsome <tim@sifive.com>
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2021-06-13 Tim NewsomeAdd remote bitbang write buffer.
Signed-off-by: Tim Newsome <tim@sifive.com>
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2021-06-04 Tim NewsomeAdd target_data_bits().
Signed-off-by: Tim Newsome <tim@sifive.com>
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2021-05-01 Tim NewsomeCleanup of config/includes.
Signed-off-by: Tim Newsome <tim@sifive.com>
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2021-03-19 Tim NewsomeImplement CRC32 algorithm for RISC-V.
Signed-off-by: Tim Newsome <tim@sifive.com>
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2020-10-14 Tim NewsomeUpstream tons of RISC-V changes.
Signed-off-by: Tim Newsome <tim@sifive.com>
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2020-05-07 Tim NewsomeAdd get_thread_reg() and set_reg() for hwthread
Signed-off-by: Tim Newsome <tim@sifive.com>
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2019-10-15 Tim NewsomeAdd complete JTAG debug logging.
Signed-off-by: Tim Newsome <tim@sifive.com>
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2019-10-15 Tim NewsomeAdd wall clock timeout warning to mpsse_flush()
Signed-off-by: Tim Newsome <tim@sifive.com>
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2019-08-28 Tim Newsomegdb_server, rtos: Fine-grained RTOS register access
Signed-off-by: Tim Newsome <tim@sifive.com>
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2019-04-24 Tim Newsomeflash/fespi: Use COMMAND_PARSE_ADDRESS
Signed-off-by: Tim Newsome <tim@sifive.com>
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2019-03-27 Tim NewsomeLots of RISC-V improvements.
Signed-off-by: Tim Newsome <tim@sifive.com>
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2019-03-08 Tim Newsomeflash/nor: use target_addr_t for flash bank base
Signed-off-by: Tim Newsome <tim@sifive.com>
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2019-03-08 Tim Newsomegdb_server, target: Add target_address_bits()
Signed-off-by: Tim Newsome <tim@sifive.com>
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2019-01-11 Tim NewsomeAdd flash support for SiFive's Freedom E platforms
Signed-off-by: Tim Newsome <tim@sifive.com>
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2018-09-25 Tim NewsomeClarify what exactly the RISC-V code supports.
Signed-off-by: Tim Newsome <tim@sifive.com>
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2018-08-08 Tim NewsomeAdd detail to `wrong register size` error.
Signed-off-by: Tim Newsome <tim@sifive.com>
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2018-07-24 Tim NewsomeAdd RISC-V support.
Signed-off-by: Tim Newsome <tim@sifive.com>
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2018-07-23 Tim NewsomeRemove FSF mailing address.
Signed-off-by: Tim Newsome <tim@sifive.com>
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2018-04-07 Tim NewsomeAdd gdb_report_register_access_error command
Signed-off-by: Tim Newsome <tim@sifive.com>
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2018-01-25 Tim NewsomeAdd read buffer to bitbang, improving performance.
Signed-off-by: Tim Newsome <tim@sifive.com>
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2018-01-13 Tim NewsomeAccept 64-bit addresses in CRC requests.
Signed-off-by: Tim Newsome <tim@sifive.com>
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2018-01-13 Tim NewsomeSupport listening on port 0.
Signed-off-by: Tim Newsome <tim@sifive.com>
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2017-10-18 Tim NewsomeDifferentiate "target not halted" messages.
Signed-off-by: Tim Newsome <tim@sifive.com>
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2017-10-18 Tim NewsomeDocument `struct reg` fields.
Signed-off-by: Tim Newsome <tim@sifive.com>
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2017-10-03 Tim NewsomeFix typo in comment.
Signed-off-by: Tim Newsome <tim@sifive.com>
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2016-11-04 Tim NewsomeMake OpenOCD build using -Og.
Signed-off-by: Tim Newsome <tim@sifive.com>
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2016-10-30 Tim NewsomePerform small writes before sending OK.
Signed-off-by: Tim Newsome <tim@sifive.com>
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2016-05-21 Tim NewsomeFix comment that limits num_bits to 32.
Signed-off-by: Tim Newsome <tim@sifive.com>
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openocd with support for Altus Metrum targets