* will be needed to collect the data which was read; the "invalue" collects
* the posted result of a preceding operation, not the current one.
*
- * @param swjdp the DAP
+ * @param dap the DAP
* @param instr JTAG_DP_APACC (AP access) or JTAG_DP_DPACC (DP access)
* @param reg_addr two significant bits; A[3:2]; for APACC access, the
* SELECT register has more addressing bits.
/* FIXME don't export ... this is a temporary workaround for the
* mem_ap_read_buf_u32() mess, until it's no longer JTAG-specific.
*/
-int adi_jtag_dp_scan(struct adiv5_dap *swjdp,
+int adi_jtag_dp_scan(struct adiv5_dap *dap,
uint8_t instr, uint8_t reg_addr, uint8_t RnW,
uint8_t *outvalue, uint8_t *invalue, uint8_t *ack)
{
- struct arm_jtag *jtag_info = swjdp->jtag_info;
+ struct arm_jtag *jtag_info = dap->jtag_info;
struct scan_field fields[2];
uint8_t out_addr_buf;
if ((instr == JTAG_DP_APACC)
&& ((reg_addr == AP_REG_DRW)
|| ((reg_addr & 0xF0) == AP_REG_BD0))
- && (swjdp->memaccess_tck != 0))
- jtag_add_runtest(swjdp->memaccess_tck,
+ && (dap->memaccess_tck != 0))
+ jtag_add_runtest(dap->memaccess_tck,
TAP_IDLE);
return jtag_get_error();
* conversions are performed (so the types of invalue and outvalue
* must be different).
*/
-static int adi_jtag_dp_scan_u32(struct adiv5_dap *swjdp,
+static int adi_jtag_dp_scan_u32(struct adiv5_dap *dap,
uint8_t instr, uint8_t reg_addr, uint8_t RnW,
uint32_t outvalue, uint32_t *invalue, uint8_t *ack)
{
buf_set_u32(out_value_buf, 0, 32, outvalue);
- retval = adi_jtag_dp_scan(swjdp, instr, reg_addr, RnW,
+ retval = adi_jtag_dp_scan(dap, instr, reg_addr, RnW,
out_value_buf, (uint8_t *)invalue, ack);
if (retval != ERROR_OK)
return retval;
outvalue, NULL, NULL);
}
-static int adi_jtag_scan_inout_check_u32(struct adiv5_dap *swjdp,
+static int adi_jtag_scan_inout_check_u32(struct adiv5_dap *dap,
uint8_t instr, uint8_t reg_addr, uint8_t RnW,
uint32_t outvalue, uint32_t *invalue)
{
int retval;
/* Issue the read or write */
- retval = adi_jtag_dp_scan_u32(swjdp, instr, reg_addr,
+ retval = adi_jtag_dp_scan_u32(dap, instr, reg_addr,
RnW, outvalue, NULL, NULL);
if (retval != ERROR_OK)
return retval;
* Assumes read gets acked with OK/FAULT, and CTRL_STAT says "OK".
*/
if ((RnW == DPAP_READ) && (invalue != NULL))
- retval = adi_jtag_dp_scan_u32(swjdp, JTAG_DP_DPACC,
- DP_RDBUFF, DPAP_READ, 0, invalue, &swjdp->ack);
+ retval = adi_jtag_dp_scan_u32(dap, JTAG_DP_DPACC,
+ DP_RDBUFF, DPAP_READ, 0, invalue, &dap->ack);
return retval;
}
-static int jtagdp_transaction_endcheck(struct adiv5_dap *swjdp)
+static int jtagdp_transaction_endcheck(struct adiv5_dap *dap)
{
int retval;
uint32_t ctrlstat;
#if 0
/* Danger!!!! BROKEN!!!! */
- adi_jtag_scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
+ adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
/* Danger!!!! BROKEN!!!! Why will jtag_execute_queue() fail here????
R956 introduced the check on return value here and now Michael Schwingen reports
/* Post CTRL/STAT read; discard any previous posted read value
* but collect its ACK status.
*/
- adi_jtag_scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
+ adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
if ((retval = jtag_execute_queue()) != ERROR_OK)
return retval;
- swjdp->ack = swjdp->ack & 0x7;
+ dap->ack = dap->ack & 0x7;
/* common code path avoids calling timeval_ms() */
- if (swjdp->ack != JTAG_ACK_OK_FAULT)
+ if (dap->ack != JTAG_ACK_OK_FAULT)
{
long long then = timeval_ms();
- while (swjdp->ack != JTAG_ACK_OK_FAULT)
+ while (dap->ack != JTAG_ACK_OK_FAULT)
{
- if (swjdp->ack == JTAG_ACK_WAIT)
+ if (dap->ack == JTAG_ACK_WAIT)
{
if ((timeval_ms()-then) > 1000)
{
{
LOG_WARNING("Invalid ACK %#x "
"in JTAG-DP transaction",
- swjdp->ack);
+ dap->ack);
return ERROR_JTAG_DEVICE_ERROR;
}
- adi_jtag_scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
+ adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
- if ((retval = dap_run(swjdp)) != ERROR_OK)
+ if ((retval = dap_run(dap)) != ERROR_OK)
return retval;
- swjdp->ack = swjdp->ack & 0x7;
+ dap->ack = dap->ack & 0x7;
}
}
LOG_DEBUG("jtag-dp: CTRL/STAT error, 0x%" PRIx32, ctrlstat);
/* Check power to debug regions */
if ((ctrlstat & 0xf0000000) != 0xf0000000)
- ahbap_debugport_init(swjdp);
+ ahbap_debugport_init(dap);
else
{
uint32_t mem_ap_csw, mem_ap_tar;
* MEM-AP access; but not if autoincrementing.
* *Real* CSW and TAR values are always shown.
*/
- if (swjdp->ap_tar_value != (uint32_t) -1)
+ if (dap->ap_tar_value != (uint32_t) -1)
LOG_DEBUG("MEM-AP Cached values: "
"ap_bank 0x%" PRIx32
", ap_csw 0x%" PRIx32
", ap_tar 0x%" PRIx32,
- swjdp->ap_bank_value,
- swjdp->ap_csw_value,
- swjdp->ap_tar_value);
+ dap->ap_bank_value,
+ dap->ap_csw_value,
+ dap->ap_tar_value);
if (ctrlstat & SSTICKYORUN)
LOG_ERROR("JTAG-DP OVERRUN - check clock, "
LOG_ERROR("JTAG-DP STICKY ERROR");
/* Clear Sticky Error Bits */
- adi_jtag_scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
+ adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
DP_CTRL_STAT, DPAP_WRITE,
- swjdp->dp_ctrl_stat | SSTICKYORUN
+ dap->dp_ctrl_stat | SSTICKYORUN
| SSTICKYERR, NULL);
- adi_jtag_scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
+ adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
- if ((retval = dap_run(swjdp)) != ERROR_OK)
+ if ((retval = dap_run(dap)) != ERROR_OK)
return retval;
LOG_DEBUG("jtag-dp: CTRL/STAT 0x%" PRIx32, ctrlstat);
- retval = dap_queue_ap_read(swjdp,
+ retval = dap_queue_ap_read(dap,
AP_REG_CSW, &mem_ap_csw);
if (retval != ERROR_OK)
return retval;
- retval = dap_queue_ap_read(swjdp,
+ retval = dap_queue_ap_read(dap,
AP_REG_TAR, &mem_ap_tar);
if (retval != ERROR_OK)
return retval;
- if ((retval = dap_run(swjdp)) != ERROR_OK)
+ if ((retval = dap_run(dap)) != ERROR_OK)
return retval;
LOG_ERROR("MEM_AP_CSW 0x%" PRIx32 ", MEM_AP_TAR 0x%"
PRIx32, mem_ap_csw, mem_ap_tar);
}
- if ((retval = dap_run(swjdp)) != ERROR_OK)
+ if ((retval = dap_run(dap)) != ERROR_OK)
return retval;
return ERROR_JTAG_DEVICE_ERROR;
}
* selection is implicitly used with future AP transactions.
* This is a NOP if the specified AP is already selected.
*
- * @param swjdp The DAP
+ * @param dap The DAP
* @param apsel Number of the AP to (implicitly) use with further
* transactions. This normally identifies a MEM-AP.
*/
-void dap_ap_select(struct adiv5_dap *swjdp,uint8_t apsel)
+void dap_ap_select(struct adiv5_dap *dap,uint8_t apsel)
{
uint32_t select = (apsel << 24) & 0xFF000000;
- if (select != swjdp->apsel)
+ if (select != dap->apsel)
{
- swjdp->apsel = select;
+ dap->apsel = select;
/* Switching AP invalidates cached values.
* Values MUST BE UPDATED BEFORE AP ACCESS.
*/
- swjdp->ap_bank_value = -1;
- swjdp->ap_csw_value = -1;
- swjdp->ap_tar_value = -1;
+ dap->ap_bank_value = -1;
+ dap->ap_csw_value = -1;
+ dap->ap_tar_value = -1;
}
}
*
* @todo Rename to reflect it being specifically a MEM-AP function.
*
- * @param swjdp The DAP connected to the MEM-AP.
+ * @param dap The DAP connected to the MEM-AP.
* @param csw MEM-AP Control/Status Word (CSW) register to assign. If this
* matches the cached value, the register is not changed.
* @param tar MEM-AP Transfer Address Register (TAR) to assign. If this
*
* @return ERROR_OK if the transaction was properly queued, else a fault code.
*/
-int dap_setup_accessport(struct adiv5_dap *swjdp, uint32_t csw, uint32_t tar)
+int dap_setup_accessport(struct adiv5_dap *dap, uint32_t csw, uint32_t tar)
{
int retval;
csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT;
- if (csw != swjdp->ap_csw_value)
+ if (csw != dap->ap_csw_value)
{
/* LOG_DEBUG("DAP: Set CSW %x",csw); */
- retval = dap_queue_ap_write(swjdp, AP_REG_CSW, csw);
+ retval = dap_queue_ap_write(dap, AP_REG_CSW, csw);
if (retval != ERROR_OK)
return retval;
- swjdp->ap_csw_value = csw;
+ dap->ap_csw_value = csw;
}
- if (tar != swjdp->ap_tar_value)
+ if (tar != dap->ap_tar_value)
{
/* LOG_DEBUG("DAP: Set TAR %x",tar); */
- retval = dap_queue_ap_write(swjdp, AP_REG_TAR, tar);
+ retval = dap_queue_ap_write(dap, AP_REG_TAR, tar);
if (retval != ERROR_OK)
return retval;
- swjdp->ap_tar_value = tar;
+ dap->ap_tar_value = tar;
}
/* Disable TAR cache when autoincrementing */
if (csw & CSW_ADDRINC_MASK)
- swjdp->ap_tar_value = -1;
+ dap->ap_tar_value = -1;
return ERROR_OK;
}
/**
* Asynchronous (queued) read of a word from memory or a system register.
*
- * @param swjdp The DAP connected to the MEM-AP performing the read.
+ * @param dap The DAP connected to the MEM-AP performing the read.
* @param address Address of the 32-bit word to read; it must be
* readable by the currently selected MEM-AP.
* @param value points to where the word will be stored when the
*
* @return ERROR_OK for success. Otherwise a fault code.
*/
-int mem_ap_read_u32(struct adiv5_dap *swjdp, uint32_t address,
+int mem_ap_read_u32(struct adiv5_dap *dap, uint32_t address,
uint32_t *value)
{
int retval;
/* Use banked addressing (REG_BDx) to avoid some link traffic
* (updating TAR) when reading several consecutive addresses.
*/
- retval = dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF,
+ retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_OFF,
address & 0xFFFFFFF0);
if (retval != ERROR_OK)
return retval;
- return dap_queue_ap_read(swjdp, AP_REG_BD0 | (address & 0xC), value);
+ return dap_queue_ap_read(dap, AP_REG_BD0 | (address & 0xC), value);
}
/**
* Synchronous read of a word from memory or a system register.
* As a side effect, this flushes any queued transactions.
*
- * @param swjdp The DAP connected to the MEM-AP performing the read.
+ * @param dap The DAP connected to the MEM-AP performing the read.
* @param address Address of the 32-bit word to read; it must be
* readable by the currently selected MEM-AP.
* @param value points to where the result will be stored.
* @return ERROR_OK for success; *value holds the result.
* Otherwise a fault code.
*/
-int mem_ap_read_atomic_u32(struct adiv5_dap *swjdp, uint32_t address,
+int mem_ap_read_atomic_u32(struct adiv5_dap *dap, uint32_t address,
uint32_t *value)
{
int retval;
- retval = mem_ap_read_u32(swjdp, address, value);
+ retval = mem_ap_read_u32(dap, address, value);
if (retval != ERROR_OK)
return retval;
- return dap_run(swjdp);
+ return dap_run(dap);
}
/**
* Asynchronous (queued) write of a word to memory or a system register.
*
- * @param swjdp The DAP connected to the MEM-AP.
+ * @param dap The DAP connected to the MEM-AP.
* @param address Address to be written; it must be writable by
* the currently selected MEM-AP.
* @param value Word that will be written to the address when transaction
*
* @return ERROR_OK for success. Otherwise a fault code.
*/
-int mem_ap_write_u32(struct adiv5_dap *swjdp, uint32_t address,
+int mem_ap_write_u32(struct adiv5_dap *dap, uint32_t address,
uint32_t value)
{
int retval;
/* Use banked addressing (REG_BDx) to avoid some link traffic
* (updating TAR) when writing several consecutive addresses.
*/
- retval = dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF,
+ retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_OFF,
address & 0xFFFFFFF0);
if (retval != ERROR_OK)
return retval;
- return dap_queue_ap_write(swjdp, AP_REG_BD0 | (address & 0xC),
+ return dap_queue_ap_write(dap, AP_REG_BD0 | (address & 0xC),
value);
}
* Synchronous write of a word to memory or a system register.
* As a side effect, this flushes any queued transactions.
*
- * @param swjdp The DAP connected to the MEM-AP.
+ * @param dap The DAP connected to the MEM-AP.
* @param address Address to be written; it must be writable by
* the currently selected MEM-AP.
* @param value Word that will be written.
*
* @return ERROR_OK for success; the data was written. Otherwise a fault code.
*/
-int mem_ap_write_atomic_u32(struct adiv5_dap *swjdp, uint32_t address,
+int mem_ap_write_atomic_u32(struct adiv5_dap *dap, uint32_t address,
uint32_t value)
{
- int retval = mem_ap_write_u32(swjdp, address, value);
+ int retval = mem_ap_write_u32(dap, address, value);
if (retval != ERROR_OK)
return retval;
- return dap_run(swjdp);
+ return dap_run(dap);
}
/*****************************************************************************
* *
-* mem_ap_write_buf(struct adiv5_dap *swjdp, uint8_t *buffer, int count, uint32_t address) *
+* mem_ap_write_buf(struct adiv5_dap *dap, uint8_t *buffer, int count, uint32_t address) *
* *
* Write a buffer in target order (little endian) *
* *
*****************************************************************************/
-int mem_ap_write_buf_u32(struct adiv5_dap *swjdp, uint8_t *buffer, int count, uint32_t address)
+int mem_ap_write_buf_u32(struct adiv5_dap *dap, uint8_t *buffer, int count, uint32_t address)
{
int wcount, blocksize, writecount, errorcount = 0, retval = ERROR_OK;
uint32_t adr = address;
while (wcount > 0)
{
/* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
- blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
+ blocksize = max_tar_block_size(dap->tar_autoincr_block, address);
if (wcount < blocksize)
blocksize = wcount;
if (blocksize == 0)
blocksize = 1;
- dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_SINGLE, address);
+ dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_SINGLE, address);
for (writecount = 0; writecount < blocksize; writecount++)
{
- retval = dap_queue_ap_write(swjdp, AP_REG_DRW,
+ retval = dap_queue_ap_write(dap, AP_REG_DRW,
*(uint32_t *) (buffer + 4 * writecount));
if (retval != ERROR_OK)
break;
}
- if (dap_run(swjdp) == ERROR_OK)
+ if (dap_run(dap) == ERROR_OK)
{
wcount = wcount - blocksize;
address = address + 4 * blocksize;
return retval;
}
-static int mem_ap_write_buf_packed_u16(struct adiv5_dap *swjdp,
+static int mem_ap_write_buf_packed_u16(struct adiv5_dap *dap,
uint8_t *buffer, int count, uint32_t address)
{
int retval = ERROR_OK;
int nbytes;
/* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
- blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
+ blocksize = max_tar_block_size(dap->tar_autoincr_block, address);
if (wcount < blocksize)
blocksize = wcount;
if (blocksize == 0)
blocksize = 1;
- dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_PACKED, address);
+ dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_PACKED, address);
writecount = blocksize;
do
if (nbytes < 4)
{
- if (mem_ap_write_buf_u16(swjdp, buffer,
+ if (mem_ap_write_buf_u16(dap, buffer,
nbytes, address) != ERROR_OK)
{
LOG_WARNING("Block write error address "
}
memcpy(&outvalue, buffer, sizeof(uint32_t));
- retval = dap_queue_ap_write(swjdp,
+ retval = dap_queue_ap_write(dap,
AP_REG_DRW, outvalue);
if (retval != ERROR_OK)
break;
- if (dap_run(swjdp) != ERROR_OK)
+ if (dap_run(dap) != ERROR_OK)
{
LOG_WARNING("Block write error address "
"0x%" PRIx32 ", count 0x%x",
return retval;
}
-int mem_ap_write_buf_u16(struct adiv5_dap *swjdp, uint8_t *buffer, int count, uint32_t address)
+int mem_ap_write_buf_u16(struct adiv5_dap *dap, uint8_t *buffer, int count, uint32_t address)
{
int retval = ERROR_OK;
if (count >= 4)
- return mem_ap_write_buf_packed_u16(swjdp, buffer, count, address);
+ return mem_ap_write_buf_packed_u16(dap, buffer, count, address);
while (count > 0)
{
- dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
+ dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
uint16_t svalue;
memcpy(&svalue, buffer, sizeof(uint16_t));
uint32_t outvalue = (uint32_t)svalue << 8 * (address & 0x3);
- retval = dap_queue_ap_write(swjdp, AP_REG_DRW, outvalue);
+ retval = dap_queue_ap_write(dap, AP_REG_DRW, outvalue);
if (retval != ERROR_OK)
break;
- retval = dap_run(swjdp);
+ retval = dap_run(dap);
if (retval != ERROR_OK)
break;
return retval;
}
-static int mem_ap_write_buf_packed_u8(struct adiv5_dap *swjdp,
+static int mem_ap_write_buf_packed_u8(struct adiv5_dap *dap,
uint8_t *buffer, int count, uint32_t address)
{
int retval = ERROR_OK;
int nbytes;
/* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
- blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
+ blocksize = max_tar_block_size(dap->tar_autoincr_block, address);
if (wcount < blocksize)
blocksize = wcount;
- dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_PACKED, address);
+ dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_PACKED, address);
writecount = blocksize;
do
if (nbytes < 4)
{
- if (mem_ap_write_buf_u8(swjdp, buffer, nbytes, address) != ERROR_OK)
+ if (mem_ap_write_buf_u8(dap, buffer, nbytes, address) != ERROR_OK)
{
LOG_WARNING("Block write error address "
"0x%" PRIx32 ", count 0x%x",
}
memcpy(&outvalue, buffer, sizeof(uint32_t));
- retval = dap_queue_ap_write(swjdp,
+ retval = dap_queue_ap_write(dap,
AP_REG_DRW, outvalue);
if (retval != ERROR_OK)
break;
- if (dap_run(swjdp) != ERROR_OK)
+ if (dap_run(dap) != ERROR_OK)
{
LOG_WARNING("Block write error address "
"0x%" PRIx32 ", count 0x%x",
return retval;
}
-int mem_ap_write_buf_u8(struct adiv5_dap *swjdp, uint8_t *buffer, int count, uint32_t address)
+int mem_ap_write_buf_u8(struct adiv5_dap *dap, uint8_t *buffer, int count, uint32_t address)
{
int retval = ERROR_OK;
if (count >= 4)
- return mem_ap_write_buf_packed_u8(swjdp, buffer, count, address);
+ return mem_ap_write_buf_packed_u8(dap, buffer, count, address);
while (count > 0)
{
- dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
+ dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
uint32_t outvalue = (uint32_t)*buffer << 8 * (address & 0x3);
- retval = dap_queue_ap_write(swjdp, AP_REG_DRW, outvalue);
+ retval = dap_queue_ap_write(dap, AP_REG_DRW, outvalue);
if (retval != ERROR_OK)
break;
- retval = dap_run(swjdp);
+ retval = dap_run(dap);
if (retval != ERROR_OK)
break;
/* FIXME don't import ... this is a temporary workaround for the
* mem_ap_read_buf_u32() mess, until it's no longer JTAG-specific.
*/
-extern int adi_jtag_dp_scan(struct adiv5_dap *swjdp,
+extern int adi_jtag_dp_scan(struct adiv5_dap *dap,
uint8_t instr, uint8_t reg_addr, uint8_t RnW,
uint8_t *outvalue, uint8_t *invalue, uint8_t *ack);
/**
* Synchronously read a block of 32-bit words into a buffer
- * @param swjdp The DAP connected to the MEM-AP.
+ * @param dap The DAP connected to the MEM-AP.
* @param buffer where the words will be stored (in host byte order).
* @param count How many words to read.
* @param address Memory address from which to read words; all the
* words must be readable by the currently selected MEM-AP.
*/
-int mem_ap_read_buf_u32(struct adiv5_dap *swjdp, uint8_t *buffer,
+int mem_ap_read_buf_u32(struct adiv5_dap *dap, uint8_t *buffer,
int count, uint32_t address)
{
int wcount, blocksize, readcount, errorcount = 0, retval = ERROR_OK;
* TAR autoincrement size (at least 2^10). Autoincrement
* mode avoids an extra per-word roundtrip to update TAR.
*/
- blocksize = max_tar_block_size(swjdp->tar_autoincr_block,
+ blocksize = max_tar_block_size(dap->tar_autoincr_block,
address);
if (wcount < blocksize)
blocksize = wcount;
if (blocksize == 0)
blocksize = 1;
- dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_SINGLE,
+ dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_SINGLE,
address);
/* FIXME remove these three calls to adi_jtag_dp_scan(),
*/
/* Scan out first read */
- adi_jtag_dp_scan(swjdp, JTAG_DP_APACC, AP_REG_DRW,
+ adi_jtag_dp_scan(dap, JTAG_DP_APACC, AP_REG_DRW,
DPAP_READ, 0, NULL, NULL);
for (readcount = 0; readcount < blocksize - 1; readcount++)
{
* previous one. Assumes read is acked "OK/FAULT",
* and CTRL_STAT says that meant "OK".
*/
- adi_jtag_dp_scan(swjdp, JTAG_DP_APACC, AP_REG_DRW,
+ adi_jtag_dp_scan(dap, JTAG_DP_APACC, AP_REG_DRW,
DPAP_READ, 0, buffer + 4 * readcount,
- &swjdp->ack);
+ &dap->ack);
}
/* Scan in last posted value; RDBUFF has no other effect,
* assuming ack is OK/FAULT and CTRL_STAT says "OK".
*/
- adi_jtag_dp_scan(swjdp, JTAG_DP_DPACC, DP_RDBUFF,
+ adi_jtag_dp_scan(dap, JTAG_DP_DPACC, DP_RDBUFF,
DPAP_READ, 0, buffer + 4 * readcount,
- &swjdp->ack);
- if (dap_run(swjdp) == ERROR_OK)
+ &dap->ack);
+ if (dap_run(dap) == ERROR_OK)
{
wcount = wcount - blocksize;
address += 4 * blocksize;
return retval;
}
-static int mem_ap_read_buf_packed_u16(struct adiv5_dap *swjdp,
+static int mem_ap_read_buf_packed_u16(struct adiv5_dap *dap,
uint8_t *buffer, int count, uint32_t address)
{
uint32_t invalue;
int nbytes;
/* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
- blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
+ blocksize = max_tar_block_size(dap->tar_autoincr_block, address);
if (wcount < blocksize)
blocksize = wcount;
- dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_PACKED, address);
+ dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_PACKED, address);
/* handle unaligned data at 4k boundary */
if (blocksize == 0)
do
{
- retval = dap_queue_ap_read(swjdp, AP_REG_DRW, &invalue);
- if (dap_run(swjdp) != ERROR_OK)
+ retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue);
+ if (dap_run(dap) != ERROR_OK)
{
LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
/* REVISIT return the *actual* fault code */
/**
* Synchronously read a block of 16-bit halfwords into a buffer
- * @param swjdp The DAP connected to the MEM-AP.
+ * @param dap The DAP connected to the MEM-AP.
* @param buffer where the halfwords will be stored (in host byte order).
* @param count How many halfwords to read.
* @param address Memory address from which to read words; all the
* words must be readable by the currently selected MEM-AP.
*/
-int mem_ap_read_buf_u16(struct adiv5_dap *swjdp, uint8_t *buffer,
+int mem_ap_read_buf_u16(struct adiv5_dap *dap, uint8_t *buffer,
int count, uint32_t address)
{
uint32_t invalue, i;
int retval = ERROR_OK;
if (count >= 4)
- return mem_ap_read_buf_packed_u16(swjdp, buffer, count, address);
+ return mem_ap_read_buf_packed_u16(dap, buffer, count, address);
while (count > 0)
{
- dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
- retval = dap_queue_ap_read(swjdp, AP_REG_DRW, &invalue);
+ dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
+ retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue);
if (retval != ERROR_OK)
break;
- retval = dap_run(swjdp);
+ retval = dap_run(dap);
if (retval != ERROR_OK)
break;
* The solution is to arrange for a large out/in scan in this loop and
* and convert data afterwards.
*/
-static int mem_ap_read_buf_packed_u8(struct adiv5_dap *swjdp,
+static int mem_ap_read_buf_packed_u8(struct adiv5_dap *dap,
uint8_t *buffer, int count, uint32_t address)
{
uint32_t invalue;
int nbytes;
/* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
- blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
+ blocksize = max_tar_block_size(dap->tar_autoincr_block, address);
if (wcount < blocksize)
blocksize = wcount;
- dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_PACKED, address);
+ dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_PACKED, address);
readcount = blocksize;
do
{
- retval = dap_queue_ap_read(swjdp, AP_REG_DRW, &invalue);
- if (dap_run(swjdp) != ERROR_OK)
+ retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue);
+ if (dap_run(dap) != ERROR_OK)
{
LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
/* REVISIT return the *actual* fault code */
/**
* Synchronously read a block of bytes into a buffer
- * @param swjdp The DAP connected to the MEM-AP.
+ * @param dap The DAP connected to the MEM-AP.
* @param buffer where the bytes will be stored.
* @param count How many bytes to read.
* @param address Memory address from which to read data; all the
* data must be readable by the currently selected MEM-AP.
*/
-int mem_ap_read_buf_u8(struct adiv5_dap *swjdp, uint8_t *buffer,
+int mem_ap_read_buf_u8(struct adiv5_dap *dap, uint8_t *buffer,
int count, uint32_t address)
{
uint32_t invalue;
int retval = ERROR_OK;
if (count >= 4)
- return mem_ap_read_buf_packed_u8(swjdp, buffer, count, address);
+ return mem_ap_read_buf_packed_u8(dap, buffer, count, address);
while (count > 0)
{
- dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
- retval = dap_queue_ap_read(swjdp, AP_REG_DRW, &invalue);
- retval = dap_run(swjdp);
+ dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
+ retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue);
+ retval = dap_run(dap);
if (retval != ERROR_OK)
break;
* for further use, and arranges to use AP #0 for all AP operations
* until dap_ap-select() changes that policy.
*
- * @param swjdp The DAP being initialized.
+ * @param dap The DAP being initialized.
*
* @todo Rename this. We also need an initialization scheme which account
* for SWD transports not just JTAG; that will need to address differences
* in layering. (JTAG is useful without any debug target; but not SWD.)
* And this may not even use an AHB-AP ... e.g. DAP-Lite uses an APB-AP.
*/
-int ahbap_debugport_init(struct adiv5_dap *swjdp)
+int ahbap_debugport_init(struct adiv5_dap *dap)
{
uint32_t idreg, romaddr, dummy;
uint32_t ctrlstat;
LOG_DEBUG(" ");
/* JTAG-DP or SWJ-DP, in JTAG mode */
- swjdp->ops = &jtag_dp_ops;
+ dap->ops = &jtag_dp_ops;
/* Default MEM-AP setup.
*
* Should we probe, or take a hint from the caller?
* Presumably we can ignore the possibility of multiple APs.
*/
- swjdp->apsel = !0;
- dap_ap_select(swjdp, 0);
+ dap->apsel = !0;
+ dap_ap_select(dap, 0);
/* DP initialization */
- retval = dap_queue_dp_read(swjdp, DP_CTRL_STAT, &dummy);
+ retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &dummy);
if (retval != ERROR_OK)
return retval;
- retval = dap_queue_dp_write(swjdp, DP_CTRL_STAT, SSTICKYERR);
+ retval = dap_queue_dp_write(dap, DP_CTRL_STAT, SSTICKYERR);
if (retval != ERROR_OK)
return retval;
- retval = dap_queue_dp_read(swjdp, DP_CTRL_STAT, &dummy);
+ retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &dummy);
if (retval != ERROR_OK)
return retval;
- swjdp->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
- retval = dap_queue_dp_write(swjdp, DP_CTRL_STAT, swjdp->dp_ctrl_stat);
+ dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
+ retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
if (retval != ERROR_OK)
return retval;
- retval = dap_queue_dp_read(swjdp, DP_CTRL_STAT, &ctrlstat);
+ retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat);
if (retval != ERROR_OK)
return retval;
- if ((retval = dap_run(swjdp)) != ERROR_OK)
+ if ((retval = dap_run(dap)) != ERROR_OK)
return retval;
/* Check that we have debug power domains activated */
while (!(ctrlstat & CDBGPWRUPACK) && (cnt++ < 10))
{
LOG_DEBUG("DAP: wait CDBGPWRUPACK");
- retval = dap_queue_dp_read(swjdp, DP_CTRL_STAT, &ctrlstat);
+ retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat);
if (retval != ERROR_OK)
return retval;
- if ((retval = dap_run(swjdp)) != ERROR_OK)
+ if ((retval = dap_run(dap)) != ERROR_OK)
return retval;
alive_sleep(10);
}
while (!(ctrlstat & CSYSPWRUPACK) && (cnt++ < 10))
{
LOG_DEBUG("DAP: wait CSYSPWRUPACK");
- retval = dap_queue_dp_read(swjdp, DP_CTRL_STAT, &ctrlstat);
+ retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat);
if (retval != ERROR_OK)
return retval;
- if ((retval = dap_run(swjdp)) != ERROR_OK)
+ if ((retval = dap_run(dap)) != ERROR_OK)
return retval;
alive_sleep(10);
}
- retval = dap_queue_dp_read(swjdp, DP_CTRL_STAT, &dummy);
+ retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &dummy);
if (retval != ERROR_OK)
return retval;
/* With debug power on we can activate OVERRUN checking */
- swjdp->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT;
- retval = dap_queue_dp_write(swjdp, DP_CTRL_STAT, swjdp->dp_ctrl_stat);
+ dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT;
+ retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
if (retval != ERROR_OK)
return retval;
- retval = dap_queue_dp_read(swjdp, DP_CTRL_STAT, &dummy);
+ retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &dummy);
if (retval != ERROR_OK)
return retval;
* Should it? If the ROM address is valid, is this the right
* place to scan the table and do any topology detection?
*/
- retval = dap_queue_ap_read(swjdp, AP_REG_IDR, &idreg);
- retval = dap_queue_ap_read(swjdp, AP_REG_BASE, &romaddr);
+ retval = dap_queue_ap_read(dap, AP_REG_IDR, &idreg);
+ retval = dap_queue_ap_read(dap, AP_REG_BASE, &romaddr);
LOG_DEBUG("MEM-AP #%d ID Register 0x%" PRIx32
", Debug ROM Address 0x%" PRIx32,
- swjdp->apsel, idreg, romaddr);
+ dap->apsel, idreg, romaddr);
return ERROR_OK;
}
}
static int dap_info_command(struct command_context *cmd_ctx,
- struct adiv5_dap *swjdp, int apsel)
+ struct adiv5_dap *dap, int apsel)
{
int retval;
uint32_t dbgbase, apid;
if (apsel >= 256)
return ERROR_INVALID_ARGUMENTS;
- apselold = swjdp->apsel;
- dap_ap_select(swjdp, apsel);
- retval = dap_queue_ap_read(swjdp, AP_REG_BASE, &dbgbase);
- retval = dap_queue_ap_read(swjdp, AP_REG_IDR, &apid);
- retval = dap_run(swjdp);
+ apselold = dap->apsel;
+ dap_ap_select(dap, apsel);
+ retval = dap_queue_ap_read(dap, AP_REG_BASE, &dbgbase);
+ retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
+ retval = dap_run(dap);
if (retval != ERROR_OK)
return retval;
command_print(cmd_ctx, "\tROM table in legacy format");
/* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
- mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFF0, &cid0);
- mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFF4, &cid1);
- mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFF8, &cid2);
- mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFFC, &cid3);
- mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFCC, &memtype);
- retval = dap_run(swjdp);
+ mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF0, &cid0);
+ mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF4, &cid1);
+ mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF8, &cid2);
+ mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFFC, &cid3);
+ mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFCC, &memtype);
+ retval = dap_run(dap);
if (retval != ERROR_OK)
return retval;
entry_offset = 0;
do
{
- mem_ap_read_atomic_u32(swjdp, (dbgbase&0xFFFFF000) | entry_offset, &romentry);
+ mem_ap_read_atomic_u32(dap, (dbgbase&0xFFFFF000) | entry_offset, &romentry);
command_print(cmd_ctx, "\tROMTABLE[0x%x] = 0x%" PRIx32 "",entry_offset,romentry);
if (romentry&0x01)
{
component_base = (uint32_t)((dbgbase & 0xFFFFF000)
+ (int)(romentry & 0xFFFFF000));
- mem_ap_read_atomic_u32(swjdp,
+ mem_ap_read_atomic_u32(dap,
(component_base & 0xFFFFF000) | 0xFE0, &c_pid0);
- mem_ap_read_atomic_u32(swjdp,
+ mem_ap_read_atomic_u32(dap,
(component_base & 0xFFFFF000) | 0xFE4, &c_pid1);
- mem_ap_read_atomic_u32(swjdp,
+ mem_ap_read_atomic_u32(dap,
(component_base & 0xFFFFF000) | 0xFE8, &c_pid2);
- mem_ap_read_atomic_u32(swjdp,
+ mem_ap_read_atomic_u32(dap,
(component_base & 0xFFFFF000) | 0xFEC, &c_pid3);
- mem_ap_read_atomic_u32(swjdp,
+ mem_ap_read_atomic_u32(dap,
(component_base & 0xFFFFF000) | 0xFD0, &c_pid4);
- mem_ap_read_atomic_u32(swjdp,
+ mem_ap_read_atomic_u32(dap,
(component_base & 0xFFFFF000) | 0xFF0, &c_cid0);
- mem_ap_read_atomic_u32(swjdp,
+ mem_ap_read_atomic_u32(dap,
(component_base & 0xFFFFF000) | 0xFF4, &c_cid1);
- mem_ap_read_atomic_u32(swjdp,
+ mem_ap_read_atomic_u32(dap,
(component_base & 0xFFFFF000) | 0xFF8, &c_cid2);
- mem_ap_read_atomic_u32(swjdp,
+ mem_ap_read_atomic_u32(dap,
(component_base & 0xFFFFF000) | 0xFFC, &c_cid3);
component_start = component_base - 0x1000*(c_pid4 >> 4);
unsigned minor;
char *major = "Reserved", *subtype = "Reserved";
- mem_ap_read_atomic_u32(swjdp,
+ mem_ap_read_atomic_u32(dap,
(component_base & 0xfffff000) | 0xfcc,
&devtype);
minor = (devtype >> 4) & 0x0f;
{
command_print(cmd_ctx, "\tNo ROM table present");
}
- dap_ap_select(swjdp, apselold);
+ dap_ap_select(dap, apselold);
return ERROR_OK;
}
projects / fw / openocd / commitdiff