target/armv7m: change FPv4_SP and FPv5_SP/DP identifiers to uppercase

Change-Id: Ia421a973e5fb4767715c9f95c91745f8ca1de1da
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/6177
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

diff --git a/src/rtos/FreeRTOS.c b/src/rtos/FreeRTOS.c
index 4d520b9b419205ec27917371cda8d953f055e08e..f04b0a268a554f44f4dbc10d00a9ff96fbf78ebf 100644 (file)
--- a/src/rtos/FreeRTOS.c
+++ b/src/rtos/FreeRTOS.c
@@ -438,7 +438,7 @@ static int FreeRTOS_get_thread_reg_list(struct rtos *rtos, int64_t thread_id,
        int cm4_fpu_enabled = 0;
        struct armv7m_common *armv7m_target = target_to_armv7m(rtos->target);
        if (is_armv7m(armv7m_target)) {
-               if (armv7m_target->fp_feature == FPv4_SP) {
+               if (armv7m_target->fp_feature == FPV4_SP) {
                        /* Found ARM v7m target which includes a FPU */
                        uint32_t cpacr;
 

diff --git a/src/rtos/nuttx.c b/src/rtos/nuttx.c
index 6569e38f2bf93fdc344b1e7645973d2df80b0a3c..0705b17b3526259cd9441a6ed27f0a6e1ffaabeb 100644 (file)
--- a/src/rtos/nuttx.c
+++ b/src/rtos/nuttx.c
@@ -352,7 +352,7 @@ static int nuttx_get_thread_reg_list(struct rtos *rtos, int64_t thread_id,
        bool cm4_fpu_enabled = false;
        struct armv7m_common *armv7m_target = target_to_armv7m(rtos->target);
        if (is_armv7m(armv7m_target)) {
-               if (armv7m_target->fp_feature == FPv4_SP) {
+               if (armv7m_target->fp_feature == FPV4_SP) {
                        /* Found ARM v7m target which includes a FPU */
                        uint32_t cpacr;
 

diff --git a/src/target/armv7m.h b/src/target/armv7m.h
index db6f8bc5246c1ce8ce9f55c57a7ac61d97df0778..f5679b91d9b1259c32596ae3165bd3c58e73d0fd 100644 (file)
--- a/src/target/armv7m.h
+++ b/src/target/armv7m.h
@@ -169,9 +169,9 @@ enum {
 
 enum {
        FP_NONE = 0,
-       FPv4_SP,
-       FPv5_SP,
-       FPv5_DP,
+       FPV4_SP,
+       FPV5_SP,
+       FPV5_DP,
 };
 
 #define ARMV7M_NUM_CORE_REGS (ARMV7M_xPSR + 1)

diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c
index 6dc33c8673c3a4e8c2ca0bf870f30d6086de9a42..e7a2fadda744ce30d6c6207eb4fcb0091da695ff 100644 (file)
--- a/src/target/cortex_m.c
+++ b/src/target/cortex_m.c
@@ -2019,7 +2019,7 @@ int cortex_m_examine(struct target *target)
                        /* test for floating point feature on Cortex-M4 */
                        if ((mvfr0 == MVFR0_DEFAULT_M4) && (mvfr1 == MVFR1_DEFAULT_M4)) {
                                LOG_DEBUG("Cortex-M%d floating point feature FPv4_SP found", i);
-                               armv7m->fp_feature = FPv4_SP;
+                               armv7m->fp_feature = FPV4_SP;
                        }
                } else if (i == 7 || i == 33 || i == 35 || i == 55) {
                        target_read_u32(target, MVFR0, &mvfr0);
@@ -2028,10 +2028,10 @@ int cortex_m_examine(struct target *target)
                        /* test for floating point features on Cortex-M7 */
                        if ((mvfr0 == MVFR0_DEFAULT_M7_SP) && (mvfr1 == MVFR1_DEFAULT_M7_SP)) {
                                LOG_DEBUG("Cortex-M%d floating point feature FPv5_SP found", i);
-                               armv7m->fp_feature = FPv5_SP;
+                               armv7m->fp_feature = FPV5_SP;
                        } else if ((mvfr0 == MVFR0_DEFAULT_M7_DP) && (mvfr1 == MVFR1_DEFAULT_M7_DP)) {
                                LOG_DEBUG("Cortex-M%d floating point feature FPv5_DP found", i);
-                               armv7m->fp_feature = FPv5_DP;
+                               armv7m->fp_feature = FPV5_DP;
                        }
                } else if (i == 0) {
                        /* Cortex-M0 does not support unaligned memory access */