--- /dev/null
+# !!!!!!!!!!!!
+# ! UNTESTED !
+# !!!!!!!!!!!!
+
+# NXP LPC1751 Cortex-M3 with 32kB Flash and 8kB Local On-Chip SRAM,
+set CHIPNAME lpc1751
+set CPUTAPID 0x4ba00477
+set CPURAMSIZE 0x2000
+set CPUROMSIZE 0x8000
+
+# After reset the chip is clocked by the ~4MHz internal RC oscillator.
+# When board-specific code (reset-init handler or device firmware)
+# configures another oscillator and/or PLL0, set CCLK to match; if
+# you don't, then flash erase and write operations may misbehave.
+# (The ROM code doing those updates cares about core clock speed...)
+#
+# CCLK is the core clock frequency in KHz
+set CCLK 4000
+
+#Include the main configuration file.
+source [find target/lpc17xx.cfg];
--- /dev/null
+# !!!!!!!!!!!!
+# ! UNTESTED !
+# !!!!!!!!!!!!
+
+# NXP LPC1752 Cortex-M3 with 64kB Flash and 16kB Local On-Chip SRAM,
+set CHIPNAME lpc1752
+set CPUTAPID 0x4ba00477
+set CPURAMSIZE 0x4000
+set CPUROMSIZE 0x10000
+
+# After reset the chip is clocked by the ~4MHz internal RC oscillator.
+# When board-specific code (reset-init handler or device firmware)
+# configures another oscillator and/or PLL0, set CCLK to match; if
+# you don't, then flash erase and write operations may misbehave.
+# (The ROM code doing those updates cares about core clock speed...)
+#
+# CCLK is the core clock frequency in KHz
+set CCLK 4000
+
+#Include the main configuration file.
+source [find target/lpc17xx.cfg];
--- /dev/null
+# !!!!!!!!!!!!
+# ! UNTESTED !
+# !!!!!!!!!!!!
+
+# NXP LPC1754 Cortex-M3 with 128kB Flash and 16kB+16kB Local On-Chip SRAM,
+set CHIPNAME lpc1754
+set CPUTAPID 0x4ba00477
+set CPURAMSIZE 0x4000
+set CPUROMSIZE 0x20000
+
+# After reset the chip is clocked by the ~4MHz internal RC oscillator.
+# When board-specific code (reset-init handler or device firmware)
+# configures another oscillator and/or PLL0, set CCLK to match; if
+# you don't, then flash erase and write operations may misbehave.
+# (The ROM code doing those updates cares about core clock speed...)
+#
+# CCLK is the core clock frequency in KHz
+set CCLK 4000
+
+#Include the main configuration file.
+source [find target/lpc17xx.cfg];
--- /dev/null
+# !!!!!!!!!!!!
+# ! UNTESTED !
+# !!!!!!!!!!!!
+
+# NXP LPC1756 Cortex-M3 with 256kB Flash and 16kB+16kB Local On-Chip SRAM,
+set CHIPNAME lpc1756
+set CPUTAPID 0x4ba00477
+set CPURAMSIZE 0x8000
+set CPUROMSIZE 0x40000
+
+# After reset the chip is clocked by the ~4MHz internal RC oscillator.
+# When board-specific code (reset-init handler or device firmware)
+# configures another oscillator and/or PLL0, set CCLK to match; if
+# you don't, then flash erase and write operations may misbehave.
+# (The ROM code doing those updates cares about core clock speed...)
+#
+# CCLK is the core clock frequency in KHz
+set CCLK 4000
+
+#Include the main configuration file.
+source [find target/lpc17xx.cfg];
--- /dev/null
+# !!!!!!!!!!!!
+# ! UNTESTED !
+# !!!!!!!!!!!!
+
+# NXP LPC1758 Cortex-M3 with 512kB Flash and 32kB+32kB Local On-Chip SRAM,
+set CHIPNAME lpc1758
+set CPUTAPID 0x4ba00477
+set CPURAMSIZE 0x8000
+set CPUROMSIZE 0x80000
+
+# After reset the chip is clocked by the ~4MHz internal RC oscillator.
+# When board-specific code (reset-init handler or device firmware)
+# configures another oscillator and/or PLL0, set CCLK to match; if
+# you don't, then flash erase and write operations may misbehave.
+# (The ROM code doing those updates cares about core clock speed...)
+#
+# CCLK is the core clock frequency in KHz
+set CCLK 4000
+
+#Include the main configuration file.
+source [find target/lpc17xx.cfg];
--- /dev/null
+# !!!!!!!!!!!!
+# ! UNTESTED !
+# !!!!!!!!!!!!
+
+# NXP LPC1759 Cortex-M3 with 512kB Flash and 32kB+32kB Local On-Chip SRAM,
+set CHIPNAME lpc1759
+set CPUTAPID 0x4ba00477
+set CPURAMSIZE 0x8000
+set CPUROMSIZE 0x80000
+
+# After reset the chip is clocked by the ~4MHz internal RC oscillator.
+# When board-specific code (reset-init handler or device firmware)
+# configures another oscillator and/or PLL0, set CCLK to match; if
+# you don't, then flash erase and write operations may misbehave.
+# (The ROM code doing those updates cares about core clock speed...)
+#
+# CCLK is the core clock frequency in KHz
+set CCLK 4000
+
+#Include the main configuration file.
+source [find target/lpc17xx.cfg];
--- /dev/null
+# !!!!!!!!!!!!
+# ! UNTESTED !
+# !!!!!!!!!!!!
+
+# NXP LPC1763 Cortex-M3 with 256kB Flash and 32kB+32kB Local On-Chip SRAM,
+set CHIPNAME lpc1763
+set CPUTAPID 0x4ba00477
+set CPURAMSIZE 0x8000
+set CPUROMSIZE 0x40000
+
+# After reset the chip is clocked by the ~4MHz internal RC oscillator.
+# When board-specific code (reset-init handler or device firmware)
+# configures another oscillator and/or PLL0, set CCLK to match; if
+# you don't, then flash erase and write operations may misbehave.
+# (The ROM code doing those updates cares about core clock speed...)
+#
+# CCLK is the core clock frequency in KHz
+set CCLK 4000
+
+#Include the main configuration file.
+source [find target/lpc17xx.cfg];
--- /dev/null
+# !!!!!!!!!!!!
+# ! UNTESTED !
+# !!!!!!!!!!!!
+
+# NXP LPC1764 Cortex-M3 with 256kB Flash and 16kB+16kB Local On-Chip SRAM,
+set CHIPNAME lpc1764
+set CPUTAPID 0x4ba00477
+set CPURAMSIZE 0x4000
+set CPUROMSIZE 0x20000
+
+# After reset the chip is clocked by the ~4MHz internal RC oscillator.
+# When board-specific code (reset-init handler or device firmware)
+# configures another oscillator and/or PLL0, set CCLK to match; if
+# you don't, then flash erase and write operations may misbehave.
+# (The ROM code doing those updates cares about core clock speed...)
+#
+# CCLK is the core clock frequency in KHz
+set CCLK 4000
+
+#Include the main configuration file.
+source [find target/lpc17xx.cfg];
--- /dev/null
+# !!!!!!!!!!!!
+# ! UNTESTED !
+# !!!!!!!!!!!!
+
+# NXP LPC1765 Cortex-M3 with 256kB Flash and 32kB+1632kB Local On-Chip SRAM,
+set CHIPNAME lpc1765
+set CPUTAPID 0x4ba00477
+set CPURAMSIZE 0x8000
+set CPUROMSIZE 0x40000
+
+# After reset the chip is clocked by the ~4MHz internal RC oscillator.
+# When board-specific code (reset-init handler or device firmware)
+# configures another oscillator and/or PLL0, set CCLK to match; if
+# you don't, then flash erase and write operations may misbehave.
+# (The ROM code doing those updates cares about core clock speed...)
+#
+# CCLK is the core clock frequency in KHz
+set CCLK 4000
+
+#Include the main configuration file.
+source [find target/lpc17xx.cfg];
--- /dev/null
+# !!!!!!!!!!!!
+# ! UNTESTED !
+# !!!!!!!!!!!!
+
+# NXP LPC1766 Cortex-M3 with 256kB Flash and 16kB+16kB Local On-Chip SRAM,
+set CHIPNAME lpc1766
+set CPUTAPID 0x4ba00477
+set CPURAMSIZE 0x8000
+set CPUROMSIZE 0x40000
+
+# After reset the chip is clocked by the ~4MHz internal RC oscillator.
+# When board-specific code (reset-init handler or device firmware)
+# configures another oscillator and/or PLL0, set CCLK to match; if
+# you don't, then flash erase and write operations may misbehave.
+# (The ROM code doing those updates cares about core clock speed...)
+#
+# CCLK is the core clock frequency in KHz
+set CCLK 4000
+
+#Include the main configuration file.
+source [find target/lpc17xx.cfg];
--- /dev/null
+# !!!!!!!!!!!!
+# ! UNTESTED !
+# !!!!!!!!!!!!
+
+# NXP LPC1767 Cortex-M3 with 512kB Flash and 32kB+32kB Local On-Chip SRAM,
+set CHIPNAME lpc1767
+set CPUTAPID 0x4ba00477
+set CPURAMSIZE 0x8000
+set CPUROMSIZE 0x80000
+
+# After reset the chip is clocked by the ~4MHz internal RC oscillator.
+# When board-specific code (reset-init handler or device firmware)
+# configures another oscillator and/or PLL0, set CCLK to match; if
+# you don't, then flash erase and write operations may misbehave.
+# (The ROM code doing those updates cares about core clock speed...)
+#
+# CCLK is the core clock frequency in KHz
+set CCLK 4000
+
+#Include the main configuration file.
+source [find target/lpc17xx.cfg];
--- /dev/null
+# NXP LPC1769 Cortex-M3 with 512kB Flash and 32kB+32kB Local On-Chip SRAM,
+set CHIPNAME lpc1769
+set CPUTAPID 0x4ba00477
+set CPURAMSIZE 0x8000
+set CPUROMSIZE 0x80000
+
+# After reset the chip is clocked by the ~4MHz internal RC oscillator.
+# When board-specific code (reset-init handler or device firmware)
+# configures another oscillator and/or PLL0, set CCLK to match; if
+# you don't, then flash erase and write operations may misbehave.
+# (The ROM code doing those updates cares about core clock speed...)
+#
+# CCLK is the core clock frequency in KHz
+set CCLK 4000
+
+#Include the main configuration file.
+source [find target/lpc17xx.cfg];
projects / fw / openocd / commitdiff