aarch64: fix handling of 'reset halt'
authorAntonio Borneo <borneo.antonio@gmail.com>
Mon, 13 Jun 2022 14:41:11 +0000 (16:41 +0200)
committerAntonio Borneo <borneo.antonio@gmail.com>
Fri, 24 Jun 2022 21:49:25 +0000 (21:49 +0000)
Commit 6c0151623cb0 ("aarch64: add support for "reset halt"")
introduces the register setting to halt at reset vector, but:
- does not consider the case 'srst_pulls_trst' that makes useless
  setting the registers as they will be erased by the pulled trst;
- does not clean sticky errors in case of 'srst_gates_jtag'.

Avoid any register initialization on 'srst_pulls_trst' and move
the cleaning of sticky errors in the common block.

Change-Id: I6f839f06f7b091e234ede31ec18096e51f017bcd
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Fixes: 6c0151623cb0 ("aarch64: add support for "reset halt"")
Reviewed-on: https://review.openocd.org/c/openocd/+/7034
Tested-by: jenkins
Reviewed-by: Christian Hoff <christian.hoff@advantest.com>
src/target/aarch64.c

index 8a8f21d13b3088aad69a75af92de61d380858a3b..e4d420f07ab688cc134a4b5d28a600280d9c6af6 100644 (file)
@@ -1942,7 +1942,7 @@ static int aarch64_assert_reset(struct target *target)
        else if (reset_config & RESET_HAS_SRST) {
                bool srst_asserted = false;
 
-               if (target->reset_halt) {
+               if (target->reset_halt && !(reset_config & RESET_SRST_PULLS_TRST)) {
                        if (target_was_examined(target)) {
 
                                if (reset_config & RESET_SRST_NO_GATING) {
@@ -1952,12 +1952,12 @@ static int aarch64_assert_reset(struct target *target)
                                         */
                                        adapter_assert_reset();
                                        srst_asserted = true;
-
-                                       /* make sure to clear all sticky errors */
-                                       mem_ap_write_atomic_u32(armv8->debug_ap,
-                                                       armv8->debug_base + CPUV8_DBG_DRCR, DRCR_CSE);
                                }
 
+                               /* make sure to clear all sticky errors */
+                               mem_ap_write_atomic_u32(armv8->debug_ap,
+                                               armv8->debug_base + CPUV8_DBG_DRCR, DRCR_CSE);
+
                                /* set up Reset Catch debug event to halt the CPU after reset */
                                retval = aarch64_enable_reset_catch(target, true);
                                if (retval != ERROR_OK)