}
#endif
-static int cmsis_dap_swd_read_reg(uint8_t cmd, uint32_t *value)
+static int queued_retval;
+
+static void cmsis_dap_swd_read_reg(struct adiv5_dap *dap, uint8_t cmd, uint32_t *value)
{
+ if (queued_retval != ERROR_OK)
+ return;
+
uint8_t *buffer = cmsis_dap_handle->packet_buffer;
int retval;
uint32_t val;
/* TODO - need better response checking */
if (retval != ERROR_OK || buffer[1] != 0x01) {
LOG_ERROR("CMSIS-DAP: Read Error (0x%02" PRIx8 ")", buffer[2]);
- return buffer[2];
+ queued_retval = buffer[2];
+ return;
}
val = le_to_h_u32(&buffer[3]);
if (value)
*value = val;
- return retval;
+ queued_retval = retval;
}
-static int cmsis_dap_swd_write_reg(uint8_t cmd, uint32_t value)
+static void cmsis_dap_swd_write_reg(struct adiv5_dap *dap, uint8_t cmd, uint32_t value)
{
+ if (queued_retval != ERROR_OK)
+ return;
+
uint8_t *buffer = cmsis_dap_handle->packet_buffer;
DEBUG_IO("CMSIS-DAP: Write Reg 0x%02" PRIx8 " 0x%08" PRIx32, cmd, value);
retval = buffer[2];
}
+ queued_retval = retval;
+}
+
+static int cmsis_dap_swd_run(struct adiv5_dap *dap)
+{
+ int retval = queued_retval;
+ queued_retval = ERROR_OK;
return retval;
}
};
static const struct swd_driver cmsis_dap_swd_driver = {
- .init = cmsis_dap_swd_init,
- .read_reg = cmsis_dap_swd_read_reg,
- .write_reg = cmsis_dap_swd_write_reg,
+ .init = cmsis_dap_swd_init,
+ .read_reg = cmsis_dap_swd_read_reg,
+ .write_reg = cmsis_dap_swd_write_reg,
+ .run = cmsis_dap_swd_run,
};
const char *cmsis_dap_transport[] = {"cmsis-dap", NULL};
#ifndef SWD_H
#define SWD_H
+#include <target/arm_adi_v5.h>
+
/* Bits in SWD command packets, written from host to target
* first bit on the wire is START
*/
/* SWD_ACK_* bits are defined in <target/arm_adi_v5.h> */
-/*
- * FOR NOW ... SWD driver ops are synchronous and return ACK
- * status ... no queuing.
- *
- * Individual ops are request/response, and fast-fail permits much
- * better fault handling. Upper layers may queue if desired.
- */
-
struct swd_driver {
/**
- * Initialize the debug link so it can perform
- * synchronous SWD operations.
+ * Initialize the debug link so it can perform SWD operations.
* @param trn value from WCR: how many clocks
* to not drive the SWDIO line at certain points in
* the SWD protocol (at least 1 clock).
*
* As an example, this would switch a dual-mode debug adapter
* into SWD mode and out of JTAG mode.
- *
- * @return ERROR_OK on success, else a negative fault code.
+ *
+ * @return ERROR_OK on success, else a negative fault code.
*/
int (*init)(uint8_t trn);
- /**
- * Synchronous read of an AP or DP register.
- *
- * @param cmd with APnDP/RnW/addr/parity bits
- * @param where to store value to read from register
- *
- * @return SWD_ACK_* code for the transaction
- * or (negative) fault code
- */
- int (*read_reg)(uint8_t cmd, uint32_t *value);
-
- /**
- * Synchronous write of an AP or DP register.
- *
- * @param cmd with APnDP/RnW/addr/parity bits
- * @param value to be written to the register
- *
- * @return SWD_ACK_* code for the transaction
- * or (negative) fault code
- */
- int (*write_reg)(uint8_t cmd, uint32_t value);
+ /**
+ * Queued read of an AP or DP register.
+ *
+ * @param dap The DAP controlled by the SWD link.
+ * @param Command byte with APnDP/RnW/addr/parity bits
+ * @param Where to store value to read from register
+ */
+ void (*read_reg)(struct adiv5_dap *dap, uint8_t cmd, uint32_t *value);
+
+ /**
+ * Queued write of an AP or DP register.
+ *
+ * @param dap The DAP controlled by the SWD link.
+ * @param Command byte with APnDP/RnW/addr/parity bits
+ * @param Value to be written to the register
+ */
+ void (*write_reg)(struct adiv5_dap *dap, uint8_t cmd, uint32_t value);
+
+ /**
+ * Execute any queued transactions and collect the result.
+ *
+ * @param dap The DAP controlled by the SWD link.
+ * @return ERROR_OK on success, Ack response code on WAIT/FAULT
+ * or negative error code on other kinds of failure.
+ */
+ int (*run)(struct adiv5_dap *dap);
/**
* Configures data collection from the Single-wire
* is normally connected to a microcontroller's UART TX,
* but which may instead be connected to SWO for use in
* collecting ITM (and possibly ETM) trace data.
- *
- * @return ERROR_OK on success, else a negative fault code.
+ *
+ * @return ERROR_OK on success, else a negative fault code.
*/
- int *(*trace)(bool swo);
+ int *(*trace)(struct adiv5_dap *dap, bool swo);
};
int swd_init_reset(struct command_context *cmd_ctx);
const struct swd_driver *swd = jtag_interface->swd;
assert(swd);
- return swd->write_reg(swd_cmd(false, false, DP_ABORT),
- STKCMPCLR | STKERRCLR | WDERRCLR | ORUNERRCLR);
+ swd->write_reg(dap, (CMSIS_CMD_DP | CMSIS_CMD_WRITE | CMSIS_CMD_A32(DP_ABORT)),
+ STKCMPCLR | STKERRCLR | WDERRCLR | ORUNERRCLR);
+ return ERROR_OK;
}
static int cmsis_dap_queue_ap_abort(struct adiv5_dap *dap, uint8_t *ack)
const struct swd_driver *swd = jtag_interface->swd;
assert(swd);
- return swd->write_reg(swd_cmd(false, false, DP_ABORT),
- DAPABORT | STKCMPCLR | STKERRCLR | WDERRCLR | ORUNERRCLR);
+ swd->write_reg(dap, (CMSIS_CMD_DP | CMSIS_CMD_WRITE | CMSIS_CMD_A32(DP_ABORT)),
+ DAPABORT | STKCMPCLR | STKERRCLR | WDERRCLR | ORUNERRCLR);
+ return ERROR_OK;
}
static int cmsis_dap_queue_dp_read(struct adiv5_dap *dap, unsigned reg, uint32_t *data)
{
LOG_DEBUG("reg = %d", reg);
- int retval = jtag_interface->swd->read_reg(
- (CMSIS_CMD_DP | CMSIS_CMD_READ | CMSIS_CMD_A32(reg)), data);
-
- if (retval != ERROR_OK)
- cmsis_dap_clear_sticky_errors(dap);
+ const struct swd_driver *swd = jtag_interface->swd;
+ assert(swd);
- return retval;
+ swd->read_reg(dap, (CMSIS_CMD_DP | CMSIS_CMD_READ | CMSIS_CMD_A32(reg)), data);
+ return ERROR_OK;
}
static int (cmsis_dap_queue_dp_write)(struct adiv5_dap *dap, unsigned reg, uint32_t data)
data &= ~CORUNDETECT;
}
- int retval = jtag_interface->swd->write_reg(
- (CMSIS_CMD_DP | CMSIS_CMD_WRITE | CMSIS_CMD_A32(reg)), data);
-
- if (retval != ERROR_OK)
- cmsis_dap_clear_sticky_errors(dap);
+ const struct swd_driver *swd = jtag_interface->swd;
+ assert(swd);
- return retval;
+ swd->write_reg(dap, (CMSIS_CMD_DP | CMSIS_CMD_WRITE | CMSIS_CMD_A32(reg)), data);
+ return ERROR_OK;
}
/** Select the AP register bank matching bits 7:4 of reg. */
dap->ap_bank_value = select_ap_bank;
select_ap_bank |= dap->ap_current;
- return cmsis_dap_queue_dp_write(dap, DP_SELECT, select_ap_bank);
+ cmsis_dap_queue_dp_write(dap, DP_SELECT, select_ap_bank);
+ return ERROR_OK;
}
static int (cmsis_dap_queue_ap_read)(struct adiv5_dap *dap, unsigned reg, uint32_t *data)
{
- int retval = cmsis_dap_ap_q_bankselect(dap, reg);
- if (retval != ERROR_OK)
- return retval;
+ cmsis_dap_ap_q_bankselect(dap, reg);
LOG_DEBUG("reg = %d", reg);
- retval = jtag_interface->swd->read_reg(
- (CMSIS_CMD_AP | CMSIS_CMD_READ | CMSIS_CMD_A32(reg)), data);
+ const struct swd_driver *swd = jtag_interface->swd;
+ assert(swd);
- if (retval != ERROR_OK)
- cmsis_dap_clear_sticky_errors(dap);
+ swd->read_reg(dap, (CMSIS_CMD_AP | CMSIS_CMD_READ | CMSIS_CMD_A32(reg)), data);
- return retval;
+ return ERROR_OK;
}
static int (cmsis_dap_queue_ap_write)(struct adiv5_dap *dap, unsigned reg, uint32_t data)
{
-
-
/* TODO: CSW_DBGSWENABLE (bit31) causes issues for some targets
* disable until we find out why */
if (reg == AP_REG_CSW)
data &= ~CSW_DBGSWENABLE;
- int retval = cmsis_dap_ap_q_bankselect(dap, reg);
- if (retval != ERROR_OK)
- return retval;
+ cmsis_dap_ap_q_bankselect(dap, reg);
LOG_DEBUG("reg = %d, data = 0x%08" PRIx32, reg, data);
- retval = jtag_interface->swd->write_reg(
- (CMSIS_CMD_AP | CMSIS_CMD_WRITE | CMSIS_CMD_A32(reg)), data);
+ const struct swd_driver *swd = jtag_interface->swd;
+ assert(swd);
- if (retval != ERROR_OK)
- cmsis_dap_clear_sticky_errors(dap);
+ swd->write_reg(dap, (CMSIS_CMD_AP | CMSIS_CMD_WRITE | CMSIS_CMD_A32(reg)), data);
- return retval;
+ return ERROR_OK;
}
/** Executes all queued DAP operations. */
static int cmsis_dap_run(struct adiv5_dap *dap)
{
LOG_DEBUG(" ");
- /* FIXME: for now the CMSIS-DAP interface hard-wires a zero-size queue. */
- int ret;
- uint32_t ctrlstat;
-
/*
Some debug dongles do more than asked for(e.g. EDBG from
Atmel) behind the scene and issuing an AP write
differently and not guarantee to be report those failures
via status byte of the return USB packet from CMSIS-DAP, so
we need to check CTRL/STAT and if that happens to clear it.
+ Note that once the CMSIS-DAP SWD implementation starts queueing
+ transfers this will cause loss of the transfers after the
+ failed one. At least a warning is printed.
*/
- ret = cmsis_dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat);
- if (ret != ERROR_OK) {
- LOG_ERROR("Failed to read CTRL/STAT register");
- return ret;
- }
+ uint32_t ctrlstat;
+ cmsis_dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat);
- if (ctrlstat & SSTICKYERR) {
- LOG_WARNING("SSTICKYERR was set, clearing it");
- ret = cmsis_dap_clear_sticky_errors(dap);
- if (ret != ERROR_OK) {
- LOG_ERROR("Failed to clear sticky errors");
- return ret;
- }
- }
+ int retval = jtag_interface->swd->run(dap);
+
+ if (retval == ERROR_OK && (ctrlstat & SSTICKYERR))
+ LOG_WARNING("Adapter returned success despite SSTICKYERR being set.");
- return ret;
+ if (retval != ERROR_OK || (ctrlstat & SSTICKYERR))
+ cmsis_dap_clear_sticky_errors(dap);
+
+ return retval;
}
const struct dap_ops cmsis_dap_ops = {
static int cmsis_dap_select(struct command_context *ctx)
{
- LOG_DEBUG(" ");
+ LOG_DEBUG("CMSIS-ADI: cmsis_dap_select");
int retval = register_commands(ctx, NULL, cmsis_dap_handlers);
/* YUK! - but this is currently a global.... */
extern struct jtag_interface *jtag_interface;
+static bool do_sync;
-static int swd_finish_read(struct adiv5_dap *dap)
+static void swd_finish_read(struct adiv5_dap *dap)
{
const struct swd_driver *swd = jtag_interface->swd;
- int retval = ERROR_OK;
if (dap->last_read != NULL) {
- retval = swd->read_reg(swd_cmd(true, false, DP_RDBUFF), dap->last_read);
+ swd->read_reg(dap, swd_cmd(true, false, DP_RDBUFF), dap->last_read);
dap->last_read = NULL;
}
- return retval;
}
-static int (swd_queue_dp_write)(struct adiv5_dap *dap, unsigned reg,
+static int swd_queue_dp_write(struct adiv5_dap *dap, unsigned reg,
uint32_t data);
-static int swd_clear_sticky_errors(struct adiv5_dap *dap)
+static void swd_clear_sticky_errors(struct adiv5_dap *dap)
{
const struct swd_driver *swd = jtag_interface->swd;
assert(swd);
- return swd->write_reg(swd_cmd(false, false, DP_ABORT),
+ swd->write_reg(dap, swd_cmd(false, false, DP_ABORT),
STKCMPCLR | STKERRCLR | WDERRCLR | ORUNERRCLR);
}
+static int swd_run_inner(struct adiv5_dap *dap)
+{
+ const struct swd_driver *swd = jtag_interface->swd;
+
+ int retval = swd->run(dap);
+
+ if (retval != ERROR_OK) {
+ /* fault response */
+ swd_clear_sticky_errors(dap);
+ }
+
+ return retval;
+}
+
+static inline int check_sync(struct adiv5_dap *dap)
+{
+ return do_sync ? swd_run_inner(dap) : ERROR_OK;
+}
+
static int swd_queue_ap_abort(struct adiv5_dap *dap, uint8_t *ack)
{
const struct swd_driver *swd = jtag_interface->swd;
assert(swd);
- return swd->write_reg(swd_cmd(false, false, DP_ABORT),
+ swd->write_reg(dap, swd_cmd(false, false, DP_ABORT),
DAPABORT | STKCMPCLR | STKERRCLR | WDERRCLR | ORUNERRCLR);
+ return check_sync(dap);
}
/** Select the DP register bank matching bits 7:4 of reg. */
-static int swd_queue_dp_bankselect(struct adiv5_dap *dap, unsigned reg)
+static void swd_queue_dp_bankselect(struct adiv5_dap *dap, unsigned reg)
{
uint32_t select_dp_bank = (reg & 0x000000F0) >> 4;
if (reg == DP_SELECT)
- return ERROR_OK;
+ return;
if (select_dp_bank == dap->dp_bank_value)
- return ERROR_OK;
+ return;
dap->dp_bank_value = select_dp_bank;
select_dp_bank |= dap->ap_current | dap->ap_bank_value;
- return swd_queue_dp_write(dap, DP_SELECT, select_dp_bank);
+ swd_queue_dp_write(dap, DP_SELECT, select_dp_bank);
}
static int swd_queue_dp_read(struct adiv5_dap *dap, unsigned reg,
uint32_t *data)
{
- int retval;
- /* REVISIT status return vs ack ... */
const struct swd_driver *swd = jtag_interface->swd;
assert(swd);
- retval = swd_queue_dp_bankselect(dap, reg);
- if (retval != ERROR_OK)
- return retval;
+ swd_queue_dp_bankselect(dap, reg);
+ swd->read_reg(dap, swd_cmd(true, false, reg), data);
- retval = swd->read_reg(swd_cmd(true, false, reg), data);
-
- if (retval != ERROR_OK) {
- /* fault response */
- swd_clear_sticky_errors(dap);
- }
-
- return retval;
+ return check_sync(dap);
}
-static int (swd_queue_dp_write)(struct adiv5_dap *dap, unsigned reg,
+static int swd_queue_dp_write(struct adiv5_dap *dap, unsigned reg,
uint32_t data)
{
- int retval;
- /* REVISIT status return vs ack ... */
const struct swd_driver *swd = jtag_interface->swd;
assert(swd);
- retval = swd_finish_read(dap);
- if (retval != ERROR_OK)
- return retval;
-
- retval = swd_queue_dp_bankselect(dap, reg);
- if (retval != ERROR_OK)
- return retval;
-
- retval = swd->write_reg(swd_cmd(false, false, reg), data);
+ swd_finish_read(dap);
+ swd_queue_dp_bankselect(dap, reg);
+ swd->write_reg(dap, swd_cmd(false, false, reg), data);
- if (retval != ERROR_OK) {
- /* fault response */
- swd_clear_sticky_errors(dap);
- }
-
- return retval;
+ return check_sync(dap);
}
/** Select the AP register bank matching bits 7:4 of reg. */
-static int swd_queue_ap_bankselect(struct adiv5_dap *dap, unsigned reg)
+static void swd_queue_ap_bankselect(struct adiv5_dap *dap, unsigned reg)
{
uint32_t select_ap_bank = reg & 0x000000F0;
if (select_ap_bank == dap->ap_bank_value)
- return ERROR_OK;
+ return;
dap->ap_bank_value = select_ap_bank;
select_ap_bank |= dap->ap_current | dap->dp_bank_value;
- return swd_queue_dp_write(dap, DP_SELECT, select_ap_bank);
+ swd_queue_dp_write(dap, DP_SELECT, select_ap_bank);
}
-static int (swd_queue_ap_read)(struct adiv5_dap *dap, unsigned reg,
+static int swd_queue_ap_read(struct adiv5_dap *dap, unsigned reg,
uint32_t *data)
{
- /* REVISIT status return ... */
const struct swd_driver *swd = jtag_interface->swd;
assert(swd);
- int retval = swd_queue_ap_bankselect(dap, reg);
- if (retval != ERROR_OK)
- return retval;
-
- retval = swd->read_reg(swd_cmd(true, true, reg), dap->last_read);
+ swd_queue_ap_bankselect(dap, reg);
+ swd->read_reg(dap, swd_cmd(true, true, reg), dap->last_read);
dap->last_read = data;
- if (retval != ERROR_OK) {
- /* fault response */
- swd_clear_sticky_errors(dap);
- return retval;
- }
-
- return retval;
+ return check_sync(dap);
}
-static int (swd_queue_ap_write)(struct adiv5_dap *dap, unsigned reg,
+static int swd_queue_ap_write(struct adiv5_dap *dap, unsigned reg,
uint32_t data)
{
- /* REVISIT status return ... */
const struct swd_driver *swd = jtag_interface->swd;
assert(swd);
- int retval;
-
- retval = swd_finish_read(dap);
- if (retval != ERROR_OK)
- return retval;
-
- retval = swd_queue_ap_bankselect(dap, reg);
- if (retval != ERROR_OK)
- return retval;
- retval = swd->write_reg(swd_cmd(false, true, reg), data);
+ swd_finish_read(dap);
+ swd_queue_ap_bankselect(dap, reg);
+ swd->write_reg(dap, swd_cmd(false, true, reg), data);
- if (retval != ERROR_OK) {
- /* fault response */
- swd_clear_sticky_errors(dap);
- }
-
- return retval;
+ return check_sync(dap);
}
/** Executes all queued DAP operations. */
static int swd_run(struct adiv5_dap *dap)
{
- /* for now the SWD interface hard-wires a zero-size queue. */
-
- int retval = swd_finish_read(dap);
-
- /* FIXME but we still need to check and scrub
- * any hardware errors ...
- */
- return retval;
+ swd_finish_read(dap);
+ return swd_run_inner(dap);
}
const struct dap_ops swd_dap_ops = {
/* Note, debugport_init() does setup too */
- status = swd_queue_dp_read(dap, DP_IDCODE, &idcode);
-
- if (status == ERROR_OK)
- LOG_INFO("SWD IDCODE %#8.8" PRIx32, idcode);
+ swd_queue_dp_read(dap, DP_IDCODE, &idcode);
/* force clear all sticky faults */
swd_clear_sticky_errors(dap);
+ status = swd_run(dap);
+
+ if (status == ERROR_OK)
+ LOG_INFO("SWD IDCODE %#8.8" PRIx32, idcode);
+
/* this is a workaround to get polling working */
jtag_add_reset(0, 0);
#define JTAG_DP_APACC 0xB
/* three-bit ACK values for SWD access (sent LSB first) */
-#define SWD_ACK_OK 0x4
-#define SWD_ACK_WAIT 0x2
-#define SWD_ACK_FAULT 0x1
+#define SWD_ACK_OK 0x1
+#define SWD_ACK_WAIT 0x2
+#define SWD_ACK_FAULT 0x4
#define DPAP_WRITE 0
#define DPAP_READ 1
projects / fw / openocd / commitdiff