struct cortex_m_common *cortex_m = target_to_cm(bank->target);
- if (cortex_m->core_info->partno == CORTEX_M0P_PARTNO && cortex_m->armv7m.debug_ap->ap_num == 1) {
+ /* CPU2 (Cortex-M0+) is supported only with non-hla adapters because it is on AP1.
+ * Using HLA adapters armv7m.debug_ap is null, and checking ap_num triggers a segfault */
+ if (cortex_m->core_info->partno == CORTEX_M0P_PARTNO &&
+ cortex_m->armv7m.debug_ap && cortex_m->armv7m.debug_ap->ap_num == 1) {
uint32_t uid64_ids;
/* UID64 is contains
page_size_kb = 2;
num_pages = flash_size_kb / page_size_kb;
stm32l4_info->bank1_sectors = num_pages;
- if (armv7m->debug_ap->ap_num == 1)
+
+ /* CPU2 (Cortex-M0+) is supported only with non-hla adapters because it is on AP1.
+ * Using HLA adapters armv7m->debug_ap is null, and checking ap_num triggers a segfault */
+ if (armv7m->debug_ap && armv7m->debug_ap->ap_num == 1)
stm32l4_info->flash_regs = stm32wl_cpu2_flash_regs;
break;
default: