Fix typos and duplicated words in comments and strings.
Change-Id: I64282c7018462deefeeb8e5f4d0d81942425b3fc
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5758
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Christopher Head <chead@zaber.com>
* Walk the list of drivers, encapsulating the data structure type.
* Application state/context can be passed through the @c x pointer.
* @param f The callback function to invoke for each function.
- * @param x For use as private data storate, passed directly to @c f.
+ * @param x For use as private data storage, passed directly to @c f.
* @returns ERROR_OK if successful, or the non-zero return value of @c f.
* This allows a walker to terminate the loop early.
*/
} else if (s->oob_format & NAND_OOB_SW_ECC_KW) {
/*
* In this case eccpos is not used as
- * the ECC data is always stored contigously
+ * the ECC data is always stored contiguously
* at the end of the OOB area. It consists
* of 10 bytes per 512-byte data block.
*/
/* FLASHCLK_CTRL = 0x05 (enable clock for SLC flash controller) */
target_write_u32(target, 0x400040c8, 0x05);
- /* after reset set other registers of SLC so reset calling is here at the begining*/
+ /* after reset set other registers of SLC so reset calling is here at the beginning */
lpc3180_reset(nand);
/* SLC_CFG = 0x (Force nCE assert, DMA ECC enabled, ECC enabled, DMA burst enabled,
* read/write data to the SLC controller.
* - DMA descriptors will be put at start of working area,
* - Hardware generated ECC will be stored at ECC_OFFS
- * - OOB wil be read/written from/to SPARE_OFFS
+ * - OOB will be read/written from/to SPARE_OFFS
* - Actual page data will be read from/to DATA_OFFS
* There are unused holes between the used areas.
*/
}
/* after reset set other registers of SLC,
- * so reset calling is here at the begining
+ * so reset calling is here at the beginning
*/
retval = lpc32xx_reset(nand);
if (ERROR_OK != retval)
* 2. Copy generated ECC data from Register to Spare Area
* 3. X'fer next 256 bytes of data from Memory to Flash.
* 4. Copy generated ECC data from Register to Spare Area.
- * 5. X'fer 16 byets of Spare area from Memory to Flash.
+ * 5. X'fer 16 bytes of Spare area from Memory to Flash.
* Read Operation Sequence for Small Block NAND
* ----------------------------------------------------------
* 1. X'fer 256 bytes of data from Flash to Memory.
* 5. X'fer 16 bytes of Spare area from Flash to Memory.
* Write Operation Sequence for Large Block NAND
* ----------------------------------------------------------
- * 1. Steps(1-4) of Write Operations repeate for four times
+ * 1. Steps(1-4) of Write Operations repeated for four times
* which generates 16 DMA descriptors to X'fer 2048 bytes of
* data & 32 bytes of ECC data.
* 2. X'fer 64 bytes of Spare area from Memory to Flash.
* Read Operation Sequence for Large Block NAND
* ----------------------------------------------------------
- * 1. Steps(1-4) of Read Operations repeate for four times
+ * 1. Steps(1-4) of Read Operations repeated for four times
* which generates 16 DMA descriptors to X'fer 2048 bytes of
* data & 32 bytes of ECC data.
* 2. X'fer 64 bytes of Spare area from Flash to Memory.
* 2. Copy generated ECC data from Register to Spare Area
* 3. X'fer next 256 bytes of data from Memory to Flash.
* 4. Copy generated ECC data from Register to Spare Area.
- * 5. X'fer 16 byets of Spare area from Memory to Flash.
+ * 5. X'fer 16 bytes of Spare area from Memory to Flash.
* Read Operation Sequence for Small Block NAND
* ----------------------------------------------------------
* 1. X'fer 256 bytes of data from Flash to Memory.
* 5. X'fer 16 bytes of Spare area from Flash to Memory.
* Write Operation Sequence for Large Block NAND
* ----------------------------------------------------------
- * 1. Steps(1-4) of Write Operations repeate for four times
+ * 1. Steps(1-4) of Write Operations repeated for four times
* which generates 16 DMA descriptors to X'fer 2048 bytes of
* data & 32 bytes of ECC data.
* 2. X'fer 64 bytes of Spare area from Memory to Flash.
* Read Operation Sequence for Large Block NAND
* ----------------------------------------------------------
- * 1. Steps(1-4) of Read Operations repeate for four times
+ * 1. Steps(1-4) of Read Operations repeated for four times
* which generates 16 DMA descriptors to X'fer 2048 bytes of
* data & 32 bytes of ECC data.
* 2. X'fer 64 bytes of Spare area from Flash to Memory.
target_mem_base = pworking_area->address;
/*
- * Skip writting page which has all 0xFF data as this will
+ * Skip writing page which has all 0xFF data as this will
* generate 0x0 value.
*/
if (data && !oob) {
return retval;
}
- /* Write first decriptor to DMA controller */
+ /* Write first descriptor to DMA controller */
retval = target_write_memory(target, 0x31000100, 4,
sizeof(dmac_ll_t) / 4,
(uint8_t *)dmalist);
return retval;
}
- /* Write OOB decriptor to DMA controller */
+ /* Write OOB descriptor to DMA controller */
retval = target_write_memory(target, 0x31000100, 4,
sizeof(dmac_ll_t) / 4,
(uint8_t *)(&dmalist[nll-1]));
return retval;
}
- /* Write first decriptor to DMA controller */
+ /* Write first descriptor to DMA controller */
retval = target_write_memory(target, 0x31000100, 4,
sizeof(dmac_ll_t) / 4, (uint8_t *)dmalist);
if (ERROR_OK != retval) {
uint32_t gpr_register_content;
target_read_u32(target, MX3_GPR, &gpr_register_content);
if (gpr_register_content & 0x00000060) {
- LOG_ERROR("pins mode overrided by GPR");
+ LOG_ERROR("pins mode overridden by GPR");
return ERROR_FAIL;
}
}
if (oob) {
if (mx3_nf_info->flags.hw_ecc_enabled) {
/*
- * part of spare block will be overrided by hardware
+ * part of spare block will be overridden by hardware
* ECC generator
*/
- LOG_DEBUG("part of spare block will be overrided by hardware ECC generator");
+ LOG_DEBUG("part of spare block will be overridden by hardware ECC generator");
}
target_write_buffer(target, MX3_NF_SPARE_BUFFER0, oob_size, oob);
}
struct mx3_nf_controller *mx3_nf_info = nand->controller_priv;
struct target *target = nand->target;
/*
- * resets NAND flash controller in zero time ? I dont know.
+ * resets NAND flash controller in zero time ? I don't know.
*/
target_write_u16(target, MX3_NF_CFG1, MX3_NF_BIT_RESET_EN);
{
target_read_u16 (target, MX3_NF_ECCSTATUS, &ecc_status);
switch (ecc_status & 0x000c) {
case 1 << 2:
- LOG_DEBUG("main area readed with 1 (correctable) error");
+ LOG_DEBUG("main area read with 1 (correctable) error");
break;
case 2 << 2:
- LOG_DEBUG("main area readed with more than 1 (incorrectable) error");
+ LOG_DEBUG("main area read with more than 1 (incorrectable) error");
return ERROR_NAND_OPERATION_FAILED;
}
switch (ecc_status & 0x0003) {
case 1:
- LOG_DEBUG("spare area readed with 1 (correctable) error");
+ LOG_DEBUG("spare area read with 1 (correctable) error");
break;
case 2:
- LOG_DEBUG("main area readed with more than 1 (incorrectable) error");
+ LOG_DEBUG("main area read with more than 1 (incorrectable) error");
return ERROR_NAND_OPERATION_FAILED;
}
}
(nand->target->endianness == TARGET_LITTLE_ENDIAN);
/*
- * should factory bad block indicator be swaped
+ * should factory bad block indicator be swapped
* as a workaround for how the nfc handles pages.
*/
if (CMD_ARGC > 4 && strcmp(CMD_ARGV[4], "biswap") == 0) {
.name = "biswap",
.mode = COMMAND_EXEC,
.handler = handle_mxc_biswap_command,
- .help = "Turns on/off bad block information swaping from main area, "
+ .help = "Turns on/off bad block information swapping from main area, "
"without parameter query status.",
.usage = "bank_id ['enable'|'disable']",
},
mxc_nf_info->optype = MXC_NF_DATAOUT_PAGE;
break;
default:
- /* Ohter command use the default 'One page data out' FDO */
+ /* Other command use the default 'One page data out' FDO */
mxc_nf_info->optype = MXC_NF_DATAOUT_PAGE;
break;
}
if (oob) {
if (mxc_nf_info->flags.hw_ecc_enabled) {
/*
- * part of spare block will be overrided by hardware
+ * part of spare block will be overridden by hardware
* ECC generator
*/
- LOG_DEBUG("part of spare block will be overrided "
+ LOG_DEBUG("part of spare block will be overridden "
"by hardware ECC generator");
}
if (nfc_is_v1())
uint16_t work_mode = 0;
uint16_t temp;
/*
- * resets NAND flash controller in zero time ? I dont know.
+ * resets NAND flash controller in zero time ? I don't know.
*/
target_write_u16(target, MXC_NF_CFG1, MXC_NF_BIT_RESET_EN);
if (mxc_nf_info->mxc_version == MXC_VERSION_MX27)
* along with this program. If not, see <http://www.gnu.org/licenses/>. *
****************************************************************************/
-/* Some of the the lower level code was based on code supplied by
+/* Some of the lower level code was based on code supplied by
* ATMEL under this copyright. */
/* BEGIN ATMEL COPYRIGHT */
}
/**
- * Remove all chips from the internal list without distingushing which one
+ * Remove all chips from the internal list without distinguishing which one
* is owned by this bank. This simplification works only for one shot
* deallocation like current flash_free_all_banks()
*/
struct sam3_bank_private *pPrivate;
uint8_t *pagebuffer;
- /* incase we bail further below, set this to null */
+ /* in case we bail further below, set this to null */
pagebuffer = NULL;
/* ignore dumb requests */
* along with this program. If not, see <http://www.gnu.org/licenses/>. *
****************************************************************************/
-/* Some of the the lower level code was based on code supplied by
+/* Some of the lower level code was based on code supplied by
* ATMEL under this copyright. */
/* BEGIN ATMEL COPYRIGHT */
}
/**
- * Remove all chips from the internal list without distingushing which one
+ * Remove all chips from the internal list without distinguishing which one
* is owned by this bank. This simplification works only for one shot
* deallocation like current flash_free_all_banks()
*/
struct sam4_bank_private *pPrivate;
uint8_t *pagebuffer;
- /* incase we bail further below, set this to null */
+ /* in case we bail further below, set this to null */
pagebuffer = NULL;
/* ignore dumb requests */
at91sam7_info->mck_freq = tmp;
}
-/* Setup the timimg registers for nvbits or normal flash */
+/* Setup the timing registers for nvbits or normal flash */
static void at91sam7_set_flash_mode(struct flash_bank *bank, int mode)
{
uint32_t fmr, fmcn = 0, fws = 0;
/* re-calculate master clock frequency */
at91sam7_read_clock_info(t_bank);
- /* no timming */
+ /* no timing */
at91sam7_set_flash_mode(t_bank, FMR_TIMING_NONE);
/* check protect state */
/* calculate master clock frequency */
at91sam7_read_clock_info(t_bank);
- /* no timming */
+ /* no timing */
at91sam7_set_flash_mode(t_bank, FMR_TIMING_NONE);
/* check protect state */
/* calculate master clock frequency */
at91sam7_read_clock_info(t_bank);
- /* no timming */
+ /* no timing */
at91sam7_set_flash_mode(t_bank, FMR_TIMING_NONE);
/* check protect state */
#define SAMD_NVMCTRL_CTRLA 0x00 /* NVM control A register */
#define SAMD_NVMCTRL_CTRLB 0x04 /* NVM control B register */
#define SAMD_NVMCTRL_PARAM 0x08 /* NVM parameters register */
-#define SAMD_NVMCTRL_INTFLAG 0x18 /* NVM Interupt Flag Status & Clear */
+#define SAMD_NVMCTRL_INTFLAG 0x18 /* NVM Interrupt Flag Status & Clear */
#define SAMD_NVMCTRL_STATUS 0x18 /* NVM status register */
#define SAMD_NVMCTRL_ADDR 0x1C /* NVM address register */
#define SAMD_NVMCTRL_LOCK 0x20 /* NVM Lock section register */
/* NVMCTRL commands. See Table 20-4 in 42129F–SAM–10/2013 */
#define SAMD_NVM_CMD_ER 0x02 /* Erase Row */
#define SAMD_NVM_CMD_WP 0x04 /* Write Page */
-#define SAMD_NVM_CMD_EAR 0x05 /* Erase Auxilary Row */
-#define SAMD_NVM_CMD_WAP 0x06 /* Write Auxilary Page */
+#define SAMD_NVM_CMD_EAR 0x05 /* Erase Auxiliary Row */
+#define SAMD_NVM_CMD_WAP 0x06 /* Write Auxiliary Page */
#define SAMD_NVM_CMD_LR 0x40 /* Lock Region */
#define SAMD_NVM_CMD_UR 0x41 /* Unlock Region */
#define SAMD_NVM_CMD_SPRM 0x42 /* Set Power Reduction Mode */
#include <target/cortex_m.h>
/* A note to prefixing.
- * Definitions and functions ingerited from at91samd.c without
- * any change retained the original prefix samd_ so they eventualy
+ * Definitions and functions inherited from at91samd.c without
+ * any change retained the original prefix samd_ so they eventually
* may go to samd_common.h and .c
- * As currently there are olny 3 short functions identical with
+ * As currently there are only 3 short functions identical with
* the original source, no common file was created. */
#define SAME5_PAGES_PER_BLOCK 16
* along with this program. If not, see <http://www.gnu.org/licenses/>. *
***************************************************************************/
-/* Some of the the lower level code was based on code supplied by
+/* Some of the lower level code was based on code supplied by
* ATMEL under this copyright. */
/* BEGIN ATMEL COPYRIGHT */
* r6: error test pattern
*/
- /* see contib/loaders/flash/armv4_5_cfi_intel_32.s for src */
+ /* see contrib/loaders/flash/armv4_5_cfi_intel_32.s for src */
static const uint32_t word_32_code[] = {
0xe4904004, /* loop: ldr r4, [r0], #4 */
0xe5813000, /* str r3, [r1] */
0xeafffffe /* done: b -2 */
};
- /* see contib/loaders/flash/armv4_5_cfi_intel_16.s for src */
+ /* see contrib/loaders/flash/armv4_5_cfi_intel_16.s for src */
static const uint32_t word_16_code[] = {
0xe0d040b2, /* loop: ldrh r4, [r0], #2 */
0xe1c130b0, /* strh r3, [r1] */
0xeafffffe /* done: b -2 */
};
- /* see contib/loaders/flash/armv4_5_cfi_intel_8.s for src */
+ /* see contrib/loaders/flash/armv4_5_cfi_intel_8.s for src */
static const uint32_t word_8_code[] = {
0xe4d04001, /* loop: ldrb r4, [r0], #1 */
0xe5c13000, /* strb r3, [r1] */
cfi_intel_clear_status_register(bank);
- /* If we are setting up the write_algorith, we need target_code_src
+ /* If we are setting up the write_algorithm, we need target_code_src
* if not we only need target_code_size. */
/* However, we don't want to create multiple code paths, so we
if (retval != ERROR_OK) {
cfi_intel_clear_status_register(bank);
LOG_ERROR(
- "Execution of flash algorythm failed. Can't fall back. Please report.");
+ "Execution of flash algorithm failed. Can't fall back. Please report.");
retval = ERROR_FLASH_OPERATION_FAILED;
/* retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE; */
/* FIXME To allow fall back or recovery, we must save the actual status
* R10 = unlock2_addr
* R11 = unlock2_cmd */
- /* see contib/loaders/flash/armv4_5_cfi_span_32.s for src */
+ /* see contrib/loaders/flash/armv4_5_cfi_span_32.s for src */
static const uint32_t armv4_5_word_32_code[] = {
/* 00008100 <sp_32_code>: */
0xe4905004, /* ldr r5, [r0], #4 */
0xeafffffe /* b 8154 <sp_32_done> */
};
- /* see contib/loaders/flash/armv4_5_cfi_span_16.s for src */
+ /* see contrib/loaders/flash/armv4_5_cfi_span_16.s for src */
static const uint32_t armv4_5_word_16_code[] = {
/* 00008158 <sp_16_code>: */
0xe0d050b2, /* ldrh r5, [r0], #2 */
break;
}
if (retval == ERROR_OK) {
- /* Increment pointers and decrease count on succesful block write */
+ /* Increment pointers and decrease count on successful block write */
buffer += blk_count;
write_p += blk_count;
count -= blk_count;
*for
*all
*CFI
- *flashs
+ *flashes
**/
cfi_read_0002_pri_ext(bank);
break;
* @a instance is driver-specific.
* @param name_index The index to the string in args containing the
* bank identifier.
- * @param bank On output, contians a pointer to the bank or NULL.
+ * @param bank On output, contains a pointer to the bank or NULL.
* @returns ERROR_OK on success, or an error indicating the problem.
*/
COMMAND_HELPER(flash_command_get_bank, unsigned name_index,
*
* @param bank The bank to protect or unprotect.
* @param set If non-zero, enable protection; if 0, disable it.
- * @param first The first sector to (un)protect, typicaly 0.
+ * @param first The first sector to (un)protect, typically 0.
* @param last The last sector to (un)project, typically N-1.
* @returns ERROR_OK if successful; otherwise, an error code.
*/
int (*info)(struct flash_bank *bank, char *buf, int buf_size);
/**
- * A more gentle flavor of filash_driver_s::probe, performing
+ * A more gentle flavor of flash_driver_s::probe, performing
* setup with less noise. Generally, driver routines should test
* to see if the bank has already been probed; if it has, the
* driver probably should not perform its probe a second time.
*
* This callback is often called from the inside of other
* routines (e.g. GDB flash downloads) to autoprobe the flash as
- * it is programing the flash.
+ * it is programming the flash.
*
* @param bank - the bank to probe
* @returns ERROR_OK if successful; otherwise, an error code.
}
/**
- * Protection funcionality is not implemented.
+ * Protection functionality is not implemented.
* The current implementation applies/removes security on the chip.
* The chip is effectively secured/unsecured after the first reset
* following the execution of this function.
struct armv7m_algorithm armv7m_info;
int retval = ERROR_OK;
- /* see contib/loaders/flash/stm32x.s for src, the same is used here except for
+ /* see contrib/loaders/flash/stm32x.s for src, the same is used here except for
* a modified *_FLASH_BASE */
static const uint8_t em357_flash_write_code[] = {
if (retval != ERROR_OK)
return retval;
- /* FASZR = 0x01, Enables CPU Programming Mode (16-bit Flash acccess) */
+ /* FASZR = 0x01, Enables CPU Programming Mode (16-bit Flash access) */
retval = target_write_u32(target, 0x40000000, 0x0001);
if (retval != ERROR_OK)
return retval;
destroy_reg_param(®_params[1]);
destroy_reg_param(®_params[2]);
- /* FASZR = 0x02, Enables CPU Run Mode (32-bit Flash acccess) */
+ /* FASZR = 0x02, Enables CPU Run Mode (32-bit Flash access) */
retval = target_write_u32(target, 0x40000000, 0x0002);
if (retval != ERROR_OK)
return retval;
*
*/
-/* Addressess */
+/* Addresses */
#define FCF_ADDRESS 0x00000400
#define FCF_FPROT 0x8
#define FCF_FSEC 0xc
}
}
- LOG_DEBUG("MDM: halt succeded after %d attempts.", tries);
+ LOG_DEBUG("MDM: halt succeeded after %d attempts.", tries);
target_poll(target);
/* enable polling in case kinetis_check_flash_security_status disabled it */
bank_iter = k_bank->bank;
if (bank_iter == NULL) {
- LOG_WARNING("Missing bank %u configuration, FCF protection flags may be incomplette", bank_idx);
+ LOG_WARNING("Missing bank %u configuration, FCF protection flags may be incomplete", bank_idx);
continue;
}
if (result == ERROR_OK) {
bank->sectors[i].is_erased = !(ftfx_fstat & 0x01);
} else {
- LOG_DEBUG("Ignoring errored PFlash sector blank-check");
+ LOG_DEBUG("Ignoring error on PFlash sector blank-check");
kinetis_ftfx_clear_error(bank->target);
bank->sectors[i].is_erased = -1;
}
if (result == ERROR_OK) {
bank->sectors[i].is_erased = !(fstat & (FTMRX_FSTAT_MGSTAT0_MASK | FTMRX_FSTAT_MGSTAT1_MASK));
} else {
- LOG_DEBUG("Ignoring errored PFlash sector blank-check");
+ LOG_DEBUG("Ignoring error on PFlash sector blank-check");
bank->sectors[i].is_erased = -1;
}
}
break;
}
- /* Exit if error occured */
+ /* Exit if error occurred */
if (retval != ERROR_OK)
break;
break;
}
- /* Exit if error occured */
+ /* Exit if error occurred */
if (retval != ERROR_OK)
break;
for (unsigned int lockregion = first; lockregion <= last; lockregion++) {
if (set) {
- /* write an odd value to base addy to protect... */
+ /* write an odd value to base address to protect... */
value = 0x01;
} else {
- /* write an even value to base addy to unprotect... */
+ /* write an even value to base address to unprotect... */
value = 0x00;
}
target_write_u32(target, bank->sectors[lockregion].offset, value);
#define FTCTR 0x2020000C /* Flash test control */
#define FBWST 0x20200010 /* Flash bridge wait-state */
#define FCRA 0x2020001C /* Flash clock divider */
-#define FMSSTART 0x20200020 /* Flash Built-In Selft Test start address */
-#define FMSSTOP 0x20200024 /* Flash Built-In Selft Test stop address */
+#define FMSSTART 0x20200020 /* Flash Built-In Self Test start address */
+#define FMSSTOP 0x20200024 /* Flash Built-In Self Test stop address */
#define FMS16 0x20200028 /* Flash 16-bit signature */
#define FMSW0 0x2020002C /* Flash 128-bit signature Word 0 */
#define FMSW1 0x20200030 /* Flash 128-bit signature Word 1 */
/**
* Maximum contiguous block of internal SRAM (bytes).
- * Autodetected by the driver. Not the total amount of SRAM, only the
+ * Autodetected by the driver. Not the total amount of SRAM, only
* the largest \em contiguous block!
*/
uint32_t max_ram_block;
return status;
}
- /* Use the BIST (Built-In Selft Test) to generate a signature of each flash
+ /* Use the BIST (Built-In Self Test) to generate a signature of each flash
* sector. Compare against the expected signature of an empty sector.
*/
for (unsigned int sector = 0; sector < bank->num_sectors; sector++) {
unsigned int burst_size_bits;
};
-/* see contib/loaders/flash/max32xxx/max32xxx.s for src */
+/* see contrib/loaders/flash/max32xxx/max32xxx.s for src */
static const uint8_t write_code[] = {
#include "../../contrib/loaders/flash/max32xxx/max32xxx.inc"
};
#define FCIS_OP_ERROR (1<<1) /* Flag operation error */
/*---- FCIC: CLear status register */
-#define FCIC_CLR_OPCMLT (1<<0) /* Cleare completion flag in register FCIS */
-#define FCIC_CLR_OPERROR (1<<1) /* Cleare error flag in register FCIS */
+#define FCIC_CLR_OPCMLT (1<<0) /* Clear completion flag in register FCIS */
+#define FCIC_CLR_OPERROR (1<<1) /* Clear error flag in register FCIS */
/*-- USERFLASH ---------------------------------------------------------------*/
#define USERFLASH_PAGE_SIZE 256
#define UFCIS_OP_ERROR (1<<1) /* Flag operation error */
/*---- UFCIC: CLear status register */
-#define UFCIC_CLR_OPCMLT (1<<0) /* Cleared completion flag in register FCIS */
-#define UFCIC_CLR_OPERROR (1<<1) /* Cleared error flag in register FCIS */
+#define UFCIC_CLR_OPCMLT (1<<0) /* Clear completion flag in register FCIS */
+#define UFCIC_CLR_OPERROR (1<<1) /* Clear error flag in register FCIS */
/*---- In info userflash address space */
#define INFOWORD0_ADDR 0x00
return ERROR_TARGET_NOT_HALTED;
}
- LOG_INFO("Plese wait ..."); /* it`s quite a long process */
+ LOG_INFO("Please wait ..."); /* it`s quite a long process */
/* chose between main bootflash and info bootflash */
if (niietcm4_info->bflash_info_remap) {
/* dump */
/* if block write failed (no sufficient working area),
* we use normal (slow) single halfword accesses */
LOG_WARNING("Can't use block writes, falling back to single memory accesses");
- LOG_INFO("Plese wait ..."); /* it`s quite a long process */
+ LOG_INFO("Please wait ..."); /* it`s quite a long process */
/* chose between main bootflash and info bootflash */
if (niietcm4_info->bflash_info_remap)
char info_bootflash_addr_str[64];
if (niietcm4_info->bflash_info_remap)
snprintf(info_bootflash_addr_str, sizeof(info_bootflash_addr_str),
- TARGET_ADDR_FMT " base adress", bank->base);
+ TARGET_ADDR_FMT " base address", bank->base);
else
snprintf(info_bootflash_addr_str, sizeof(info_bootflash_addr_str),
- "not mapped to global adress space");
+ "not mapped to global address space");
snprintf(niietcm4_info->chip_brief,
sizeof(niietcm4_info->chip_brief),
"Bootflash :\n"
" %d kB total\n"
" %d pages %d kB each\n"
- " 0x%08x base adress\n"
+ " 0x%08x base address\n"
"%s"
"Info bootflash :\n"
" %d kB total\n"
" %d kB total\n"
" %d pages %d B each\n"
" %d bit cells\n"
- " not maped to global adress space\n"
+ " not mapped to global address space\n"
"Info userflash :\n"
" %d B total\n"
" %d pages of %d B each\n"
" %d bit cells\n"
- " not maped to global adress space\n"
+ " not mapped to global address space\n"
"RAM :\n"
" 192 kB total\n"
- " 0x20000000 base adress\n"
+ " 0x20000000 base address\n"
"External memory :\n"
" 8/16 bit address space\n"
- " 0x%08x base adress\n"
+ " 0x%08x base address\n"
"\n"
"INFOWORD STATUS\n"
"Bootflash info region remap :\n"
break;
}
- /* only fixup jedec flashs found in table */
+ /* only fixup jedec flashes found in table */
if (!non_cfi->mfr)
return;
enum nrf5_uicr_registers {
NRF5_UICR_BASE = 0x10001000, /* User Information
- * Configuration Regsters */
+ * Configuration Registers */
#define NRF5_UICR_REG(offset) (NRF5_UICR_BASE + offset)
NRF51_DEVICE_DEF(0x007A, "51422", "CEAA", "C0", 256),
NRF51_DEVICE_DEF(0x0088, "51422", "CFAC", "A0", 256),
- /* The driver fully autodects nRF52 series devices by FICR INFO,
+ /* The driver fully autodetects nRF52 series devices by FICR INFO,
* no need for nRF52xxx HWIDs in this table */
#if 0
/* nRF52810 Devices */
}
if (first != 0) {
- LOG_ERROR("Code region 0 must start at the begining of the bank");
+ LOG_ERROR("Code region 0 must start at the beginning of the bank");
return ERROR_FAIL;
}
};
/* We need to retain the flash-driver name as well as the commands
- * for backwards compatability */
+ * for backwards compatibility */
const struct flash_driver nrf51_flash = {
.name = "nrf51",
.commands = nrf5_command_handlers,
/* command/response mask */
#define OCL_CMD_MASK 0xFFFF0000L
-/* commads */
+/* commands */
#define OCL_FLASH_BLOCK 0x0CFB0000L
#define OCL_ERASE_BLOCK 0x0CEB0000L
#define OCL_ERASE_ALL 0x0CEA0000L
return ERROR_OK;
}
-/* see contib/loaders/flash/pic32mx.s for src */
+/* see contrib/loaders/flash/pic32mx.s for src */
static uint32_t pic32mx_flash_write_code[] = {
/* write: */
#include <target/algorithm.h>
#include <target/armv7m.h>
-/* device documets:
+/* device documents:
PSoC(R) 4: PSoC 4200 Family Datasheet
Document Number: 001-87197 Rev. *B Revised August 29, 2013
/* build ID as Cypress sw does:
* bit 31..16 silicon ID
* bit 15..8 revision ID (so far 0x11 for all devices)
- * bit 7..0 family ID (lowes 8 bits)
+ * bit 7..0 family ID (lowest 8 bits)
*/
if (silicon_id)
*silicon_id = ((part0 & 0x0000ffff) << 16)
#define PANTHER_DEVICE_ID 0x4008001C
/* NVL is not actually mapped to the Cortex-M address space
- * As we need a base addess different from other banks in the device
+ * As we need a base address different from other banks in the device
* we use the address of NVL programming data in Cypress images */
#define NVL_META_BASE 0x90000000
* @brief Invokes SROM API functions which are responsible for Flash operations
*
* @param target current target
- * @param req_and_params requect id of the function to invoke
+ * @param req_and_params request id of the function to invoke
* @param working_area address of memory buffer in target's memory space for SROM API parameters
* @param data_out pointer to variable which will be populated with execution status
* @return ERROR_OK in case of success, ERROR_XXX code otherwise
/** ***********************************************************************************************
* @brief Translates Protection status to string
* @param protection protection value
- * @return pointer to const string describintg protection status
+ * @return pointer to const string describing protection status
*************************************************************************************************/
static const char *protection_to_str(uint8_t protection)
{
int hr = ERROR_OK;
- /* Retrieve data from SPCIF_GEOMATRY */
+ /* Retrieve data from SPCIF_GEOMETRY */
uint32_t geom;
target_read_u32(target, PSOC6_SPCIF_GEOMETRY, &geom);
uint32_t row_sz_lg2 = (geom & 0xF0) >> 4;
* @brief Performs Program operation
* @param bank current flash bank
* @param buffer pointer to the buffer with data
- * @param offset starting offset in falsh bank
+ * @param offset starting offset in flash bank
* @param count number of bytes in buffer
* @return ERROR_OK in case of success, ERROR_XXX code otherwise
*************************************************************************************************/
const struct armv7m_common *cm = target_to_armv7m(target);
- /* PSoC6 reboots immediatelly after issuing SYSRESETREQ / VECTRESET
+ /* PSoC6 reboots immediately after issuing SYSRESETREQ / VECTRESET
* this disables SWD/JTAG pins momentarily and may break communication
* Ignoring return value of mem_ap_write_atomic_u32 seems to be ok here */
if (is_cm0) {
if (ret != ERROR_OK)
return ret;
- /* Write the inital unlock value to KEY */
+ /* Write the initial unlock value to KEY */
ret = target_write_u32(target, FLASHCTRL0_KEY,
FLASHCTRL0_KEY_INITIAL_UNLOCK);
if (ret != ERROR_OK)
sim3x_info = bank->driver_priv;
if (sim3x_info->flash_locked) {
- LOG_ERROR("Falsh is locked");
+ LOG_ERROR("Flash is locked");
return ERROR_FAIL;
}
ret = target_read_u32(target, CPUID, &val);
/* if correct value is read, then it will continue */
if (ret != ERROR_OK || (val & CPUID_CHECK_VALUE_MASK) != CPUID_CHECK_VALUE) {
- /* if correct value is'n read, then it will check SIM3X_AP_INIT_STAT register */
+ /* if correct value isn't read, then it will check SIM3X_AP_INIT_STAT register */
ret = ap_read_register(dap, SIM3X_AP_INIT_STAT, &val);
if (ret != ERROR_OK)
return ret;
if (stellaris_info->did1 == 0)
return ERROR_FLASH_BANK_NOT_PROBED;
- /* Read main and master clock freqency register */
+ /* Read main and master clock frequency register */
stellaris_read_clock_info(bank);
printed = snprintf(buf,
* chip identification and status *
***************************************************************************/
-/* Set the flash timimg register to match current clocking */
+/* Set the flash timing register to match current clocking */
static void stellaris_set_flash_timing(struct flash_bank *bank)
{
struct stellaris_flash_bank *stellaris_info = bank->driver_priv;
target_read_u32(target, FLASH_FMC, &flash_fmc);
} while (flash_fmc & FMC_ERASE);
- /* Check acess violations */
+ /* Check access violations */
target_read_u32(target, FLASH_CRIS, &flash_cris);
if (flash_cris & (AMASK)) {
LOG_WARNING("Error erasing flash page %i, flash_cris 0x%" PRIx32 "",
return ERROR_OK;
}
-/* see contib/loaders/flash/stellaris.s for src */
+/* see contrib/loaders/flash/stellaris.s for src */
static const uint8_t stellaris_write_code[] = {
/* write: */
if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
LOG_DEBUG("writing flash word-at-a-time");
} else if (retval == ERROR_FLASH_OPERATION_FAILED) {
- /* if an error occured, we examine the reason, and quit */
+ /* if an error occurred, we examine the reason, and quit */
target_read_u32(target, FLASH_CRIS, &flash_cris);
LOG_ERROR("flash writing failed with CRIS: 0x%" PRIx32 "", flash_cris);
* can be very different.
*
* To reduce testing complexity and dangers of regressions,
- * a seperate file is used for stm32fx2x.
+ * a separate file is used for stm32fx2x.
*
* Sector sizes in kiBytes:
* 1 MiByte part with 4 x 16, 1 x 64, 7 x 128.
if (retval != ERROR_OK)
return retval;
- /* FLASH_OPTCR1 has quite diffent meanings ... */
+ /* FLASH_OPTCR1 has quite different meanings ... */
if (stm32x_info->has_boot_addr) {
/* for F7xx it contains boot0 and boot1 */
stm32x_info->option_bytes.boot_addr = optiondata;
bank->prot_blocks = NULL;
}
- /* if explicitely called out as OTP bank, short circuit probe */
+ /* if explicitly called out as OTP bank, short circuit probe */
if (stm32x_is_otp(bank)) {
if (stm32x_otp_is_f7(bank)) {
otp_size_in_b = STM32F7_OTP_SIZE;
stm32l4_read_flash_reg(bank, STM32_FLASH_WRP2AR, &wrp2ar);
stm32l4_read_flash_reg(bank, STM32_FLASH_WRP2BR, &wrp2br);
} else {
- /* prevent unintialized errors */
+ /* prevent uninitialized errors */
wrp2ar = 0;
wrp2br = 0;
}
if (retval != ERROR_OK)
return retval;
- /* first we need to write any unaligned head bytes upto
+ /* first we need to write any unaligned head bytes up to
* the next 128 byte page */
if (offset % hp_nb)
struct arm_algorithm arm_algo;
int retval = ERROR_OK;
- /* see contib/loaders/flash/str7x.s for src */
+ /* see contrib/loaders/flash/str7x.s for src */
static const uint32_t str7x_flash_write_code[] = {
/* write: */
struct arm_algorithm arm_algo;
int retval = ERROR_OK;
- /* see contib/loaders/flash/str9x.s for src */
+ /* see contrib/loaders/flash/str9x.s for src */
static const uint32_t str9x_flash_write_code[] = {
/* write: */
bank->sectors[sector].is_protected = 0;
/*
- * clear status regiser, sent erase command, kickoff erase
+ * clear status register, sent erase command, kickoff erase
*/
target_write_u16(target, flashAddr, 0x0040);
LOG_DEBUG("write *(uint16_t *)0x%08" PRIx32 "=0x0040", flashAddr);
target_read_u32(target, 0xFFE8BC04, &fmmac2);
target_write_u32(target, 0xFFE8BC04, (fmmac2 & ~7) | tms470_info->ordinal);
- /* get the original sector proection flags for this bank */
+ /* get the original sector protection flags for this bank */
target_read_u32(target, 0xFFE88008, &fmbsea);
target_read_u32(target, 0xFFE8800C, &fmbseb);
bank->sectors[i].offset = i * W600_FLASH_SECSIZE;
bank->sectors[i].size = W600_FLASH_SECSIZE;
bank->sectors[i].is_erased = -1;
- /* offset 0 to W600_FLASH_PROTECT_SIZE shoule be protected */
+ /* offset 0 to W600_FLASH_PROTECT_SIZE should be protected */
bank->sectors[i].is_protected = (i < W600_FLASH_PROTECT_SIZE / W600_FLASH_SECSIZE);
}
unsigned int sectors = bank->num_sectors;
- /* On devices with 12 sectors, sectors 10 & 11 are ptected
+ /* On devices with 12 sectors, sectors 10 & 11 are protected
* together instead of individually */
if (sectors == 12)
sectors--;
}
}
- /* XMC4xxx also supports read proptection, make a note
+ /* XMC4xxx also supports read protection, make a note
* in the private driver structure */
if (protection[0] & PROCON_RPRO_MASK)
fb->read_protected = true;
projects / fw / openocd / commitdiff