* *
* LPC1700 support Copyright (C) 2009 by Audrius Urmanavicius *
* didele.deze@gmail.com *
+ * LPC11Uxx support Copyright (C) 2012 by Jared Boone, ShareBrained *
+ * Technology, jared@sharebrained.com *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
/**
* @file
- * flash programming support for NXP LPC17xx and LPC2xxx devices.
+ * flash programming support for NXP LPC11Uxx, LPC17xx and LPC2xxx devices.
*
* @todo Provide a way to update CCLK after declaring the flash bank. The value which is correct after chip reset will
* rarely still work right after the clocks switch to use the PLL (e.g. 4MHz --> 100 MHz).
*
* lpc800:
* - 810 | 1 | 2 (tested with LPC810/LPC812)
+ * lpc11u:
+ * - 11Uxx (tested with LPC11U14)
*/
typedef enum {
lpc1700,
lpc4300,
lpc800,
+ lpc11u,
} lpc2000_variant;
struct lpc2000_flash_bank {
bank->sectors[i].is_erased = -1;
bank->sectors[i].is_protected = 1;
}
+ } else if (lpc2000_info->variant == lpc11u) {
+ lpc2000_info->cmd51_max_buffer = 1024;
+ switch (bank->size) {
+ case 16 * 1024:
+ bank->num_sectors = 4;
+ break;
+ case 24 * 1024:
+ bank->num_sectors = 6;
+ break;
+ case 32 * 1024:
+ bank->num_sectors = 8;
+ break;
+ default:
+ LOG_ERROR("BUG: unknown bank->size encountered");
+ exit(-1);
+ }
+
+ bank->sectors = malloc(sizeof(struct flash_sector) * bank->num_sectors);
+
+ for (int i = 0; i < bank->num_sectors; i++) {
+ bank->sectors[i].offset = offset;
+ /* All sectors are 4kB-sized */
+ bank->sectors[i].size = 4 * 1024;
+ offset += bank->sectors[i].size;
+ bank->sectors[i].is_erased = -1;
+ bank->sectors[i].is_protected = 1;
+ }
} else {
LOG_ERROR("BUG: unknown lpc2000_info->variant encountered");
exit(-1);
/* write IAP code to working area */
switch (lpc2000_info->variant) {
case lpc800:
+ case lpc11u:
case lpc1700:
case lpc4300:
target_buffer_set_u32(target, jump_gate, ARMV4_5_T_BX(12));
switch (lpc2000_info->variant) {
case lpc800:
+ case lpc11u:
case lpc1700:
armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
armv7m_info.core_mode = ARM_MODE_THREAD;
switch (lpc2000_info->variant) {
case lpc800:
+ case lpc11u:
case lpc1700:
case lpc4300:
/* IAP stack */
lpc2000_info->cmd51_can_8192b = 0;
lpc2000_info->checksum_vector = 7;
lpc2000_info->iap_max_stack = 148;
+ } else if (strcmp(CMD_ARGV[6], "lpc11u") == 0) {
+ lpc2000_info->variant = lpc11u;
+ lpc2000_info->cmd51_dst_boundary = 256;
+ lpc2000_info->cmd51_can_256b = 1;
+ lpc2000_info->cmd51_can_8192b = 0;
+ lpc2000_info->checksum_vector = 7;
+ lpc2000_info->iap_max_stack = 128;
} else {
LOG_ERROR("unknown LPC2000 variant: %s", CMD_ARGV[6]);
free(lpc2000_info);
--- /dev/null
+# Main file for NXP LPC11Uxx Cortex-M0
+#
+# !!!!!!
+#
+# This file should not be included directly, rather
+# by the lpc11u12.cfg, lpc11u14.cfg, etc. which set the
+# needed variables to the appropriate values.
+#
+# !!!!!!
+
+# LPC11Uxx chips support both JTAG and SWD transports.
+# Adapt based on what transport is active.
+#source [find target/swj-dp.tcl]
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ error "_CHIPNAME not set. Please do not include lpc11uxx.cfg directly, but the specific chip configuration file (lpc11u12.cfg, lpc11u14.cfg, etc)."
+}
+
+# After reset the chip is clocked by the ~12MHz internal RC oscillator.
+# When board-specific code (reset-init handler or device firmware)
+# configures another oscillator and/or PLL0, set CCLK to match; if
+# you don't, then flash erase and write operations may misbehave.
+# (The ROM code doing those updates cares about core clock speed...)
+#
+# CCLK is the core clock frequency in KHz
+if { [info exists CCLK] } {
+ set _CCLK $CCLK
+} else {
+ set _CCLK 12000
+}
+
+if { [info exists CPUTAPID] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ error "_CPUTAPID not set. Please do not include lpc11uxx.cfg directly, but the specific chip configuration file (lpc11u12.cfg, lpc11u14.cfg, etc)."
+}
+
+if { [info exists CPURAMSIZE] } {
+ set _CPURAMSIZE $CPURAMSIZE
+} else {
+ error "_CPURAMSIZE not set. Please do not include lpc11uxx.cfg directly, but the specific chip configuration file (lpc11u12.cfg, lpc11u14.cfg, etc)."
+}
+
+if { [info exists CPUROMSIZE] } {
+ set _CPUROMSIZE $CPUROMSIZE
+} else {
+ error "_CPUROMSIZE not set. Please do not include lpc11uxx.cfg directly, but the specific chip configuration file (lpc11u12.cfg, lpc11u14.cfg, etc)."
+}
+
+if { [info exists TRANSPORT] } {
+ set _TRANSPORT $TRANSPORT
+} else {
+ set _TRANSPORT hla_swd
+}
+
+transport select $_TRANSPORT
+
+hla newtap $_CHIPNAME cpu -expected-id $_CPUTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME hla_target -chain-position $_TARGETNAME
+
+# The LPC11Uxx devices have 4/6/8kB of SRAM In the ARMv6-M "Code" area (at 0x10000000)
+$_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size $_CPURAMSIZE -work-area-backup 0
+
+# The LPC11Uxx devices have 16/24/32kB of flash memory, managed by ROM code
+# (including a boot loader which verifies the flash exception table's checksum).
+# flash bank <name> lpc2000 <base> <size> 0 0 <target#> <variant> <clock> [calc checksum]
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME lpc2000 0x0 $_CPUROMSIZE 0 0 $_TARGETNAME lpc11u $_CCLK calc_checksum
+
+proc lpc11u_enable_IRC {} {
+ # Turn on IRC
+ echo "LPC11U: Enabling IRC"
+
+ # Disable IRC_PD bit in the PDRUNCFG register by just turning everything on
+ mww 0x40048238 0
+
+ # Switch main clock to IRC in the MAINCLKSEL register
+ mww 0x40048070 0
+
+ # Toggle the ENA bit in the MAINCLKUEN register
+ mww 0x40048074 0
+ mww 0x40048074 1
+
+ # Set SYSAHBCLKDIV to 1
+ mww 0x40048078 1
+
+ # Enable the reset clocks in the SYSAHBCLKCTRL register
+ mww 0x40048080 0x1003f
+}
+
+$_TARGETNAME configure -event reset-init {
+ # Do not remap 0x0000-0x0200 to anything but the flash (i.e. select
+ # "User Flash Mode" where interrupt vectors are _not_ remapped,
+ # and reside in flash instead).
+ #
+ # See Table 7. System memory remap register (SYSMEMREMAP, address 0x4004 8000) bit description
+ # Bit Symbol Value Description Reset value
+ # 1:0 MAP Memory map control. 0
+ # 0x0 Boot Loader Mode. Interrupt vectors are re-mapped to Boot ROM.
+ # 0x1 User RAM Mode. Interrupt vectors are re-mapped to Static RAM.
+ # 0x2 User Flash Mode. Interrupt vectors are not re-mapped and reside in Flash.
+ # 31:2 - - Reserved. The value read from a reserved bit is not defined. NA
+
+ mww 0x40048000 0x02
+
+ lpc11u_enable_IRC
+}
+
+# if srst is not fitted use VECTRESET to
+# perform a soft reset - SYSRESETREQ is not supported
+#cortex_m reset_config vectreset
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