flash/stm32l4x: introduce stm32l4_part_info.flags for devices features

instead of adding a new member into stm32l4_part_info for every relevant
feature, .flags serves as container for the devices' features.

identified features: F_HAS_DUAL_BANK, F_USE_ALL_WRPXX, F_HAS_TZ

Change-Id: I3093e54c6509dec33043ebe6f87675198bf1967a
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/5540
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>

diff --git a/src/flash/nor/stm32l4x.c b/src/flash/nor/stm32l4x.c
index 6816381619b7dc35432cdfcd527e40216ed73e85..bfedc8d66d92001188b52779c182109474da9e48 100644 (file)
--- a/src/flash/nor/stm32l4x.c
+++ b/src/flash/nor/stm32l4x.c
@@ -116,6 +116,19 @@
 
 #define FLASH_ERASE_TIMEOUT 250
 
+
+/* relevant STM32L4 flags ****************************************************/
+#define F_NONE              0
+/* this flag indicates if the device flash is with dual bank architecture */
+#define F_HAS_DUAL_BANK     BIT(0)
+/* this flags is used for dual bank devices only, it indicates if the
+ * 4 WRPxx are usable if the device is configured in single-bank mode */
+#define F_USE_ALL_WRPXX     BIT(1)
+/* this flag indicates if the device embeds a TrustZone security feature */
+#define F_HAS_TZ            BIT(2)
+/* end of STM32L4 flags ******************************************************/
+
+
 enum stm32l4_flash_reg_index {
        STM32_FLASH_ACR_INDEX,
        STM32_FLASH_KEYR_INDEX,
@@ -167,10 +180,7 @@ struct stm32l4_part_info {
        const struct stm32l4_rev *revs;
        const size_t num_revs;
        const uint16_t max_flash_size_kb;
-       const bool has_dual_bank;
-       /* this field is used for dual bank devices only, it indicates if the
-        * 4 WRPxx are usable if the device is configured in single-bank mode */
-       const bool use_all_wrpxx;
+       const uint32_t flags; /* one bit per feature, see STM32L4 flags: macros F_XXX */
        const uint32_t flash_regs_base;
        const uint32_t *default_flash_regs;
        const uint32_t fsize_addr;
@@ -280,8 +290,7 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
          .num_revs              = ARRAY_SIZE(stm32_415_revs),
          .device_str            = "STM32L47/L48xx",
          .max_flash_size_kb     = 1024,
-         .has_dual_bank         = true,
-         .use_all_wrpxx         = false,
+         .flags                 = F_HAS_DUAL_BANK,
          .flash_regs_base       = 0x40022000,
          .default_flash_regs    = stm32l4_flash_regs,
          .fsize_addr            = 0x1FFF75E0,
@@ -294,8 +303,7 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
          .num_revs              = ARRAY_SIZE(stm32_435_revs),
          .device_str            = "STM32L43/L44xx",
          .max_flash_size_kb     = 256,
-         .has_dual_bank         = false,
-         .use_all_wrpxx         = false,
+         .flags                 = F_NONE,
          .flash_regs_base       = 0x40022000,
          .default_flash_regs    = stm32l4_flash_regs,
          .fsize_addr            = 0x1FFF75E0,
@@ -308,8 +316,7 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
          .num_revs              = ARRAY_SIZE(stm32_460_revs),
          .device_str            = "STM32G07/G08xx",
          .max_flash_size_kb     = 128,
-         .has_dual_bank         = false,
-         .use_all_wrpxx         = false,
+         .flags                 = F_NONE,
          .flash_regs_base       = 0x40022000,
          .default_flash_regs    = stm32l4_flash_regs,
          .fsize_addr            = 0x1FFF75E0,
@@ -322,8 +329,7 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
          .num_revs              = ARRAY_SIZE(stm32_461_revs),
          .device_str            = "STM32L49/L4Axx",
          .max_flash_size_kb     = 1024,
-         .has_dual_bank         = true,
-         .use_all_wrpxx         = false,
+         .flags                 = F_HAS_DUAL_BANK,
          .flash_regs_base       = 0x40022000,
          .default_flash_regs    = stm32l4_flash_regs,
          .fsize_addr            = 0x1FFF75E0,
@@ -336,8 +342,7 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
          .num_revs              = ARRAY_SIZE(stm32_462_revs),
          .device_str            = "STM32L45/L46xx",
          .max_flash_size_kb     = 512,
-         .has_dual_bank         = false,
-         .use_all_wrpxx         = false,
+         .flags                 = F_NONE,
          .flash_regs_base       = 0x40022000,
          .default_flash_regs    = stm32l4_flash_regs,
          .fsize_addr            = 0x1FFF75E0,
@@ -350,8 +355,7 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
          .num_revs              = ARRAY_SIZE(stm32_464_revs),
          .device_str            = "STM32L41/L42xx",
          .max_flash_size_kb     = 128,
-         .has_dual_bank         = false,
-         .use_all_wrpxx         = false,
+         .flags                 = F_NONE,
          .flash_regs_base       = 0x40022000,
          .default_flash_regs    = stm32l4_flash_regs,
          .fsize_addr            = 0x1FFF75E0,
@@ -364,8 +368,7 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
          .num_revs              = ARRAY_SIZE(stm32_466_revs),
          .device_str            = "STM32G03/G04xx",
          .max_flash_size_kb     = 64,
-         .has_dual_bank         = false,
-         .use_all_wrpxx         = false,
+         .flags                 = F_NONE,
          .flash_regs_base       = 0x40022000,
          .default_flash_regs    = stm32l4_flash_regs,
          .fsize_addr            = 0x1FFF75E0,
@@ -378,8 +381,7 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
          .num_revs              = ARRAY_SIZE(stm32_468_revs),
          .device_str            = "STM32G43/G44xx",
          .max_flash_size_kb     = 128,
-         .has_dual_bank         = false,
-         .use_all_wrpxx         = false,
+         .flags                 = F_NONE,
          .flash_regs_base       = 0x40022000,
          .default_flash_regs    = stm32l4_flash_regs,
          .fsize_addr            = 0x1FFF75E0,
@@ -392,8 +394,7 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
          .num_revs              = ARRAY_SIZE(stm32_469_revs),
          .device_str            = "STM32G47/G48xx",
          .max_flash_size_kb     = 512,
-         .has_dual_bank         = true,
-         .use_all_wrpxx         = true,
+         .flags                 = F_HAS_DUAL_BANK | F_USE_ALL_WRPXX,
          .flash_regs_base       = 0x40022000,
          .default_flash_regs    = stm32l4_flash_regs,
          .fsize_addr            = 0x1FFF75E0,
@@ -406,8 +407,7 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
          .num_revs              = ARRAY_SIZE(stm32_470_revs),
          .device_str            = "STM32L4R/L4Sxx",
          .max_flash_size_kb     = 2048,
-         .has_dual_bank         = true,
-         .use_all_wrpxx         = true,
+         .flags                 = F_HAS_DUAL_BANK | F_USE_ALL_WRPXX,
          .flash_regs_base       = 0x40022000,
          .default_flash_regs    = stm32l4_flash_regs,
          .fsize_addr            = 0x1FFF75E0,
@@ -420,8 +420,7 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
          .num_revs              = ARRAY_SIZE(stm32_471_revs),
          .device_str            = "STM32L4P5/L4Q5x",
          .max_flash_size_kb     = 1024,
-         .has_dual_bank         = true,
-         .use_all_wrpxx         = true,
+         .flags                 = F_HAS_DUAL_BANK | F_USE_ALL_WRPXX,
          .flash_regs_base       = 0x40022000,
          .default_flash_regs    = stm32l4_flash_regs,
          .fsize_addr            = 0x1FFF75E0,
@@ -434,8 +433,7 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
          .num_revs              = ARRAY_SIZE(stm32_472_revs),
          .device_str            = "STM32L55/L56xx",
          .max_flash_size_kb     = 512,
-         .has_dual_bank         = true,
-         .use_all_wrpxx         = true,
+         .flags                 = F_HAS_DUAL_BANK | F_USE_ALL_WRPXX | F_HAS_TZ,
          .flash_regs_base       = 0x40022000,
          .default_flash_regs    = stm32l5_ns_flash_regs,
          .fsize_addr            = 0x0BFA05E0,
@@ -448,8 +446,7 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
          .num_revs              = ARRAY_SIZE(stm32_479_revs),
          .device_str            = "STM32G49/G4Axx",
          .max_flash_size_kb     = 512,
-         .has_dual_bank         = false,
-         .use_all_wrpxx         = false,
+         .flags                 = F_NONE,
          .flash_regs_base       = 0x40022000,
          .default_flash_regs    = stm32l4_flash_regs,
          .fsize_addr            = 0x1FFF75E0,
@@ -462,8 +459,7 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
          .num_revs              = ARRAY_SIZE(stm32_495_revs),
          .device_str            = "STM32WB5x",
          .max_flash_size_kb     = 1024,
-         .has_dual_bank         = false,
-         .use_all_wrpxx         = false,
+         .flags                 = F_NONE,
          .flash_regs_base       = 0x58004000,
          .default_flash_regs    = stm32l4_flash_regs,
          .fsize_addr            = 0x1FFF75E0,
@@ -476,8 +472,7 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
          .num_revs              = ARRAY_SIZE(stm32_496_revs),
          .device_str            = "STM32WB3x",
          .max_flash_size_kb     = 512,
-         .has_dual_bank         = false,
-         .use_all_wrpxx         = false,
+         .flags                 = F_NONE,
          .flash_regs_base       = 0x58004000,
          .default_flash_regs    = stm32l4_flash_regs,
          .fsize_addr            = 0x1FFF75E0,
@@ -490,8 +485,7 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
          .num_revs              = ARRAY_SIZE(stm32_497_revs),
          .device_str            = "STM32WLEx",
          .max_flash_size_kb     = 256,
-         .has_dual_bank         = false,
-         .use_all_wrpxx         = false,
+         .flags                 = F_NONE,
          .flash_regs_base       = 0x58004000,
          .default_flash_regs    = stm32l4_flash_regs,
          .fsize_addr            = 0x1FFF75E0,
@@ -847,7 +841,7 @@ static int stm32l4_get_all_wrpxy(struct flash_bank *bank, enum stm32_bank_id dev
                        return ret;
 
                /* for some devices (like STM32L4R/S) in single-bank mode, the 4 WRPxx are usable */
-               if (stm32l4_info->part_info->use_all_wrpxx && !stm32l4_info->dual_bank_mode)
+               if ((stm32l4_info->part_info->flags & F_USE_ALL_WRPXX) && !stm32l4_info->dual_bank_mode)
                        wrp2y_sectors_offset = 0;
        }
 
@@ -1611,7 +1605,7 @@ static int stm32l4_mass_erase(struct flash_bank *bank)
 
        uint32_t action = FLASH_MER1;
 
-       if (stm32l4_info->part_info->has_dual_bank)
+       if (stm32l4_info->part_info->flags & F_HAS_DUAL_BANK)
                action |= FLASH_MER2;
 
        if (target->state != TARGET_HALTED) {
@@ -1858,7 +1852,7 @@ COMMAND_HANDLER(stm32l4_handle_wrp_info_command)
        }
 
        if (dev_bank_id == STM32_BANK2) {
-               if (!stm32l4_info->part_info->has_dual_bank) {
+               if (!(stm32l4_info->part_info->flags & F_HAS_DUAL_BANK)) {
                        LOG_ERROR("this device has no second bank");
                        return ERROR_FAIL;
                } else if (!stm32l4_info->dual_bank_mode) {