* @param outvalue points to a 32-bit (little-endian) integer
* @param invalue NULL, or points to a 32-bit (little-endian) integer
* @param ack points to where the three bit JTAG_ACK_* code will be stored
+ * @param memaccess_tck number of idle cycles to add after AP access
*/
static int adi_jtag_dp_scan(struct adiv5_dap *dap,
uint8_t instr, uint8_t reg_addr, uint8_t RnW,
- uint8_t *outvalue, uint8_t *invalue, uint8_t *ack)
+ uint8_t *outvalue, uint8_t *invalue, uint8_t *ack,
+ uint32_t memaccess_tck)
{
struct jtag_tap *tap = dap->tap;
struct scan_field fields[2];
if ((instr == JTAG_DP_APACC)
&& ((reg_addr == MEM_AP_REG_DRW)
|| ((reg_addr & 0xF0) == MEM_AP_REG_BD0))
- && (dap->ap[dap_ap_get_select(dap)].memaccess_tck != 0))
- jtag_add_runtest(dap->ap[dap_ap_get_select(dap)].memaccess_tck,
- TAP_IDLE);
+ && memaccess_tck != 0)
+ jtag_add_runtest(memaccess_tck, TAP_IDLE);
return ERROR_OK;
}
*/
static int adi_jtag_dp_scan_u32(struct adiv5_dap *dap,
uint8_t instr, uint8_t reg_addr, uint8_t RnW,
- uint32_t outvalue, uint32_t *invalue, uint8_t *ack)
+ uint32_t outvalue, uint32_t *invalue, uint8_t *ack,
+ uint32_t memaccess_tck)
{
uint8_t out_value_buf[4];
int retval;
buf_set_u32(out_value_buf, 0, 32, outvalue);
retval = adi_jtag_dp_scan(dap, instr, reg_addr, RnW,
- out_value_buf, (uint8_t *)invalue, ack);
+ out_value_buf, (uint8_t *)invalue, ack, memaccess_tck);
if (retval != ERROR_OK)
return retval;
/**
* Utility to write AP registers.
*/
-static inline int adi_jtag_ap_write_check(struct adiv5_dap *dap,
+static inline int adi_jtag_ap_write_check(struct adiv5_ap *ap,
uint8_t reg_addr, uint8_t *outvalue)
{
- return adi_jtag_dp_scan(dap, JTAG_DP_APACC, reg_addr, DPAP_WRITE,
- outvalue, NULL, NULL);
+ return adi_jtag_dp_scan(ap->dap, JTAG_DP_APACC, reg_addr, DPAP_WRITE,
+ outvalue, NULL, NULL, ap->memaccess_tck);
}
static int adi_jtag_scan_inout_check_u32(struct adiv5_dap *dap,
uint8_t instr, uint8_t reg_addr, uint8_t RnW,
- uint32_t outvalue, uint32_t *invalue)
+ uint32_t outvalue, uint32_t *invalue, uint32_t memaccess_tck)
{
int retval;
/* Issue the read or write */
retval = adi_jtag_dp_scan_u32(dap, instr, reg_addr,
- RnW, outvalue, NULL, NULL);
+ RnW, outvalue, NULL, NULL, memaccess_tck);
if (retval != ERROR_OK)
return retval;
*/
if ((RnW == DPAP_READ) && (invalue != NULL))
retval = adi_jtag_dp_scan_u32(dap, JTAG_DP_DPACC,
- DP_RDBUFF, DPAP_READ, 0, invalue, &dap->ack);
+ DP_RDBUFF, DPAP_READ, 0, invalue, &dap->ack, 0);
return retval;
}
* but collect its ACK status.
*/
retval = adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
- DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
+ DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat, 0);
if (retval != ERROR_OK)
return retval;
retval = jtag_execute_queue();
}
retval = adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
- DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
+ DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat, 0);
if (retval != ERROR_OK)
return retval;
retval = jtag_execute_queue();
retval = adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
DP_CTRL_STAT, DPAP_WRITE,
dap->dp_ctrl_stat | SSTICKYORUN
- | SSTICKYERR, NULL);
+ | SSTICKYERR, NULL, 0);
if (retval != ERROR_OK)
return retval;
retval = adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
- DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
+ DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat, 0);
if (retval != ERROR_OK)
return retval;
retval = jtag_execute_queue();
uint32_t *data)
{
return adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
- reg, DPAP_READ, 0, data);
+ reg, DPAP_READ, 0, data, 0);
}
static int jtag_dp_q_write(struct adiv5_dap *dap, unsigned reg,
uint32_t data)
{
return adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
- reg, DPAP_WRITE, data, NULL);
+ reg, DPAP_WRITE, data, NULL, 0);
}
/** Select the AP register bank matching bits 7:4 of reg. */
-static int jtag_ap_q_bankselect(struct adiv5_dap *dap, unsigned reg)
+static int jtag_ap_q_bankselect(struct adiv5_ap *ap, unsigned reg)
{
- uint32_t select_ap_bank = reg & 0x000000F0;
+ struct adiv5_dap *dap = ap->dap;
+ uint32_t select = ((uint32_t)ap->ap_num << 24) | (reg & 0x000000F0);
- if (select_ap_bank == dap->ap_bank_value)
+ if (select == dap->select)
return ERROR_OK;
- dap->ap_bank_value = select_ap_bank;
- select_ap_bank |= dap->ap_current;
+ dap->select = select;
- return jtag_dp_q_write(dap, DP_SELECT, select_ap_bank);
+ return jtag_dp_q_write(dap, DP_SELECT, select);
}
-static int jtag_ap_q_read(struct adiv5_dap *dap, unsigned reg,
+static int jtag_ap_q_read(struct adiv5_ap *ap, unsigned reg,
uint32_t *data)
{
- int retval = jtag_ap_q_bankselect(dap, reg);
+ int retval = jtag_ap_q_bankselect(ap, reg);
if (retval != ERROR_OK)
return retval;
- return adi_jtag_scan_inout_check_u32(dap, JTAG_DP_APACC, reg,
- DPAP_READ, 0, data);
+ return adi_jtag_scan_inout_check_u32(ap->dap, JTAG_DP_APACC, reg,
+ DPAP_READ, 0, data, ap->memaccess_tck);
}
-static int jtag_ap_q_write(struct adiv5_dap *dap, unsigned reg,
+static int jtag_ap_q_write(struct adiv5_ap *ap, unsigned reg,
uint32_t data)
{
uint8_t out_value_buf[4];
- int retval = jtag_ap_q_bankselect(dap, reg);
+ int retval = jtag_ap_q_bankselect(ap, reg);
if (retval != ERROR_OK)
return retval;
buf_set_u32(out_value_buf, 0, 32, data);
- return adi_jtag_ap_write_check(dap, reg, out_value_buf);
+ return adi_jtag_ap_write_check(ap, reg, out_value_buf);
}
static int jtag_ap_q_abort(struct adiv5_dap *dap, uint8_t *ack)
{
/* for JTAG, this is the only valid ABORT register operation */
return adi_jtag_dp_scan_u32(dap, JTAG_DP_ABORT,
- 0, DPAP_WRITE, 1, NULL, ack);
+ 0, DPAP_WRITE, 1, NULL, ack, 0);
}
static int jtag_dp_run(struct adiv5_dap *dap)
/* Make sure we don't try to perform any other accesses before the DPIDR read. */
dap->do_reconnect = false;
- dap->dp_bank_value = 0;
+ dap->select = 0;
swd_queue_dp_read(dap, DP_IDCODE, &idcode);
/** Select the DP register bank matching bits 7:4 of reg. */
static void swd_queue_dp_bankselect(struct adiv5_dap *dap, unsigned reg)
{
- uint32_t select_dp_bank = (reg & 0x000000F0) >> 4;
-
if (reg == DP_SELECT)
return;
- if (select_dp_bank == dap->dp_bank_value)
+ uint32_t select_dp_bank = (reg & 0x000000F0) >> 4;
+ uint32_t select = select_dp_bank
+ | (dap->select & (DP_SELECT_APSEL | DP_SELECT_APBANK));
+
+ if (select == dap->select)
return;
- dap->dp_bank_value = select_dp_bank;
- select_dp_bank |= dap->ap_current | dap->ap_bank_value;
+ dap->select = select;
- swd_queue_dp_write(dap, DP_SELECT, select_dp_bank);
+ swd_queue_dp_write(dap, DP_SELECT, select);
}
static int swd_queue_dp_read(struct adiv5_dap *dap, unsigned reg,
}
/** Select the AP register bank matching bits 7:4 of reg. */
-static void swd_queue_ap_bankselect(struct adiv5_dap *dap, unsigned reg)
+static void swd_queue_ap_bankselect(struct adiv5_ap *ap, unsigned reg)
{
- uint32_t select_ap_bank = reg & 0x000000F0;
+ struct adiv5_dap *dap = ap->dap;
+ uint32_t select = ((uint32_t)ap->ap_num << 24)
+ | (reg & 0x000000F0)
+ | (dap->select & DP_SELECT_DPBANK);
- if (select_ap_bank == dap->ap_bank_value)
+ if (select == dap->select)
return;
- dap->ap_bank_value = select_ap_bank;
- select_ap_bank |= dap->ap_current | dap->dp_bank_value;
+ dap->select = select;
- swd_queue_dp_write(dap, DP_SELECT, select_ap_bank);
+ swd_queue_dp_write(dap, DP_SELECT, select);
}
-static int swd_queue_ap_read(struct adiv5_dap *dap, unsigned reg,
+static int swd_queue_ap_read(struct adiv5_ap *ap, unsigned reg,
uint32_t *data)
{
const struct swd_driver *swd = jtag_interface->swd;
assert(swd);
+ struct adiv5_dap *dap = ap->dap;
+
int retval = swd_check_reconnect(dap);
if (retval != ERROR_OK)
return retval;
- swd_queue_ap_bankselect(dap, reg);
- swd->read_reg(swd_cmd(true, true, reg), dap->last_read, dap->ap[dap_ap_get_select(dap)].memaccess_tck);
+ swd_queue_ap_bankselect(ap, reg);
+ swd->read_reg(swd_cmd(true, true, reg), dap->last_read, ap->memaccess_tck);
dap->last_read = data;
return check_sync(dap);
}
-static int swd_queue_ap_write(struct adiv5_dap *dap, unsigned reg,
+static int swd_queue_ap_write(struct adiv5_ap *ap, unsigned reg,
uint32_t data)
{
const struct swd_driver *swd = jtag_interface->swd;
assert(swd);
+ struct adiv5_dap *dap = ap->dap;
+
int retval = swd_check_reconnect(dap);
if (retval != ERROR_OK)
return retval;
swd_finish_read(dap);
- swd_queue_ap_bankselect(dap, reg);
- swd->write_reg(swd_cmd(false, true, reg), data, dap->ap[dap_ap_get_select(dap)].memaccess_tck);
+ swd_queue_ap_bankselect(ap, reg);
+ swd->write_reg(swd_cmd(false, true, reg), data, ap->memaccess_tck);
return check_sync(dap);
}
#define IDR_JEP106_ARM 0x04760000
+#define DP_SELECT_APSEL 0xFF000000
+#define DP_SELECT_APBANK 0x000000F0
+#define DP_SELECT_DPBANK 0x0000000F
+#define DP_SELECT_INVALID 0x00FFFF00 /* Reserved bits one */
+
/**
* This represents an ARM Debug Interface (v5) Access Port (AP).
* Most common is a MEM-AP, for memory access.
uint32_t apsel;
/**
- * Cache for DP_SELECT bits identifying the current AP. A DAP may
- * connect to multiple APs, such as one MEM-AP for general access,
- * another reserved for accessing debug modules, and a JTAG-DP.
- * "-1" indicates no cached value.
+ * Cache for DP_SELECT register. A value of DP_SELECT_INVALID
+ * indicates no cached value and forces rewrite of the register.
*/
- uint32_t ap_current;
-
- /**
- * Cache for DP_SELECT bits identifying the current four-word AP
- * register bank. This caches AP register addresss bits 7:4; JTAG
- * and SWD access primitves pass address bits 3:2; bits 1:0 are zero.
- * "-1" indicates no cached value.
- */
- uint32_t ap_bank_value;
-
- /**
- * Cache for DP_SELECT bits identifying the current four-word DP
- * register bank. This caches DP register addresss bits 7:4; JTAG
- * and SWD access primitves pass address bits 3:2; bits 1:0 are zero.
- */
- uint32_t dp_bank_value;
+ uint32_t select;
/* information about current pending SWjDP-AHBAP transaction */
uint8_t ack;
uint32_t data);
/** AP register read. */
- int (*queue_ap_read)(struct adiv5_dap *dap, unsigned reg,
+ int (*queue_ap_read)(struct adiv5_ap *ap, unsigned reg,
uint32_t *data);
/** AP register write. */
- int (*queue_ap_write)(struct adiv5_dap *dap, unsigned reg,
+ int (*queue_ap_write)(struct adiv5_ap *ap, unsigned reg,
uint32_t data);
/** AP operation abort. */
AP_TYPE_AXI_AP = 0x4, /* AXI Memory-AP */
};
-/* AP selection applies to future AP transactions */
-void dap_ap_select(struct adiv5_dap *dap, uint8_t ap);
-
/**
* Queue a DP register read.
* Note that not all DP registers are readable; also, that JTAG and SWD
unsigned reg, uint32_t *data)
{
assert(ap->dap->ops != NULL);
- dap_ap_select(ap->dap, ap->ap_num);
- return ap->dap->ops->queue_ap_read(ap->dap, reg, data);
+ return ap->dap->ops->queue_ap_read(ap, reg, data);
}
/**
unsigned reg, uint32_t data)
{
assert(ap->dap->ops != NULL);
- dap_ap_select(ap->dap, ap->ap_num);
- return ap->dap->ops->queue_ap_write(ap->dap, reg, data);
+ return ap->dap->ops->queue_ap_write(ap, reg, data);
}
/**
}
}
-/** Accessor for currently selected DAP-AP number (0..255) */
-static inline uint8_t dap_ap_get_select(struct adiv5_dap *swjdp)
-{
- return (uint8_t)(swjdp->ap_current >> 24);
-}
-
/* Queued MEM-AP memory mapped single word transfers. */
int mem_ap_read_u32(struct adiv5_ap *ap,
uint32_t address, uint32_t *value);
projects / fw / openocd / commitdiff