stm32h7x.cfg: alignment with RM0399 rev3

in RM0399 rev2, there was these bits in DBGMCU_CR registers:
 - DBGSTBY_D3 : bit 7
 - DBGSTOP_D3 : bit 8

these bits have been changed to reserved in rev3

Change-Id: I9d10d90e383795dc8e25a117d59fa065dc594610
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/5861
Tested-by: jenkins
Reviewed-by: Christopher Head <chead@zaber.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

diff --git a/tcl/target/stm32h7x.cfg b/tcl/target/stm32h7x.cfg
index 43a8b024e5a3ec49154edb31d6b25c848202058a..5220af3b1c4b3d94b740a45ed6de872e9b2d63d9 100644 (file)
--- a/tcl/target/stm32h7x.cfg
+++ b/tcl/target/stm32h7x.cfg
@@ -149,8 +149,10 @@ $_CHIPNAME.cpu0 configure -event examine-end {
        stm32h7x_dbgmcu_mmw 0x004 0x00600000 0
 
        # Enable debug during low power modes (uses more power)
-       # DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP in D3, D2 & D1 Domains
-       stm32h7x_dbgmcu_mmw 0x004 0x000001BF 0
+       # DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP D1 Domain
+       stm32h7x_dbgmcu_mmw 0x004 0x00000007 0
+       # DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP D2 Domain
+       stm32h7x_dbgmcu_mmw 0x004 0x00000038 0
 
        # Stop watchdog counters during halt
        # DBGMCU_APB3FZ1 |= WWDG1