flash/nor/psoc6: remove setting of xPSR.T bit from sromalgo_prepare()

PSoC6 erases flash to 0x00 not more common 0xff, so a device
with erased flash loads xPSR.T=0 from the zeroed reset vector.
Wrong thumb bit value caused a target algorithm failed with HardFault.
The low level write to xPSR solved the problem only if xPSR cached
copy was not marked dirty.

Later commit 49bd64347a21f5e12b33c256171b3035126d1260 fixed T setting
for all Cortex-M target algorithms.

Since 49bd64 this part of code is useless as xPSR target_start_algorithm()
sets always xPSR dirty so the effect of the low level write is eliminated
(and proper setting of thumb bit is ensured in target_start_algorithm())

Change-Id: I68aea5e921fbc6203f2fe91a45f10d22869327de
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/5875
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

diff --git a/src/flash/nor/psoc6.c b/src/flash/nor/psoc6.c
index 19d483bab42424b6e21ee63d05895eb07f949d11..931404e3eab5eac75dcd4c3cef0c653383bc0977 100644 (file)
--- a/src/flash/nor/psoc6.c
+++ b/src/flash/nor/psoc6.c
@@ -151,12 +151,6 @@ static int sromalgo_prepare(struct target *target)
        if (hr != ERROR_OK)
                return hr;
 
-       /* Restore THUMB bit in xPSR register */
-       const struct armv7m_common *cm = target_to_armv7m(target);
-       hr = cm->store_core_reg_u32(target, ARMV7M_REGSEL_xPSR, 0x01000000);
-       if (hr != ERROR_OK)
-               return hr;
-
        /* Allocate Working Area for Stack and Flash algorithm */
        hr = target_alloc_working_area(target, RAM_STACK_WA_SIZE, &g_stack_area);
        if (hr != ERROR_OK)