# http://processors.wiki.ti.com/index.php/Debug_Access_Port_(DAP)
# http://processors.wiki.ti.com/index.php?title=How_to_Find_the_Silicon_Revision_of_your_OMAP35x
-# Slooow during startup
-adapter_khz 10
+set CHIPTYPE "am35x"
+source [find target/amdm37x.cfg]
+# The TI-14 JTAG connector does not have srst. CPU reset is handled in
+# hardware.
+reset_config trst_only
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME am3517
-}
-
-set JRC_TAPID 0
-
-set DAP_TAPID 0x0b86802f
-
-# Subsidiary TAP: CoreSight Debug Access Port (DAP)
-if { [info exists DAP_TAPID ] } {
- set _DAP_TAPID $DAP_TAPID
-} else {
- set _DAP_TAPID 0x0b6d602f
-}
-
-
-# Primary TAP: ICEpick-C (JTAG route controller) and boundary scan
-if { [info exists JRC_TAPID ] } {
- set _JRC_TAPID $JRC_TAPID
-} else {
- set _JRC_TAPID 0x0b7ae02f
-}
-
-# ICEpick-C ... used to route Cortex, and more not shown here
-source [find target/icepick.cfg]
-
-
-jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf \
- -expected-id $_DAP_TAPID -disable
-jtag configure $_CHIPNAME.dap -event tap-enable \
- "icepick_c_tapenable $_CHIPNAME.jrc 3"
-
-jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \
- -expected-id $_JRC_TAPID
-
-
-
-# GDB target: Cortex-A8, using DAP
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_a8 -chain-position $_CHIPNAME.dap
-
-# SRAM: 64K at 0x4020.0000; use the first 16K
-$_TARGETNAME configure -work-area-phys 0x40200000 -work-area-size 0x4000
-
-###################
-
-# the reset sequence is event-driven
-# and kind of finicky...
-
-# some TCK tycles are required to activate the DEBUG power domain
-jtag configure $_CHIPNAME.jrc -event post-reset "runtest 100"
-
-# have the DAP "always" be active
-jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.dap"
-
-proc omap3_dbginit {target} {
-
- # General Cortex A8 debug initialisation
- cortex_a8 dbginit
- # Enable DBGU signal for OMAP353x
- $target mww phys 0x5401d030 0x00002000
-}
-
-# be absolutely certain the JTAG clock will work with the worst-case
-# 16.8MHz/2 = 8.4MHz core clock, even before a bootloader kicks in.
-# OK to speed up *after* PLL and clock tree setup.
-
-$_TARGETNAME configure -event "reset-start" { adapter_khz 10}
-
-# Assume SRST is unavailable (e.g. TI-14 JTAG), so we must assert reset
-# ourselves using PRM_RSTCTRL. RST_GS (2) is a warm reset, like ICEpick
-# would issue. RST_DPLL3 (4) is a cold reset.
-set PRM_RSTCTRL 0x48307250
-$_TARGETNAME configure -event reset-assert "$_TARGETNAME mww phys $PRM_RSTCTRL 2"
-
-$_TARGETNAME configure -event reset-assert-post "omap3_dbginit $_TARGETNAME; adapter_khz 1000"
-
+# "amdm37x_dbginit am35x.cpu" needs to be run after init.
-reset_config trst_only
--- /dev/null
+#
+# Copyright (C) 2010 by Karl Kurbjun
+# Copyright (C) 2009, 2010 by Øyvind Harboe
+# Copyright (C) 2009 by David Brownell
+# Copyright (C) 2009 by Magnus Lundin
+#
+# TI AM/DM37x
+# http://www.ti.com/litv/pdf/sprugn4b
+#
+# This script is based on the AM3517 initialization. It should be considered
+# preliminary since it needs more complete testing and only the basic
+# operations work.
+#
+
+###############################################################################
+# User modifiable parameters
+###############################################################################
+
+# This script uses the variable CHIPTYPE to determine whether this is an AM35x
+# or DM37x target. If CHIPTYPE is not set it will error out.
+if { [info exists CHIPTYPE] } {
+
+ if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+ } else {
+ set _CHIPNAME $CHIPTYPE
+ }
+
+ switch $CHIPTYPE {
+ dm37x {
+ # Primary TAP: ICEpick-C (JTAG route controller) and boundary scan
+ set _JRC_TAPID 0x0b89102f
+ }
+ am35x {
+ # Primary TAP: ICEpick-C (JTAG route controller) and boundary scan
+ set _JRC_TAPID 0x0b7ae02f
+ }
+ default {
+ error "ERROR: CHIPTYPE was set, but it was not set to a valid value. Acceptable values are \"dm37x\" or \"am35x\"."
+ }
+ }
+} else {
+ error "ERROR: CHIPTYPE was not defined. Please set CHIPTYPE to \"am35x\" for the AM35x or \"dm37x\" for the DM37x series in the board configuration."
+}
+
+# Run the adapter at the fastest acceptable speed with the slowest possible
+# core clock.
+adapter_khz 10
+
+###############################################################################
+# JTAG setup
+# The OpenOCD commands are described in the TAP Declaration section
+# http://openocd.berlios.de/doc/html/TAP-Declaration.html
+###############################################################################
+
+# The AM/DM37x has an ICEpick module in it like many of TI's other devices. More
+# can be read about this module in sprugn4b under chapter 27: "Debug and
+# Emulation". The module is used to route the JTAG chain to the various
+# subsystems in the chip.
+source [find target/icepick.cfg]
+
+# The TAP order should be described from the TDO connection in OpenOCD to the
+# TDI pin. The OpenOCD FAQ describes this in more detail:
+# http://openocd.berlios.de/doc/html/FAQ.html
+
+# From SPRUGN4B CH27 the available secondary TAPs are in this order from TDO:
+#
+# Device | TAP number
+# ---------|------------
+# DAP | 3
+# Sequencer| 2 Note: The sequencer is an ARM968
+# DSP | 1
+# D2D | 0
+#
+# Right now the only secondary tap enabled is the DAP so the rest are left
+# undescribed.
+
+######
+# Start of Chain Description
+# The Secondary TAPs all have enable functions defined for use with the ICEpick
+# Only the DAP is enabled. The AM37xx does not have the Sequencer or DSP but
+# the TAP numbers for ICEpick do not change.
+#
+# TODO: A disable function should also be added.
+######
+
+# Secondary TAP: DAP is closest to the TDO output
+# The TAP enable event also needs to be described
+jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf -disable
+jtag configure $_CHIPNAME.dap -event tap-enable \
+ "icepick_c_tapenable $_CHIPNAME.jrc 3"
+
+# These taps are only present in the DM37x series.
+if { $CHIPTYPE == "dm37x" } {
+ # Secondary TAP: Sequencer (ARM968) it is not in the chain by default
+ # The ICEpick can be used to enable it in the chain.
+ jtag newtap $_CHIPNAME arm2 -irlen 4 -ircapture 0x1 -irmask 0x0f -disable
+ jtag configure $_CHIPNAME.arm2 -event tap-enable \
+ "icepick_c_tapenable $_CHIPNAME.jrc 2"
+
+ # Secondary TAP: C64x+ DSP - it is not in the chain by default (-disable)
+ # The ICEpick can be used to enable it in the chain.
+ jtag newtap $_CHIPNAME dsp -irlen 38 -ircapture 0x25 -irmask 0x3f -disable
+ jtag configure $_CHIPNAME.dsp -event tap-enable \
+ "icepick_c_tapenable $_CHIPNAME.jrc 1"
+}
+
+# Secondary TAP: D2D it is not in the chain by default (-disable)
+# The ICEpick can be used to enable it in the chain.
+# This IRLEN is probably incorrect - not sure where the documentation is.
+jtag newtap $_CHIPNAME d2d -irlen 4 -ircapture 0x1 -irmask 0x0f -disable
+jtag configure $_CHIPNAME.d2d -event tap-enable \
+ "icepick_c_tapenable $_CHIPNAME.jrc 0"
+
+# Primary TAP: ICEpick - it is closest to TDI so last in the chain
+jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \
+ -expected-id $_JRC_TAPID
+
+######
+# End of Chain Description
+######
+
+######
+# Start JTAG TAP events
+######
+
+# some TCK tycles are required to activate the DEBUG power domain
+jtag configure $_CHIPNAME.jrc -event post-reset "runtest 100"
+
+# Enable the DAP TAP
+jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.dap"
+
+######
+# End JTAG TAP events
+######
+
+###############################################################################
+# Target Setup:
+# This section is described in the OpenOCD documentation under CPU Configuration
+# http://openocd.berlios.de/doc/html/CPU-Configuration.html
+###############################################################################
+
+# Create the CPU target to be used with GDB: Cortex-A8, using DAP
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_a8 -chain-position $_CHIPNAME.dap
+
+# The DM37x has 64K of SRAM starting at address 0x4020_0000. Allow the first
+# 16K to be used as a scratchpad for OpenOCD.
+
+$_TARGETNAME configure -work-area-phys 0x40200000 -work-area-size 0x4000
+
+######
+# Start Target Reset Event Setup:
+######
+
+# Set the JTAG clock down to 10 kHz to be sure that it will work with the
+# slowest possible core clock (16.8MHz/2 = 8.4MHz). It is OK to speed up
+# *after* PLL and clock tree setup.
+
+$_TARGETNAME configure -event "reset-start" { adapter_khz 10 }
+
+# Reset needs to be performed in in software.
+# The AM/DM37x TRM (sprugn4b) describes the software reset in detail.
+# PRM_RSTCTRL is described in table 3-425 on page 618. We assert RST_GS
+# (bit 1 (in 31:0) ) to do a warm reset.
+
+# Create a vaiable for the register address
+set PRM_RSTCTRL 0x48307250
+
+# Describe the reset assert process: A value of 2 must be written
+# (assert bit 1) to the physical address of PRM_RSTCTRL.
+
+$_TARGETNAME configure -event \
+ reset-assert "$_TARGETNAME mww phys $PRM_RSTCTRL 2"
+
+# After the reset is asserted we need to re-initialize debugging and speed up
+# the JTAG clock.
+
+$_TARGETNAME configure -event \
+ reset-assert-post "amdm37x_dbginit $_TARGETNAME; adapter_khz 1000"
+
+######
+# End Target Reset Event Setup:
+######
+
+###############################################################################
+# Target Functions
+# Add any functions needed for the target here
+###############################################################################
+
+# Run this to enable invasive debugging. This is run automatically in the
+# reset sequence.
+proc amdm37x_dbginit {target} {
+ # General Cortex A8 debug initialisation
+ cortex_a8 dbginit
+
+ # Enable DBGEN signal. This signal is described in the ARM v7 TRM, but
+ # access to the signal appears to be implementation specific. TI does not
+ # describe this register much except a quick line that states DBGEM (sic) is
+ # at this address and this bit.
+ $target mww phys 0x5401d030 0x00002000
+}
+
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