Make messages reference "DAP" if they're actually transport-agnostic, or
"JTAG-DP" when they're JTAG-specific. Saying SWJ-DP is often wrong (on
most Cortex-A8 chips) and is confusing even if correct (since we don't
yet support SWD).
Rename a JTAG-specific routine to jtagdp_transaction_endcheck() to highlight
that it's JTAG-specific, and that identify DAP clients undesirably depending
on JTAG. (They will all need to change for SWD support.)
Shrink a few overlong lines of code. Copy a comment from code removed
in a previous patch (for the ARMv7-M "dap baseaddr" command).
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
*/
if ((instr == JTAG_DP_APACC)
&& (swjdp->trans_mode == TRANS_MODE_ATOMIC))
*/
if ((instr == JTAG_DP_APACC)
&& (swjdp->trans_mode == TRANS_MODE_ATOMIC))
- return swjdp_transaction_endcheck(swjdp);
+ return jtagdp_transaction_endcheck(swjdp);
*/
if ((instr == JTAG_DP_APACC)
&& (swjdp->trans_mode == TRANS_MODE_ATOMIC))
*/
if ((instr == JTAG_DP_APACC)
&& (swjdp->trans_mode == TRANS_MODE_ATOMIC))
- return swjdp_transaction_endcheck(swjdp);
+ return jtagdp_transaction_endcheck(swjdp);
-int swjdp_transaction_endcheck(struct swjdp_common *swjdp)
+int jtagdp_transaction_endcheck(struct swjdp_common *swjdp)
{
int retval;
uint32_t ctrlstat;
{
int retval;
uint32_t ctrlstat;
/* Check for STICKYERR and STICKYORUN */
if (ctrlstat & (SSTICKYORUN | SSTICKYERR))
{
/* Check for STICKYERR and STICKYORUN */
if (ctrlstat & (SSTICKYORUN | SSTICKYERR))
{
- LOG_DEBUG("swjdp: CTRL/STAT error 0x%" PRIx32 "", ctrlstat);
+ LOG_DEBUG("jtag-dp: CTRL/STAT error, 0x%" PRIx32, ctrlstat);
/* Check power to debug regions */
if ((ctrlstat & 0xf0000000) != 0xf0000000)
{
/* Check power to debug regions */
if ((ctrlstat & 0xf0000000) != 0xf0000000)
{
uint32_t mem_ap_csw, mem_ap_tar;
/* Print information about last AHBAP access */
uint32_t mem_ap_csw, mem_ap_tar;
/* Print information about last AHBAP access */
- LOG_ERROR("AHBAP Cached values: dp_select 0x%" PRIx32 ", ap_csw 0x%" PRIx32 ", ap_tar 0x%" PRIx32 "", swjdp->dp_select_value, swjdp->ap_csw_value, swjdp->ap_tar_value);
+ LOG_ERROR("AHBAP Cached values: dp_select 0x%" PRIx32
+ ", ap_csw 0x%" PRIx32 ", ap_tar 0x%" PRIx32,
+ swjdp->dp_select_value, swjdp->ap_csw_value,
+ swjdp->ap_tar_value);
if (ctrlstat & SSTICKYORUN)
LOG_ERROR("JTAG-DP OVERRUN - "
"check clock or reduce jtag speed");
if (ctrlstat & SSTICKYORUN)
LOG_ERROR("JTAG-DP OVERRUN - "
"check clock or reduce jtag speed");
if ((retval = jtag_execute_queue()) != ERROR_OK)
return retval;
if ((retval = jtag_execute_queue()) != ERROR_OK)
return retval;
- LOG_DEBUG("swjdp: status 0x%" PRIx32 "", ctrlstat);
+ LOG_DEBUG("jtag-dp: CTRL/STAT 0x%" PRIx32, ctrlstat);
dap_ap_read_reg_u32(swjdp, AP_REG_CSW, &mem_ap_csw);
dap_ap_read_reg_u32(swjdp, AP_REG_TAR, &mem_ap_tar);
if ((retval = jtag_execute_queue()) != ERROR_OK)
return retval;
dap_ap_read_reg_u32(swjdp, AP_REG_CSW, &mem_ap_csw);
dap_ap_read_reg_u32(swjdp, AP_REG_TAR, &mem_ap_tar);
if ((retval = jtag_execute_queue()) != ERROR_OK)
return retval;
- LOG_ERROR("Read MEM_AP_CSW 0x%" PRIx32 ", MEM_AP_TAR 0x%" PRIx32 "", mem_ap_csw, mem_ap_tar);
+ LOG_ERROR("MEM_AP_CSW 0x%" PRIx32 ", MEM_AP_TAR 0x%"
+ PRIx32, mem_ap_csw, mem_ap_tar);
}
if ((retval = jtag_execute_queue()) != ERROR_OK)
}
if ((retval = jtag_execute_queue()) != ERROR_OK)
csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT;
if (csw != swjdp->ap_csw_value)
{
csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT;
if (csw != swjdp->ap_csw_value)
{
- /* LOG_DEBUG("swjdp : Set CSW %x",csw); */
+ /* LOG_DEBUG("DAP: Set CSW %x",csw); */
dap_ap_write_reg_u32(swjdp, AP_REG_CSW, csw);
swjdp->ap_csw_value = csw;
}
if (tar != swjdp->ap_tar_value)
{
dap_ap_write_reg_u32(swjdp, AP_REG_CSW, csw);
swjdp->ap_csw_value = csw;
}
if (tar != swjdp->ap_tar_value)
{
- /* LOG_DEBUG("swjdp : Set TAR %x",tar); */
+ /* LOG_DEBUG("DAP: Set TAR %x",tar); */
dap_ap_write_reg_u32(swjdp, AP_REG_TAR, tar);
swjdp->ap_tar_value = tar;
}
dap_ap_write_reg_u32(swjdp, AP_REG_TAR, tar);
swjdp->ap_tar_value = tar;
}
{
mem_ap_read_u32(swjdp, address, value);
{
mem_ap_read_u32(swjdp, address, value);
- return swjdp_transaction_endcheck(swjdp);
+ return jtagdp_transaction_endcheck(swjdp);
}
/*****************************************************************************
}
/*****************************************************************************
{
mem_ap_write_u32(swjdp, address, value);
{
mem_ap_write_u32(swjdp, address, value);
- return swjdp_transaction_endcheck(swjdp);
+ return jtagdp_transaction_endcheck(swjdp);
}
/*****************************************************************************
}
/*****************************************************************************
dap_ap_write_reg(swjdp, AP_REG_DRW, buffer + 4 * writecount);
}
dap_ap_write_reg(swjdp, AP_REG_DRW, buffer + 4 * writecount);
}
- if (swjdp_transaction_endcheck(swjdp) == ERROR_OK)
+ if (jtagdp_transaction_endcheck(swjdp) == ERROR_OK)
{
wcount = wcount - blocksize;
address = address + 4 * blocksize;
{
wcount = wcount - blocksize;
address = address + 4 * blocksize;
memcpy(&outvalue, buffer, sizeof(uint32_t));
dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
memcpy(&outvalue, buffer, sizeof(uint32_t));
dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
- if (swjdp_transaction_endcheck(swjdp) != ERROR_OK)
+ if (jtagdp_transaction_endcheck(swjdp) != ERROR_OK)
{
LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
return ERROR_JTAG_DEVICE_ERROR;
{
LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
return ERROR_JTAG_DEVICE_ERROR;
memcpy(&svalue, buffer, sizeof(uint16_t));
uint32_t outvalue = (uint32_t)svalue << 8 * (address & 0x3);
dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
memcpy(&svalue, buffer, sizeof(uint16_t));
uint32_t outvalue = (uint32_t)svalue << 8 * (address & 0x3);
dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
- retval = swjdp_transaction_endcheck(swjdp);
+ retval = jtagdp_transaction_endcheck(swjdp);
count -= 2;
address += 2;
buffer += 2;
count -= 2;
address += 2;
buffer += 2;
memcpy(&outvalue, buffer, sizeof(uint32_t));
dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
memcpy(&outvalue, buffer, sizeof(uint32_t));
dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
- if (swjdp_transaction_endcheck(swjdp) != ERROR_OK)
+ if (jtagdp_transaction_endcheck(swjdp) != ERROR_OK)
{
LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
return ERROR_JTAG_DEVICE_ERROR;
{
LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
return ERROR_JTAG_DEVICE_ERROR;
dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
uint32_t outvalue = (uint32_t)*buffer << 8 * (address & 0x3);
dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
uint32_t outvalue = (uint32_t)*buffer << 8 * (address & 0x3);
dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
- retval = swjdp_transaction_endcheck(swjdp);
+ retval = jtagdp_transaction_endcheck(swjdp);
count--;
address++;
buffer++;
count--;
address++;
buffer++;
adi_jtag_dp_scan(swjdp, JTAG_DP_DPACC, DP_RDBUFF,
DPAP_READ, 0, buffer + 4 * readcount,
&swjdp->ack);
adi_jtag_dp_scan(swjdp, JTAG_DP_DPACC, DP_RDBUFF,
DPAP_READ, 0, buffer + 4 * readcount,
&swjdp->ack);
- if (swjdp_transaction_endcheck(swjdp) == ERROR_OK)
+ if (jtagdp_transaction_endcheck(swjdp) == ERROR_OK)
{
wcount = wcount - blocksize;
address += 4 * blocksize;
{
wcount = wcount - blocksize;
address += 4 * blocksize;
do
{
dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue);
do
{
dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue);
- if (swjdp_transaction_endcheck(swjdp) != ERROR_OK)
+ if (jtagdp_transaction_endcheck(swjdp) != ERROR_OK)
{
LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
return ERROR_JTAG_DEVICE_ERROR;
{
LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
return ERROR_JTAG_DEVICE_ERROR;
{
dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue);
{
dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue);
- retval = swjdp_transaction_endcheck(swjdp);
+ retval = jtagdp_transaction_endcheck(swjdp);
if (address & 0x1)
{
for (i = 0; i < 2; i++)
if (address & 0x1)
{
for (i = 0; i < 2; i++)
do
{
dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue);
do
{
dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue);
- if (swjdp_transaction_endcheck(swjdp) != ERROR_OK)
+ if (jtagdp_transaction_endcheck(swjdp) != ERROR_OK)
{
LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
return ERROR_JTAG_DEVICE_ERROR;
{
LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
return ERROR_JTAG_DEVICE_ERROR;
{
dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue);
{
dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue);
- retval = swjdp_transaction_endcheck(swjdp);
+ retval = jtagdp_transaction_endcheck(swjdp);
*((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
count--;
address++;
*((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
count--;
address++;
/* Check that we have debug power domains activated */
while (!(ctrlstat & CDBGPWRUPACK) && (cnt++ < 10))
{
/* Check that we have debug power domains activated */
while (!(ctrlstat & CDBGPWRUPACK) && (cnt++ < 10))
{
- LOG_DEBUG("swjdp: wait CDBGPWRUPACK");
+ LOG_DEBUG("DAP: wait CDBGPWRUPACK");
dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT);
if ((retval = jtag_execute_queue()) != ERROR_OK)
return retval;
dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT);
if ((retval = jtag_execute_queue()) != ERROR_OK)
return retval;
while (!(ctrlstat & CSYSPWRUPACK) && (cnt++ < 10))
{
while (!(ctrlstat & CSYSPWRUPACK) && (cnt++ < 10))
{
- LOG_DEBUG("swjdp: wait CSYSPWRUPACK");
+ LOG_DEBUG("DAP: wait CSYSPWRUPACK");
dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT);
if ((retval = jtag_execute_queue()) != ERROR_OK)
return retval;
dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT);
if ((retval = jtag_execute_queue()) != ERROR_OK)
return retval;
dap_ap_select(swjdp, apsel);
dap_ap_read_reg_u32(swjdp, AP_REG_BASE, &dbgbase);
dap_ap_read_reg_u32(swjdp, AP_REG_IDR, &apid);
dap_ap_select(swjdp, apsel);
dap_ap_read_reg_u32(swjdp, AP_REG_BASE, &dbgbase);
dap_ap_read_reg_u32(swjdp, AP_REG_IDR, &apid);
- swjdp_transaction_endcheck(swjdp);
+ jtagdp_transaction_endcheck(swjdp);
/* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
mem_ap = ((apid&0x10000) && ((apid&0x0F) != 0));
command_print(cmd_ctx, "AP ID register 0x%8.8" PRIx32, apid);
/* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
mem_ap = ((apid&0x10000) && ((apid&0x0F) != 0));
command_print(cmd_ctx, "AP ID register 0x%8.8" PRIx32, apid);
mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFF8, &cid2);
mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFFC, &cid3);
mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFCC, &memtype);
mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFF8, &cid2);
mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFFC, &cid3);
mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFCC, &memtype);
- swjdp_transaction_endcheck(swjdp);
+ jtagdp_transaction_endcheck(swjdp);
if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
command_print(cmd_ctx, "\tCID3 0x%2.2" PRIx32
", CID2 0x%2.2" PRIx32
if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
command_print(cmd_ctx, "\tCID3 0x%2.2" PRIx32
", CID2 0x%2.2" PRIx32
if (apselsave != apsel)
dap_ap_select(swjdp, apsel);
if (apselsave != apsel)
dap_ap_select(swjdp, apsel);
+ /* NOTE: assumes we're talking to a MEM-AP, which
+ * has a base address. There are other kinds of AP,
+ * though they're not common for now. This should
+ * use the ID register to verify it's a MEM-AP.
+ */
dap_ap_read_reg_u32(swjdp, AP_REG_BASE, &baseaddr);
dap_ap_read_reg_u32(swjdp, AP_REG_BASE, &baseaddr);
- retval = swjdp_transaction_endcheck(swjdp);
+ retval = jtagdp_transaction_endcheck(swjdp);
command_print(CMD_CTX, "0x%8.8" PRIx32, baseaddr);
if (apselsave != apsel)
command_print(CMD_CTX, "0x%8.8" PRIx32, baseaddr);
if (apselsave != apsel)
dap_ap_select(swjdp, apsel);
dap_ap_read_reg_u32(swjdp, AP_REG_IDR, &apid);
dap_ap_select(swjdp, apsel);
dap_ap_read_reg_u32(swjdp, AP_REG_IDR, &apid);
- retval = swjdp_transaction_endcheck(swjdp);
+ retval = jtagdp_transaction_endcheck(swjdp);
command_print(CMD_CTX, "ap %" PRIi32 " selected, identification register 0x%8.8" PRIx32,
apsel, apid);
command_print(CMD_CTX, "ap %" PRIi32 " selected, identification register 0x%8.8" PRIx32,
apsel, apid);
dap_ap_select(swjdp, apsel);
dap_ap_read_reg_u32(swjdp, AP_REG_IDR, &apid);
dap_ap_select(swjdp, apsel);
dap_ap_read_reg_u32(swjdp, AP_REG_IDR, &apid);
- retval = swjdp_transaction_endcheck(swjdp);
+ retval = jtagdp_transaction_endcheck(swjdp);
command_print(CMD_CTX, "0x%8.8" PRIx32, apid);
if (apselsave != apsel)
dap_ap_select(swjdp, apselsave);
command_print(CMD_CTX, "0x%8.8" PRIx32, apid);
if (apselsave != apsel)
dap_ap_select(swjdp, apselsave);
int dap_ap_read_reg_u32(struct swjdp_common *swjdp,
uint32_t addr, uint32_t *value);
int dap_ap_read_reg_u32(struct swjdp_common *swjdp,
uint32_t addr, uint32_t *value);
-/* Queued transactions must be completed with swjdp_transaction_endcheck() */
-int swjdp_transaction_endcheck(struct swjdp_common *swjdp);
+/* Queued JTAG ops must be completed with jtagdp_transaction_endcheck() */
+int jtagdp_transaction_endcheck(struct swjdp_common *swjdp);
/* MEM-AP memory mapped bus single uint32_t register transfers, without endcheck */
int mem_ap_read_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t *value);
/* MEM-AP memory mapped bus single uint32_t register transfers, without endcheck */
int mem_ap_read_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t *value);
dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0);
dap_ap_read_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRDR & 0xC), value);
dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0);
dap_ap_read_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRDR & 0xC), value);
- retval = swjdp_transaction_endcheck(swjdp);
+ retval = jtagdp_transaction_endcheck(swjdp);
/* restore DCB_DCRDR - this needs to be in a seperate
* transaction otherwise the emulated DCC channel breaks */
/* restore DCB_DCRDR - this needs to be in a seperate
* transaction otherwise the emulated DCC channel breaks */
dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0);
dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRSR & 0xC), regnum | DCRSR_WnR);
dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0);
dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRSR & 0xC), regnum | DCRSR_WnR);
- retval = swjdp_transaction_endcheck(swjdp);
+ retval = jtagdp_transaction_endcheck(swjdp);
/* restore DCB_DCRDR - this needs to be in a seperate
* transaction otherwise the emulated DCC channel breaks */
/* restore DCB_DCRDR - this needs to be in a seperate
* transaction otherwise the emulated DCC channel breaks */
target_write_u32(target, dwt_list[i].dwt_comparator_address + 8,
dwt_list[i].function);
}
target_write_u32(target, dwt_list[i].dwt_comparator_address + 8,
dwt_list[i].function);
}
- swjdp_transaction_endcheck(swjdp);
+ jtagdp_transaction_endcheck(swjdp);
register_cache_invalidate(cortex_m3->armv7m.core_cache);
register_cache_invalidate(cortex_m3->armv7m.core_cache);
- swjdp_transaction_endcheck(swjdp);
+ jtagdp_transaction_endcheck(swjdp);
LOG_DEBUG("%s SHCSR 0x%" PRIx32 ", SR 0x%" PRIx32 ", CFSR 0x%" PRIx32 ", AR 0x%" PRIx32 "", armv7m_exception_string(armv7m->exception_number), \
shcsr, except_sr, cfsr, except_ar);
return ERROR_OK;
LOG_DEBUG("%s SHCSR 0x%" PRIx32 ", SR 0x%" PRIx32 ", CFSR 0x%" PRIx32 ", AR 0x%" PRIx32 "", armv7m_exception_string(armv7m->exception_number), \
shcsr, except_sr, cfsr, except_ar);
return ERROR_OK;