reset_config trst_and_srst separate
-adapter_nsrst_delay 100
+adapter srst delay 100
jtag_ntrst_delay 100
source [find target/ixp42x.cfg]
transport select swd
# chosen speed is 'safe' choice, but your adapter may be capable of more
-adapter_khz 400
+adapter speed 400
source [find target/adsp-sc58x.cfg]
#usb_blaster_vid_pid 0x6810 0x09fb
#usb_blaster_device_desc "USB-Blaster II"
-adapter_khz 100
+adapter speed 100
source [find target/swj-dp.tcl]
# set a safe JTAG clock speed, can be overridden
-adapter_khz 1000
+adapter speed 1000
global _CHIPNAME
if { [info exists CHIPNAME] } {
source [find cpld/xilinx-xc7.cfg]
source [find cpld/jtagspi.cfg]
-adapter_khz 25000
+adapter speed 25000
# Usage:
#
$_TARGETNAME configure -event reset-start {
# start off real slow when we're running off internal RC oscillator
- adapter_khz 32
+ adapter speed 32
}
proc peek32 {address} {
echo "Master clock ok."
# Now that we're up and running, crank up speed!
- global post_reset_khz ; adapter_khz $post_reset_khz
+ global post_reset_khz ; adapter speed $post_reset_khz
echo "Configuring the SDRAM controller..."
}
# This target is pretty snappy...
-adapter_khz 16000
+adapter speed 16000
proc at91rm9200_dk_init { } {
# Try to run at 1khz... Yea, that slow!
# Chip is really running @ 32khz
- adapter_khz 8
+ adapter speed 8
mww 0xfffffc64 0xffffffff
## disable all clocks but system clock
#========================================
# CPU now runs at 180mhz
# SYS runs at 60mhz.
- adapter_khz 40000
+ adapter speed 40000
#========================================
flash bank $_FLASHNAME cfi 0x10000000 0x00800000 2 2 $_TARGETNAME
# The chip may run @ 32khz, so set a really low JTAG speed
-adapter_khz 8
+adapter speed 8
proc at91rm9200_ek_init { } {
# Try to run at 1khz... Yea, that slow!
# Chip is really running @ 32khz
- adapter_khz 8
+ adapter speed 8
mww 0xfffffc64 0xffffffff
## disable all clocks but system clock
#========================================
# CPU now runs at 180mhz
# SYS runs at 60mhz.
- adapter_khz 40000
+ adapter speed 40000
#========================================
## Init SDRAM
reset_config srst_only
-adapter_nsrst_delay 200
+adapter srst delay 200
jtag_ntrst_delay 200
# If you don't want to execute built-in boot rom code (and there are good reasons at times not to do that) in the
# jtag speed without causing GDB keep alive problem.
arm7_9 fast_memory_access disable
- adapter_khz 2 ;# Slow-speed oscillator enabled at reset, so run jtag speed slow.
+ adapter speed 2 ;# Slow-speed oscillator enabled at reset, so run jtag speed slow.
halt ;# Make sure processor is halted, or error will result in following steps.
wait_halt 10000
mww 0xfffffd08 0xa5000501 ;# RSTC_MR : enable user reset.
# Switch over to adaptive clocking.
- adapter_khz 0
+ adapter speed 0
# Enable faster DCC downloads and memory accesses.
set CHIPNAME at91sam3n4c
-adapter_khz 32
+adapter speed 32
source [find target/at91sam3nXX.cfg]
reset_config none
# slow default clock
-adapter_khz 1000
+adapter speed 1000
set CHIPNAME uscale
# BCM28155_AP
-adapter_khz 20000
+adapter speed 20000
set CHIPNAME bcm28155
source [find target/bcm281xx.cfg]
# Toradex Colibri PXA270
source [find target/pxa270.cfg]
reset_config trst_and_srst srst_push_pull
-adapter_nsrst_assert_width 40
+adapter srst pulse_width 40
# CS0 -- one bank of CFI flash, 32 MBytes
# the bank is 32-bits wide, two 16-bit chips in parallel
source [find target/pxa270.cfg]
# longer-than-normal reset delay
-adapter_nsrst_delay 800
+adapter srst delay 800
reset_config trst_and_srst separate
proc csb337_clk_init { } {
# CPU is in Slow Clock Mode (32KiHz) ... needs slow JTAG clock
- adapter_khz 8
+ adapter speed 8
# CKGR_MOR: start main oscillator (3.6864 MHz)
mww 0xfffffc20 0xff01
sleep 20
# CPU is in Normal Mode ... allows faster JTAG clock speed
- adapter_khz 40000
+ adapter speed 40000
}
proc csb337_nor_init { } {
# Determined by trial and error
reset_config trst_and_srst combined
-adapter_nsrst_delay 200
+adapter srst delay 200
jtag_ntrst_delay 200
$_TARGETNAME configure -event gdb-attach { reset init }
set _TARGETNAME $_CHIPNAME.cpu
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-adapter_nsrst_delay 200
+adapter srst delay 200
jtag_ntrst_delay 0
ftdi_layout_init 0x8008 0x800b
-adapter_khz 25000
+adapter speed 25000
source [find cpld/xilinx-xc6s.cfg]
echo "Initialize DM365 EVM board"
# CLKIN = 24 MHz ... can't talk quickly to ARM yet
- adapter_khz 1500
+ adapter speed 1500
# FIXME -- PLL init
# http://dangerousprototypes.com/docs/Bus_Blaster
#
# To reprogram the on-board CPLD do:
-# openocd -f board/dp_busblaster_v3.cfg -c "adapter
_khz 1000; init; svf <path_to_svf>; shutdown"
+# openocd -f board/dp_busblaster_v3.cfg -c "adapter
speed 1000; init; svf <path_to_svf>; shutdown"
#
source [find interface/ftdi/dp_busblaster.cfg]
source [find interface/jlink.cfg]
transport select swd
-adapter_khz 1000
+adapter speed 1000
set CHIPNAME efm32
source [find target/efm32.cfg]
#
# NOTE: to use J-Link instead of the on-board interface,
-# you may also need to reduce adapter_khz to be about 1200.
+# you may also need to reduce adapter speed to be about 1200.
# source [find interface/jlink.cfg]
# include the FT2232 interface config for on-board JTAG interface
proc init_board {} {
# Delays on reset lines
- adapter_nsrst_delay 500
+ adapter srst delay 500
jtag_ntrst_delay 1
# Adaptive JTAG clocking through RTCK.
transport select jtag
# set a safe JTAG clock speed, can be overridden
-adapter_khz 1000
+adapter speed 1000
# SRST and TRST are wired up
reset_config trst_and_srst
# delay after SRST goes inactive
-adapter_nsrst_delay 70
+adapter srst delay 70
# board has an i.MX8MQ with 4 Cortex-A53 cores
set CHIPNAME imx8mq
# Micrel MIC2775-29YM5 Supervisor
# Reset output will remain active for 280ms (maximum)
#
-adapter_nsrst_delay 300
+adapter srst delay 300
jtag_ntrst_delay 300
arm7_9 fast_memory_access enable
arm7_9 dcc_downloads enable
-adapter_khz 16000
+adapter speed 16000
# Target events
# iMX6Q POR gates JTAG and the chip is completely incommunicado
# over JTAG for at least 10ms after nSRST is deasserted
-adapter_nsrst_delay 11
+adapter srst delay 11
# Source generic iMX6Q target configuration
set CHIPNAME imx6q
# hook the init function into the reset-init event
$_TARGETNAME.0 configure -event reset-init { imx6q_sabresd_init }
# set a slow default JTAG clock, can be overridden later
-adapter_khz 1000
+adapter speed 1000
# Initial JTAG speed should not exceed 1/6 of the initial CPU clock
# frequency (24MHz). Be conservative and use 1/8 of the frequency.
# (24MHz / 8 = 3MHz)
-adapter_khz 3000
+adapter speed 3000
$_TARGETNAME configure -event reset-start {
# Upon reset, set the JTAG frequency to 3MHz again, see above.
echo "Setting JTAG speed to 3MHz until clocks are initialized."
- adapter_khz 3000
+ adapter speed 3000
# Halt the CPU.
halt
# Tests showed that 15MHz works OK, higher speeds can cause problems,
# though. Not sure if this is a CPU issue or JTAG adapter issue.
echo "Increasing JTAG speed to 15MHz."
- adapter_khz 15000
+ adapter speed 15000
# Enable faster memory access.
arm7_9 fast_memory_access enable
source [find target/hilscher_netx500.cfg]
reset_config trst_and_srst
-adapter_nsrst_delay 500
+adapter srst delay 500
jtag_ntrst_delay 500
$_TARGETNAME configure -work-area-virt 0x1000 -work-area-phys 0x1000 -work-area-size 0x4000 -work-area-backup 1
source [find target/hilscher_netx500.cfg]
reset_config trst_and_srst
-adapter_nsrst_delay 500
+adapter srst delay 500
jtag_ntrst_delay 500
$_TARGETNAME configure -work-area-virt 0x1000 -work-area-phys 0x1000 -work-area-size 0x4000 -work-area-backup 1
# problems try to line below
# reset_config trst_and_srst srst_pulls_trst
reset_config trst_and_srst
-adapter_nsrst_delay 500
+adapter srst delay 500
jtag_ntrst_delay 500
$_TARGETNAME configure -work-area-virt 0x08000000 -work-area-phys 0x08000000 -work-area-size 0x4000 -work-area-backup 1
source [find target/hilscher_netx50.cfg]
reset_config trst_and_srst
-adapter_nsrst_delay 500
+adapter srst delay 500
jtag_ntrst_delay 500
$_TARGETNAME configure -work-area-virt 0x10000000 -work-area-phys 0x10000000 -work-area-size 0x4000 -work-area-backup 1
source [find target/hilscher_netx500.cfg]
reset_config trst_and_srst
-adapter_nsrst_delay 500
+adapter srst delay 500
jtag_ntrst_delay 500
$_TARGETNAME configure -work-area-virt 0x1000 -work-area-phys 0x1000 -work-area-size 0x4000 -work-area-backup 1
source [find target/hilscher_netx500.cfg]
reset_config trst_and_srst
-adapter_nsrst_delay 500
+adapter srst delay 500
jtag_ntrst_delay 500
$_TARGETNAME configure -work-area-virt 0x1000 -work-area-phys 0x1000 -work-area-size 0x4000 -work-area-backup 1
# startup @ 500kHz
-adapter_khz 500
+adapter speed 500
# http://www.hitex.com/
# Delays on reset lines
-adapter_nsrst_delay 50
+adapter srst delay 50
jtag_ntrst_delay 1
# Maximum of 1/8 of clock frequency (XTAL = 16 MHz).
# Adaptive clocking through RTCK is not supported.
-adapter_khz 2000
+adapter speed 2000
# Target device: LPC29xx with ETB
# The following variables are used by the LPC2900 script:
# Event handlers
$_TARGETNAME configure -event reset-start {
# Back to the slow JTAG clock
- adapter_khz 2000
+ adapter speed 2000
}
# External 16-bit flash at chip select CS7 (SST39VF3201-70, 4 MiB)
mww 0xFFFF8070 0x02000000 ;# SYS_CLK_CONF: PLL
# Increase JTAG speed
- adapter_khz 6000
+ adapter speed 6000
# Enable external memory bus (16-bit SRAM at CS6, 16-bit flash at CS7)
mww 0xE0001138 0x0000001F ;# P1.14 = D0
jtag newtap str750 cpu -irlen 4 -ircapture 0x1 -irmask 0x0f -expected-id 0x4f1f0041
# for some reason this board like to startup @ 500kHz
-adapter_khz 500
+adapter speed 500
source [find interface/ftdi/hitex_str9-comstick.cfg]
# set jtag speed
-adapter_khz 3000
+adapter speed 3000
-adapter_nsrst_delay 100
+adapter srst delay 100
jtag_ntrst_delay 100
#use combined on interfaces or targets that can't set TRST/SRST separately
reset_config trst_and_srst
# Set reset type
#reset_config srst_only
-adapter_khz 3000
+adapter speed 3000
# Slow speed to be sure it will work
jtag_rclk 1000
arm core_state arm
jtag_rclk 3000
-# adapter_khz 3000
+# adapter speed 3000
}
# Set reset type.
# reset_config trst_and_srst
-# adapter_nsrst_delay 200
+# adapter srst delay 200
# jtag_ntrst_delay 200
arm7_9 fast_memory_access disable
# Slow-speed oscillator enabled at reset, so run jtag speed slow.
- adapter_khz 4
+ adapter speed 4
# Make sure processor is halted, or error will result in following steps.
halt
wait_halt 10000
# Switch over to adaptive clocking.
- adapter_khz 6000
+ adapter speed 6000
# Enable faster DCC downloads.
# This setup puts RAM at 0xA0000000
# reset the board correctly
- adapter_khz 500
+ adapter speed 500
reset run
reset halt
reset_config trst_and_srst separate trst_open_drain srst_open_drain
# Run at 6 MHz
-adapter_khz 6000
+adapter speed 6000
$_TARGETNAME configure -event "reset-assert" {
echo "Reseting ...."
# Set reset type
#reset_config srst_only
-adapter_khz 3000
+adapter speed 3000
# Slow speed to be sure it will work
jtag_rclk 1000
arm core_state arm
jtag_rclk 3000
-# adapter_khz 3000
+# adapter speed 3000
}
source [find target/exynos5250.cfg]
# Experimentally determined highest working speed
-adapter_khz 200
+adapter speed 200
reset_config none
transport select jtag
-adapter_khz 25000
+adapter speed 25000
source [find cpld/xilinx-xc7.cfg]
source [find cpld/jtagspi.cfg]
source [find cpld/jtagspi.cfg]
source [find fpga/xilinx-xadc.cfg]
source [find fpga/xilinx-dna.cfg]
-adapter_khz 25000
+adapter speed 25000
# example command to write bitstream, soft-cpu bios and runtime:
# openocd -f board/kc705.cfg -c "init;\
source [find cpld/jtagspi.cfg]
-adapter_khz 25000
+adapter speed 25000
source [find target/imx.cfg]
$_TARGETNAME configure -event reset-init { kindle2_init }
-$_TARGETNAME configure -event reset-start { adapter_khz 1000 }
+$_TARGETNAME configure -event reset-start { adapter speed 1000 }
# 8MiB NOR Flash
set _FLASHNAME $_CHIPNAME.flash
# this is broken but enabled by default
arm11 memwrite burst disable
-adapter_khz 1000
+adapter speed 1000
ftdi_tdo_sample_edge falling
proc kindle2_init {} {
source [find target/pxa255.cfg]
-adapter_nsrst_delay 250
+adapter srst delay 250
jtag_ntrst_delay 250
# NOTE: until after pinmux and such are set up, only CS0 is
# Recommended MBFTDI programmer
source [find interface/ftdi/mbftdi.cfg]
-adapter_khz 2000
+adapter speed 2000
transport select jtag
# Altera MAXII EPM240T100C CPLD
# Built-in MBFTDI programmer
source [find interface/ftdi/mbftdi.cfg]
-adapter_khz 2000
+adapter speed 2000
transport select jtag
# Cyclone III EP3C10E144 FPGA
# Built-in MBFTDI programmer
source [find interface/ftdi/mbftdi.cfg]
-adapter_khz 2000
+adapter speed 2000
transport select jtag
# MAX10 10M50SAE144C8GES FPGA
$_TARGETNAME configure -event reset-start {
# Start *real slow* as we do not know the
# state the boot rom left the clock in
- adapter_khz 10
+ adapter speed 10
}
# Set up 100MHz clock to CPU
#
#
global MCB1700_CCLK
- adapter_khz [expr $MCB1700_CCLK / 8]
+ adapter speed [expr $MCB1700_CCLK / 8]
# Do not remap 0x0000-0x0020 to anything but the flash (i.e. select
# "User Flash Mode" where interrupt vectors are _not_ remapped,
#
source [find interface/cmsis-dap.cfg]
-adapter_khz 1000
+adapter speed 1000
set CHIPNAME saml11
source [find target/atsaml1x.cfg]
$_TARGETNAME configure -work-area-phys 0x40000000 -work-area-size 0x4000 -work-area-backup 1
#reset configuration
-adapter_nsrst_delay 100
+adapter srst delay 100
jtag_ntrst_delay 100
reset_config trst_and_srst
# IMPORTANT! See README at top of this file.
#-------------------------------------------------------------------------
- adapter_khz 12000
+ adapter speed 12000
jtag interface
#-------------------------------------------------------------------------
nand device s3c2440 0
- adapter_nsrst_delay 100
+ adapter srst delay 100
jtag_ntrst_delay 100
reset_config trst_and_srst
init
}
-adapter_khz 1000
-adapter_nsrst_delay 100
+adapter speed 1000
+adapter srst delay 100
jtag_ntrst_delay 100
reset_config trst_and_srst
#
ftdi_layout_init 0x0008 0x004b
reset_config none
-adapter_khz 30000
+adapter speed 30000
source [find cpld/xilinx-xc7.cfg]
source [find cpld/jtagspi.cfg]
transport select jtag
# set a safe speed, can be overridden
-adapter_khz 1000
+adapter speed 1000
# reset configuration has TRST and SRST support
reset_config trst_and_srst srst_push_pull
# need at least 100ms delay after SRST release for JTAG
-adapter_nsrst_delay 100
+adapter srst delay 100
# source the target file
source [find target/imx7.cfg]
transport select jtag
# set a safe JTAG clock speed, can be overridden
-adapter_khz 1000
+adapter speed 1000
# default JTAG configuration has only SRST and no TRST
reset_config srst_only srst_push_pull
# delay after SRST goes inactive
-adapter_nsrst_delay 70
+adapter srst delay 70
# board has an i.MX8MQ with 4 Cortex-A53 cores
set CHIPNAME imx8mq
# delays needed to get stable reads of cpu state
jtag_ntrst_delay 10
-adapter_nsrst_delay 200
+adapter srst delay 200
# board uses pullup and connects only srst
reset_config srst_open_drain
# srst is connected to NRESET of CPU and fully resets everything...
reset_config srst_only srst_pulls_trst
-adapter_khz 1
+adapter speed 1
$_TARGETNAME configure -event reset-start {
- adapter_khz 1
+ adapter speed 1
}
$_TARGETNAME configure -event reset-init {
echo "set up pll"
sleep 100
- adapter_khz 5000
+ adapter speed 5000
}
$_TARGETNAME arm7_9 dcc_downloads enable
source [find interface/ftdi/openrd.cfg]
source [find target/feroceon.cfg]
-adapter_khz 2000
+adapter speed 2000
$_TARGETNAME configure \
-work-area-phys 0x10000000 \
poll_period 1
# Set the adapter speed
-adapter_khz 3000
+adapter speed 3000
# Enable the target description feature
gdb_target_description enable
source [find target/lpc3250.cfg]
-adapter_nsrst_delay 200
+adapter srst delay 200
jtag_ntrst_delay 1
-adapter_khz 200
+adapter speed 200
reset_config trst_and_srst separate
arm7_9 dcc_downloads enable
$_TARGETNAME configure -event reset-start {
arm7_9 fast_memory_access disable
- adapter_khz 200
+ adapter speed 200
}
$_TARGETNAME configure -event reset-end {
- adapter_khz 6000
+ adapter speed 6000
arm7_9 fast_memory_access enable
}
reset_config trst_and_srst
-adapter_nsrst_delay 200
+adapter srst delay 200
jtag_ntrst_delay 200
#xscale debug_handler 0 0xFFFF0800 ;# debug handler base address
source [find target/quark_d20xx.cfg]
-adapter_khz 1000
+adapter speed 1000
reset_config trst_only
source [find target/quark_x10xx.cfg]
#default frequency but this can be adjusted at runtime
-adapter_khz 4000
+adapter speed 4000
reset_config trst_only
#
reset_config trst_and_srst srst_pulls_trst
-adapter_khz 1000
-adapter_nsrst_delay 100
+adapter speed 1000
+adapter srst delay 100
jtag_ntrst_delay 100
$_TARGETNAME configure -work-area-phys 0x00000000 -work-area-size 0x04000000 -work-area-backup 0
# Target events
#
-$_TARGETNAME configure -event reset-start {adapter_khz 1000}
+$_TARGETNAME configure -event reset-start {adapter speed 1000}
$_TARGETNAME configure -event reset-init {
# switch on PLL for 200MHz operation
arm7_9 dcc_downloads enable
arm7_9 fast_memory_access enable
- adapter_khz 15000
+ adapter speed 15000
# map nor flash to 0x20000000
# map sdram to 0x00000000
#ftdi_layout_signal nTRST -data 0x0010
reset_config none
-adapter_khz 5000
+adapter speed 5000
transport select jtag
source [find interface/ftdi/sheevaplug.cfg]
source [find target/feroceon.cfg]
-adapter_khz 2000
+adapter speed 2000
$_TARGETNAME configure \
-work-area-phys 0x10000000 \
#
# Be sure you include the speed and interface before this file
# Example:
-# -c "adapter_khz 5000" -f "interface/ftdi/olimex-arm-usb-tiny-h.cfg" -f "board/sifive-e31arty.cfg"
+# -c "adapter speed 5000" -f "interface/ftdi/olimex-arm-usb-tiny-h.cfg" -f "board/sifive-e31arty.cfg"
set _CHIPNAME riscv
jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000001
#
# Be sure you include the speed and interface before this file
# Example:
-# -c "adapter_khz 5000" -f "interface/ftdi/olimex-arm-usb-tiny-h.cfg" -f "board/sifive-e51arty.cfg"
+# -c "adapter speed 5000" -f "interface/ftdi/olimex-arm-usb-tiny-h.cfg" -f "board/sifive-e51arty.cfg"
set _CHIPNAME riscv
jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000001
-adapter_khz 10000
+adapter speed 10000
adapter driver ftdi
ftdi_device_desc "Dual RS232-HS"
#Reset Stretcher logic on FE310 is ~1 second long
#This doesn't apply if you use
# ftdi_set_signal, but still good to document
-#adapter_nsrst_delay 1500
+#adapter srst delay 1500
set _CHIPNAME riscv
jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
# Telo board & C100 support trst and srst
# make the reset asserted to
# allow RC circuit to discharge for: [ms]
-adapter_nsrst_assert_width 100
+adapter srst pulse_width 100
jtag_ntrst_assert_width 100
# don't talk to JTAG after reset for: [ms]
-adapter_nsrst_delay 100
+adapter srst delay 100
jtag_ntrst_delay 100
reset_config trst_and_srst separate
# issue telnet: reset init
# issue gdb: monitor reset init
$_TARGETNAME configure -event reset-init {
- adapter_khz 100
+ adapter speed 100
# this will setup Telo board
setupTelo
#turn up the JTAG speed
- adapter_khz 3000
+ adapter speed 3000
echo "JTAG speek now 3MHz"
echo "type helpC100 to get help on C100"
}
source [find interface/ftdi/xds100v2.cfg]
transport select jtag
-adapter_khz 30000
+adapter speed 30000
source [find target/am437x.cfg]
$_TARGETNAME configure -event reset-init { init_platform 0x61a11b32 }
# Works on both AM437x GP EVM and AM438x ePOS EVM
transport select jtag
-adapter_khz 16000
+adapter speed 16000
source [find target/am437x.cfg]
# The JTAG interface is built directly on the board.
source [find interface/ftdi/xds100v2.cfg]
-adapter_khz 16000
+adapter speed 16000
reset_config trst_and_srst
# AM335x Beaglebone Black
# http://beagleboard.org/bone
-adapter_khz 1000
+adapter speed 1000
reset_config trst_and_srst
#
source [find interface/xds110.cfg]
transport select jtag
-adapter_khz 2500
+adapter speed 2500
source [find target/ti_cc13x0.cfg]
# TI CC13x2 LaunchPad Evaluation Kit
#
source [find interface/xds110.cfg]
-adapter_khz 2500
+adapter speed 2500
transport select jtag
source [find target/ti_cc13x2.cfg]
# TI CC26x0 LaunchPad Evaluation Kit
#
source [find interface/xds110.cfg]
-adapter_khz 2500
+adapter speed 2500
transport select jtag
source [find target/ti_cc26x0.cfg]
# TI CC26x2 LaunchPad Evaluation Kit
#
source [find interface/xds110.cfg]
-adapter_khz 2500
+adapter speed 2500
transport select jtag
source [find target/ti_cc26x2.cfg]
transport select jtag
}
-adapter_khz 2500
+adapter speed 2500
set WORKAREASIZE 0x40000
source [find target/ti_cc32xx.cfg]
# TI CC3220SF-LaunchXL LaunchPad Evaluation Kit
#
source [find interface/xds110.cfg]
-adapter_khz 2500
+adapter speed 2500
transport select swd
source [find target/ti_cc3220sf.cfg]
# TI CC32xx-LaunchXL LaunchPad Evaluation Kit
#
source [find interface/xds110.cfg]
-adapter_khz 2500
+adapter speed 2500
transport select swd
source [find target/ti_cc32xx.cfg]
# TI MSP432 LaunchPad Evaluation Kit
#
source [find interface/xds110.cfg]
-adapter_khz 2500
+adapter speed 2500
transport select swd
source [find target/ti_msp432.cfg]
-adapter_khz 1500
+adapter speed 1500
source [find interface/ftdi/xds100v2.cfg]
source [find target/ti_tms570.cfg]
# board does not feature anything but JTAG
transport select jtag
-adapter_khz 10000
+adapter speed 10000
# SRST-only reset configuration
reset_config srst_only srst_push_pull
mww 0xf4300004 0x00000000
sleep 10
-# adapter_khz NNNN
+# adapter speed NNNN
# remap off in case of IROM boot
mww 0xf0000004 0x00000001
mww 0xf4300004 0x00000000
sleep 10
-# adapter_khz NNNN
+# adapter speed NNNN
# remap off in case of IROM boot
mww 0xf0000004 0x00000001
# hook the init function into the reset-init event
${_TARGETNAME}0 configure -event reset-init { board_init }
# set a slow default JTAG clock, can be overridden later
-adapter_khz 1000
+adapter speed 1000
reset_config trst_and_srst separate
# XM4 = 400MHz, XL6P = 600MHz...let's run at 0.1*400MHz=40MHz
-adapter_khz 40000
+adapter speed 40000
# flash bank <driver> <base> <size> <chip_width> <bus_width>
# XL6P has 32 MB flash
source [find target/samsung_s3c2440.cfg]
-adapter_khz 16000
+adapter speed 16000
# Samsung K9F1208U0C NAND flash chip (64MiB, 3.3V, 8-bit)
nand device $_CHIPNAME.nand s3c2440 $_TARGETNAME
# other things than flash programming.
$_TARGETNAME configure -work-area-phys 0x00020000 -work-area-size 0x20000 -work-area-backup 0
-adapter_khz 16000
+adapter speed 16000
proc production_info {} {
# See calao-usb-a9260-c01.cfg and calao-usb-a9260-c02.cfg.
#
-adapter_nsrst_delay 200
+adapter srst delay 200
jtag_ntrst_delay 200
adapter driver ft232r
-adapter_khz 1000
+adapter speed 1000
reset_config none
# this generally works fast: the fpga can handle 30MHz, the spi flash can handle
# 54MHz with simple read, no dummy cycles, and wait-for-write-completion
-adapter_khz 30000
+adapter speed 30000
reset_config none
# this generally works fast: the fpga can handle 30MHz, the spi flash can handle
# 54MHz with simple read, no dummy cycles, and wait-for-write-completion
-adapter_khz 10000
+adapter speed 10000
aice vid_pid 0x1CFC 0x0000
aice port aice_usb
reset_config trst_and_srst
-adapter_khz 24000
+adapter speed 24000
aice retry_times 50
aice count_to_check_dbger 30
}
# JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
-adapter_khz 1000
+adapter speed 1000
-adapter_nsrst_delay 100
+adapter srst delay 100
if {[using_jtag]} {
jtag_ntrst_delay 100
}
set _CPUTAPID 0x3f0f0f0f
}
-adapter_nsrst_delay 200
+adapter srst delay 200
jtag_ntrst_delay 200
## JTAG scan chain
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
# SWD/JTAG speed
-adapter_khz 1000
+adapter speed 1000
##
## Target configuration
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME aducm360 0x00 0 0 0 $_TARGETNAME
-adapter_nsrst_delay 100
+adapter srst delay 100
cortex_m reset_config sysresetreq
# 0220ms JTAG pins switched to SD mode
#
# The time frame of 20ms can be not enough to init and halt the CPU. In this
-# case I would recommend to set: "adapter_khz 15000"
+# case I would recommend to set: "adapter speed 15000"
# To get more or less precise timings, the board should provide reset pin,
# or some bench power supply with remote function. In my case I used
# EEZ H24005 with this command to power on and halt the target:
# core 1 - 0x80112000
# Slow speed to be sure it will work
-adapter_khz 1000
+adapter speed 1000
set _TARGETNAME1 $_CHIPNAME.cpu.0
set _TARGETNAME2 $_CHIPNAME.cpu.1
target create $_TARGETNAME1 cortex_a -dap $_CHIPNAME.dap \
-coreid 0 -dbgbase 0x80110000
-$_TARGETNAME1 configure -event reset-start { adapter_khz 1000 }
+$_TARGETNAME1 configure -event reset-start { adapter speed 1000 }
$_TARGETNAME1 configure -event reset-assert-post "cycv_dbginit $_TARGETNAME1"
#target create $_TARGETNAME2 cortex_a -dap $_CHIPNAME.dap \
# -coreid 1 -dbgbase 0x80112000
-#$_TARGETNAME2 configure -event reset-start { adapter_khz 1000 }
+#$_TARGETNAME2 configure -event reset-start { adapter speed 1000 }
#$_TARGETNAME2 configure -event reset-assert-post "cycv_dbginit $_TARGETNAME2"
proc cycv_dbginit {target} {
# Run the adapter at the fastest acceptable speed with the slowest possible
# core clock.
-adapter_khz 10
+adapter speed 10
###############################################################################
# JTAG setup
# slowest possible core clock (16.8MHz/2 = 8.4MHz). It is OK to speed up
# *after* PLL and clock tree setup.
-$_TARGETNAME configure -event "reset-start" { adapter_khz 10 }
+$_TARGETNAME configure -event "reset-start" { adapter speed 10 }
# Describe the reset assert process for openocd - this is asserted with the
# ICEPick
global _TARGETNAME
amdm37x_dbginit $_TARGETNAME
- adapter_khz 1000
+ adapter speed 1000
}
$_TARGETNAME configure -event gdb-attach {
# Atheros AR71xx MIPS 24Kc SoC.
# tested on PB44 refererence board
-adapter_nsrst_delay 100
+adapter srst delay 100
jtag_ntrst_delay 100
reset_config trst_and_srst
# running off a crystal, we can run closer to the limit. Note
# that there can be a pretty wide band where things are more or less stable.
-adapter_khz 500
+adapter speed 500
-adapter_nsrst_delay 100
+adapter srst delay 100
if {[using_jtag]} {
jtag_ntrst_delay 100
}
# running off a crystal, we can run closer to the limit. Note
# that there can be a pretty wide band where things are more or less stable.
-adapter_khz 500
+adapter speed 500
-adapter_nsrst_delay 100
+adapter srst delay 100
if {[using_jtag]} {
jtag_ntrst_delay 100
}
# Datasheet does not specify SYSCLK to JTAG/SWD clock ratio.
# Usually used SYSCLK/6 is hell slow, testing shows that debugging can work @ SYSCLK/2
# but your mileage may vary.
-adapter_khz 50
+adapter speed 50
# System RC oscillator RCSYS starts in 3 cycles
-adapter_nsrst_delay 0
+adapter srst delay 0
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-adapter_nsrst_delay 300
+adapter srst delay 300
jtag_ntrst_delay 200
-adapter_khz 3
+adapter speed 3
######################
# Target configuration
reset_config trst_and_srst
-adapter_khz 4
+adapter speed 4
-adapter_nsrst_delay 200
+adapter srst delay 200
jtag_ntrst_delay 200
scan_chain
$_TARGETNAME configure -event reset-start {
# at reset chip runs at 32khz
- adapter_khz 8
+ adapter speed 8
}
$_TARGETNAME configure -event reset-init {at91sam_init}
sleep 10 ;# wait 10 ms
# Now run at anything fast... ie: 10mhz!
- adapter_khz 10000 ;# Increase JTAG Speed to 6 MHz
+ adapter speed 10000 ;# Increase JTAG Speed to 6 MHz
mww 0xffffec00 0x0a0a0a0a ;# SMC_SETUP0 : Setup SMC for Intel NOR Flash JS28F128P30T85 128MBit
mww 0xffffec04 0x0b0b0b0b ;# SMC_PULSE0
# Set fallback clock to 1/6 of worst-case clock speed (which would be the 32.768 kHz slow clock).
-adapter_khz 5
+adapter speed 5
# Establish internal SRAM memory work areas that are important to pre-bootstrap loaders, etc. The
# AT91SAM9G20 has two SRAM areas, one starting at 0x00200000 and the other starting at 0x00300000.
# This limit is most probably imposed by incorrectly handled SWD WAIT
# on some SWD adapters.
-adapter_khz 400
+adapter speed 400
# Atmel's EDBG (on-board cmsis-dap adapter of Xplained kits) works
# without problem at maximal clock speed. Atmel recommends
# adapter speed less than 10 * CPU clock.
-# adapter_khz 5000
+# adapter speed 5000
if {![using_hla]} {
# if srst is not fitted use SYSRESETREQ to
# For SRST based variant we still need proper timings.
# For ETH part the reset should be asserted at least for 10ms
# Since there is no other information let's take 100ms to be sure.
-adapter_nsrst_assert_width 100
+adapter srst pulse_width 100
# according to the SoC documentation it should take at least 5ms from
# reset end till bootstrap end. In the practice we need 8ms to get JTAG back
# to live.
-adapter_nsrst_delay 8
+adapter srst delay 8
if { [info exists CHIPNAME] } {
set _CHIPNAME $_CHIPNAME
set _ENDIAN little
# jtag speed
-adapter_khz 4500
+adapter speed 4500
reset_config srst_only
-adapter_nsrst_delay 100
+adapter srst delay 100
#jtag scan chain
if { [info exists CPUTAPID] } {
#to use it, script will be like:
#init
-#adapter_khz 4500
+#adapter speed 4500
#reset init
#verify_ircapture disable
#
set _ENDIAN little
# jtag speed
-adapter_khz 4500
+adapter speed 4500
# avr jtag docs never connect RSTN
reset_config none
# Atmel's EDBG (on-board cmsis-dap adapter of Xplained kits) works
# without problem at clock speed over 5000 khz. Atmel recommends
# adapter speed less than 10 * CPU clock.
-adapter_khz 2000
+adapter speed 2000
if {![using_hla]} {
# if srst is not fitted use SYSRESETREQ to
$_TARGETNAME configure -work-area-phys 0x20400000 -work-area-size $_WORKAREASIZE -work-area-backup 0
-adapter_khz 1800
+adapter speed 1800
if {![using_hla]} {
# if srst is not fitted use SYSRESETREQ to
set _CPUTAPID 0x21e8203f
-adapter_nsrst_delay 100
+adapter srst delay 100
jtag_ntrst_delay 100
reset_config trst_and_srst separate
set _CHIPNAME bcm6348
set _CPUID 0x0634817f
-adapter_khz 1000
+adapter speed 1000
jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUID
set _WORKAREASIZE 0x5F00
}
-adapter_khz 4000
+adapter speed 4000
if { [info exists CPUTAPID] } {
set _CPUTAPID $CPUTAPID
# this script only configures one core (that is used to run Linux)
# assume no PLL lock, start slowly
-adapter_khz 100
+adapter speed 100
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
mww $TIMER_WDT_HIGH_BOUND 0xffffff
mww $TIMER_WDT_CURRENT_COUNT 0x0
echo "JTAG speed lowered to 100kHz"
- adapter_khz 100
+ adapter speed 100
mww $TIMER_WDT_CONTROL 0x1
# wait until the reset
echo -n "Wating for watchdog to trigger..."
# Config for Texas Instruments low power RF SoC CC2538
# http://www.ti.com/lit/pdf/swru319
-adapter_khz 100
+adapter speed 100
source [find target/icepick.cfg]
source [find target/ti-cjtag.cfg]
target create $_TARGETNAME dragonite -endian $_ENDIAN -chain-position $_TARGETNAME
reset_config trst_and_srst
-adapter_nsrst_delay 200
+adapter srst delay 200
jtag_ntrst_delay 200
}
#jtag speed
-adapter_khz 4500
+adapter speed 4500
#has only srst
reset_config srst_only
}
#jtag speed
-adapter_khz 800
+adapter speed 800
reset_config srst_only
}
#jtag speed
-adapter_khz 800
+adapter speed 800
reset_config srst_only
swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
-adapter_khz 1000
+adapter speed 1000
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
}
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-adapter_nsrst_delay 100
+adapter srst delay 100
jtag_ntrst_delay 100
set _TARGETNAME $_CHIPNAME.cpu
$_TARGETNAME esirisc cache_arch $CACHEARCH
}
-adapter_khz 2000
+adapter speed 2000
reset_config none
target create $_TARGETNAME feroceon -endian $_ENDIAN -chain-position $_TARGETNAME
reset_config trst_and_srst
-adapter_nsrst_delay 200
+adapter srst delay 200
jtag_ntrst_delay 200
}
# delays on reset lines
-adapter_nsrst_delay 100
+adapter srst delay 100
if {[using_jtag]} {
jtag_ntrst_delay 100
}
flash bank $_FLASHNAME fm3 0 0 0 0 $_TARGETNAME
# 4MHz / 6 = 666kHz, so use 500
-adapter_khz 500
+adapter speed 500
if {![using_hla]} {
# if srst is not fitted use SYSRESETREQ to
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -endian little -dap $_CHIPNAME.dap
-adapter_khz 500
+adapter speed 500
if {![using_hla]} {
cortex_m reset_config sysresetreq
reset_config trst_and_srst srst_pulls_trst
# This delay is needed otherwise communication with the target would
# be unreliable
-adapter_nsrst_delay 100
+adapter srst delay 100
# Set the adapter speed ridiculously low just in case we are
# running off of a 32kHz clock
-adapter_khz 2
+adapter speed 2
proc gp32xxxa_halt_and_reset_control_registers {} {
# System control registers
# Set the adapter speed ridiculously low just in case we are
# running off of a 32kHz clock
- adapter_khz 2
+ adapter speed 2
# Disable any advanced features at this stage
arm7_9 dcc_downloads disable
# Now that we know that we are running at 48Mhz
# Increase JTAG speed and enable speed optimization features
- adapter_khz 5000
+ adapter speed 5000
arm7_9 dcc_downloads enable
arm7_9 fast_memory_access enable
}
reset_config trst_and_srst
#jtag nTRST and nSRST delay
-adapter_nsrst_delay 100
+adapter srst delay 100
jtag_ntrst_delay 100
if { [info exists CHIPNAME] } {
reset_config trst_and_srst srst_gates_jtag
-adapter_nsrst_delay 5
+adapter srst delay 5
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
}
# Slow speed to be sure it will work
-adapter_khz 1000
-$_TARGETNAME configure -event reset-start { adapter_khz 1000 }
+adapter speed 1000
+$_TARGETNAME configure -event reset-start { adapter speed 1000 }
$_TARGETNAME configure -event reset-assert-post "imx6_dbginit $_TARGETNAME"
}
# jtag speed. We need to stick to 16kHz until we've finished reset.
-adapter_khz 16
+adapter speed 16
reset_config trst_and_srst
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME arm966e -endian $_ENDIAN -chain-position $_TARGETNAME
-$_TARGETNAME configure -event reset-start { adapter_khz 16 }
+$_TARGETNAME configure -event reset-start { adapter speed 16 }
$_TARGETNAME configure -event reset-init {
# We can increase speed now that we know the target is halted.
- adapter_khz 3000
+ adapter speed 3000
}
$_TARGETNAME configure -work-area-phys 0x50000000 -work-area-size 16384 -work-area-backup 1
flash bank $_CHIPNAME.flash niietcm4 0 0 0 0 $_TARGETNAME
-adapter_khz 2000
+adapter speed 2000
-adapter_nsrst_delay 100
+adapter srst delay 100
if {[using_jtag]} {
jtag_ntrst_delay 100
}
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME kinetis_ke 0 0 0 0 $_TARGETNAME
-adapter_khz 1000
+adapter speed 1000
reset_config srst_nogate
# Table 5-1. Clock Summary of KL25 Sub-Family Reference Manual
# specifies up to 1MHz for VLPR mode and up to 24MHz for run mode;
# Table 17 of Sub-Family Data Sheet rev4 lists 25MHz as the maximum frequency.
-adapter_khz 1000
+adapter speed 1000
reset_config srst_nogate
set _CPUTAPID 0x00922f0f
}
-adapter_khz 6000
+adapter speed 6000
# jtag scan chain
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
flash bank $_FLASHNAME kinetis 0 0 0 0 $_TARGETNAME
kinetis create_banks
-adapter_khz 1000
+adapter speed 1000
reset_config srst_nogate
source [find target/swj-dp.tcl]
-adapter_khz 500
+adapter speed 500
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
# Run with *real slow* clock by default since the
# boot rom could have been playing with the PLL, so
# we have no idea what clock the target is running at.
-adapter_khz 10
+adapter speed 10
# delays on reset lines
-adapter_nsrst_delay 200
+adapter srst delay 200
if {[using_jtag]} {
jtag_ntrst_delay 200
}
reset_config trst_and_srst
# reset delays
- adapter_nsrst_delay 100
+ adapter srst delay 100
jtag_ntrst_delay 100
- adapter_khz $adapter_freq_khz
+ adapter speed $adapter_freq_khz
foreach i $cputapids {
append expected_ids "-expected-id " $i " "
# Target configuration
##################################################################
-adapter_nsrst_delay 1000
+adapter srst delay 1000
jtag_ntrst_delay 0
set _TARGETNAME $_CHIPNAME.cpu
source [find target/swj-dp.tcl]
-adapter_khz 500
+adapter speed 500
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
# NXP LPC4370 - 1x ARM Cortex-M4 + 2x ARM Cortex-M0 @ up to 204 MHz each
#
-adapter_khz 500
+adapter speed 500
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
# If srst is not fitted use SYSRESETREQ to perform a soft reset
cortex_m reset_config sysresetreq
}
-adapter_nsrst_delay 100
+adapter srst delay 100
$_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size 0x1ff0 -work-area-backup 0
target smp $_TARGETNAME
-adapter_khz 2000
+adapter speed 2000
# www.maximintegrated.com
# adapter speed
-adapter_khz 4000
+adapter speed 4000
# reset pin configuration
reset_config srst_only
# www.maximintegrated.com
# adapter speed
-adapter_khz 4000
+adapter speed 4000
# reset pin configuration
reset_config srst_only
# www.maximintegrated.com
# adapter speed
-adapter_khz 4000
+adapter speed 4000
# reset pin configuration
reset_config srst_only
jtag_ntrst_delay 200
# rclk hasn't been working well. This maybe the mc13224v or something else.
-#adapter_khz 2000
-adapter_khz 2000
+#adapter speed 2000
+adapter speed 2000
######################
# Target configuration
}
# JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
-adapter_khz 1000
+adapter speed 1000
-adapter_nsrst_delay 100
+adapter srst delay 100
if {[using_jtag]} {
jtag_ntrst_delay 100
}
# The chip should start up from internal 16Mhz RC, so setting adapter
# clock to 1Mhz should be OK
#
-adapter_khz 1000
+adapter speed 1000
proc enable_all_ram {} {
# nRF51822 Product Anomaly Notice (PAN) #16 explains that not all RAM banks
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
-adapter_khz 1000
+adapter speed 1000
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
flash bank $_FLASHNAME numicro 0x00300000 0 0 0 $_TARGETNAME
# set default SWCLK frequency
-adapter_khz 1000
+adapter speed 1000
# set default srst setting "none"
reset_config none
# be absolutely certain the JTAG clock will work with the worst-case
# 16.8MHz/2 = 8.4MHz core clock, even before a bootloader kicks in.
# OK to speed up *after* PLL and clock tree setup.
-adapter_khz 1000
-$_TARGETNAME configure -event "reset-start" { adapter_khz 1000 }
+adapter speed 1000
+$_TARGETNAME configure -event "reset-start" { adapter speed 1000 }
# Assume SRST is unavailable (e.g. TI-14 JTAG), so we must assert reset
# ourselves using PRM_RSTCTRL. RST_GS (2) is a warm reset, like ICEpick
set _CPUTAPID 0x0692602f
}
-adapter_nsrst_delay 100
+adapter srst delay 100
# NOTE: presumes irlen 38 is the C55x DSP, matching BSDL for
# its standalone siblings (like TMS320VC5502) of the same era
# be absolutely certain the JTAG clock will work with the worst-case
# CLKIN = 20 MHz (best case: 30 MHz) even when no bootloader turns
# on the PLL and starts using it. OK to speed up after clock setup.
-adapter_khz 1500
-$_TARGETNAME configure -event "reset-start" { adapter_khz 1500 }
+adapter speed 1500
+$_TARGETNAME configure -event "reset-start" { adapter speed 1500 }
arm7_9 fast_memory_access enable
arm7_9 dcc_downloads enable
set _WORKAREASIZE 0x4000
}
-adapter_nsrst_delay 100
+adapter srst delay 100
jtag_ntrst_delay 100
#jtag scan chain
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME psoc4 0 0 0 0 $_TARGETNAME
-adapter_khz 1500
+adapter speed 1500
# Reset, bloody PSoC 4 reset
#
}
if { ! [info exists PSOC4_USE_ACQUIRE] } {
- if { 0 == [string compare [adapter_name] kitprog ] } {
+ if { 0 == [string compare [adapter name] kitprog ] } {
set PSOC4_USE_ACQUIRE 1
} else {
set PSOC4_USE_ACQUIRE 0
$t invoke-event reset-assert-pre
if { $halt && $PSOC4_USE_ACQUIRE } {
- catch { [adapter_name] acquire_psoc }
+ catch { [adapter name] acquire_psoc }
$t arp_examine
} else {
if { $PSOC4_TEST_MODE_WORKAROUND } {
source [find target/swj-dp.tcl]
-adapter_khz 1000
+adapter speed 1000
global _CHIPNAME
if { [info exists CHIPNAME] } {
# PXA255 comes out of reset using 3.6864 MHz oscillator.
# Until the PLL kicks in, keep the JTAG clock slow enough
# that we get no errors.
-adapter_khz 300
-$_TARGETNAME configure -event "reset-start" { adapter_khz 300 }
+adapter speed 300
+$_TARGETNAME configure -event "reset-start" { adapter speed 300 }
# both TRST and SRST are *required* for debug
# DCSR is often accessed with SRST active
set _CPUTAPID3 0x89265013
}
-# set adapter_nsrst_delay to the delay introduced by your reset circuit
+# set adapter srst delay to the delay introduced by your reset circuit
# the rest of the needed delays are built into the openocd program
-adapter_nsrst_delay 260
+adapter srst delay 260
# set the jtag_ntrst_delay to the delay introduced by a reset circuit
# the rest of the needed delays are built into the openocd program
jtag_ntrst_delay 250
set _CPUTAPID_PXA32X_C0 0x7E642013
}
-# set adapter_nsrst_delay to the delay introduced by your reset circuit
+# set adapter srst delay to the delay introduced by your reset circuit
# the rest of the needed delays are built into the openocd program
-adapter_nsrst_delay 260
+adapter srst delay 260
# set the jtag_ntrst_delay to the delay introduced by a reset circuit
# the rest of the needed delays are built into the openocd program
# For SRST based variant we still need proper timings.
# For ETH part the reset should be asserted at least for 10ms
# Since there is no other information let's take 100ms to be sure.
-adapter_nsrst_assert_width 100
+adapter srst pulse_width 100
# according to the SoC documentation it should take at least 5ms from
# reset end till bootstrap end. In the practice we need 8ms to get JTAG back
# to live.
-adapter_nsrst_delay 8
+adapter srst delay 8
if { [info exists CHIPNAME] } {
set _CHIPNAME $_CHIPNAME
flash write_image [file] <parameters>
verify_image [file] <parameters>
-4. adapter_khz sets the maximum speed (or alternatively RCLK). If invoked
+4. adapter speed sets the maximum speed (or alternatively RCLK). If invoked
multiple times only the last setting is used.
interface/xxx.cfg files are always executed *before* target/xxx.cfg
-files, so any adapter_khz in interface/xxx.cfg will be overridden by
-target/xxx.cfg. adapter_khz in interface/xxx.cfg would then, effectively,
+files, so any adapter speed in interface/xxx.cfg will be overridden by
+target/xxx.cfg. adapter speed in interface/xxx.cfg would then, effectively,
set the default JTAG speed.
Note that a target/xxx.cfg file can invoke another target/yyy.cfg file,
cortex_m reset_config sysresetreq
}
-adapter_khz 1000
+adapter speed 1000
#
# RCLK?
#
-# adapter_khz 0
+# adapter speed 0
#
# Really low clock during reset?
#
-# adapter_khz 1
+# adapter speed 1
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME arm11 -endian $_ENDIAN -chain-position $_TARGETNAME
-adapter_nsrst_delay 500
+adapter srst delay 500
jtag_ntrst_delay 500
#reset configuration
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME sim3x 0 $_CPUROMSIZE 0 0 $_TARGETNAME
-adapter_khz 1000
+adapter speed 1000
-adapter_nsrst_delay 100
+adapter srst delay 100
if {[using_jtag]} {
jtag_ntrst_delay 100
}
set _CPUTAPID 0x08630001
}
-adapter_nsrst_delay 100
+adapter srst delay 100
jtag_ntrst_delay 100
reset_config trst_and_srst separate
# NOTE: this may be increased by a reset-init handler, after it
# configures and enables the PLL. Or you might need to decrease
# this, if you're using a slower clock.
-adapter_khz 500
+adapter speed 500
source [find mem_helper.tcl]
}
$_TARGETNAME configure -event reset-start {
- adapter_khz 500
+ adapter speed 500
#
# When nRST is asserted on most Stellaris devices, it clears some of
flash bank $_FLASHNAME stm32f1x 0x08000000 $_FLASH_SIZE 0 0 $_TARGETNAME
# adapter speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
-adapter_khz 1000
+adapter speed 1000
-adapter_nsrst_delay 100
+adapter srst delay 100
reset_config srst_nogate
proc stm32f0x_default_reset_start {} {
# Reset clock is HSI (8 MHz)
- adapter_khz 1000
+ adapter speed 1000
}
proc stm32f0x_default_examine_end {} {
mmw 0x40021004 0x00000002 0 ;# RCC_CFGR |= SW[1]
# Boost JTAG frequency
- adapter_khz 8000
+ adapter speed 8000
}
# Default hooks
flash bank $_FLASHNAME stm32f1x 0x08000000 $_FLASH_SIZE 0 0 $_TARGETNAME
# JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
-adapter_khz 1000
+adapter speed 1000
-adapter_nsrst_delay 100
+adapter srst delay 100
if {[using_jtag]} {
jtag_ntrst_delay 100
}
# bit more to be on the safe side. Perhaps superstition, but if are
# running off a crystal, we can run closer to the limit. Note
# that there can be a pretty wide band where things are more or less stable.
-adapter_khz 1000
+adapter speed 1000
-adapter_nsrst_delay 100
+adapter srst delay 100
if {[using_jtag]} {
jtag_ntrst_delay 100
}
# bit more to be on the safe side. Perhaps superstition, but if are
# running off a crystal, we can run closer to the limit. Note
# that there can be a pretty wide band where things are more or less stable.
-adapter_khz 1000
+adapter speed 1000
-adapter_nsrst_delay 100
+adapter srst delay 100
if {[using_jtag]} {
jtag_ntrst_delay 100
}
proc stm32f3x_default_reset_start {} {
# Reset clock is HSI (8 MHz)
- adapter_khz 1000
+ adapter speed 1000
}
proc stm32f3x_default_examine_end {} {
mmw 0x40021004 0x00000002 0 ;# RCC_CFGR |= SW[1]
# Boost JTAG frequency
- adapter_khz 8000
+ adapter speed 8000
}
# Default hooks
# bit more to be on the safe side. Perhaps superstition, but if are
# running off a crystal, we can run closer to the limit. Note
# that there can be a pretty wide band where things are more or less stable.
-adapter_khz 2000
+adapter speed 2000
-adapter_nsrst_delay 100
+adapter srst delay 100
if {[using_jtag]} {
jtag_ntrst_delay 100
}
mmw 0x40023808 0x00000002 0 ;# RCC_CFGR |= RCC_CFGR_SW_PLL
# Boost JTAG frequency
- adapter_khz 8000
+ adapter speed 8000
}
$_TARGETNAME configure -event reset-start {
# Reduce speed since CPU speed will slow down to 16MHz with the reset
- adapter_khz 2000
+ adapter speed 2000
}
flash bank $_CHIPNAME.itcm-flash.alias virtual 0x00200000 0 0 0 $_TARGETNAME $_FLASHNAME
# adapter speed should be <= F_CPU/6. F_CPU after reset is 16MHz, so use F_JTAG = 2MHz
-adapter_khz 2000
+adapter speed 2000
-adapter_nsrst_delay 100
+adapter srst delay 100
if {[using_jtag]} {
jtag_ntrst_delay 100
}
if {[using_jtag]} {
[[target current] cget -dap] memaccess 16
} {
- adapter_khz 8000
+ adapter speed 8000
}
}
$_TARGETNAME configure -event reset-start {
# Reduce speed since CPU speed will slow down to 16MHz with the reset
- adapter_khz 2000
+ adapter speed 2000
}
targets $_CHIPNAME.cpu0
# Clock after reset is HSI at 64 MHz, no need of PLL
-adapter_khz 1800
+adapter speed 1800
-adapter_nsrst_delay 100
+adapter srst delay 100
if {[using_jtag]} {
jtag_ntrst_delay 100
}
$_CHIPNAME.cpu0 configure -event reset-init {
# Clock after reset is HSI at 64 MHz, no need of PLL
- adapter_khz 4000
+ adapter speed 4000
}
if {[set $_CHIPNAME.DUAL_CORE]} {
# JTAG speed should be <= F_CPU/6.
# F_CPU after reset is ~2MHz, so use F_JTAG max = 333kHz
-adapter_khz 300
+adapter speed 300
-adapter_nsrst_delay 100
+adapter srst delay 100
if { [info exists CPUTAPID] } {
set _CPUTAPID $CPUTAPID
while { ([ mrw 0x4002100c ] & 0x0c) != 0x04 } { }
# Increase speed
- adapter_khz 2500
+ adapter speed 2500
}
$_TARGETNAME configure -event reset-init {
}
$_TARGETNAME configure -event reset-start {
- adapter_khz 300
+ adapter speed 300
}
$_TARGETNAME configure -event examine-end {
# JTAG speed should be <= F_CPU/6.
# F_CPU after reset is 2MHz, so use F_JTAG max = 333kHz
-adapter_khz 300
+adapter speed 300
-adapter_nsrst_delay 100
+adapter srst delay 100
if {[using_jtag]} {
jtag_ntrst_delay 100
}
mmw 0x40023808 0x00000001 0
# Increase JTAG speed
- adapter_khz 2000
+ adapter speed 2000
}
$_TARGETNAME configure -event reset-init {
}
$_TARGETNAME configure -event reset-start {
- adapter_khz 300
+ adapter speed 300
}
$_TARGETNAME configure -event examine-end {
#
# Note that there is a pretty wide band where things are
# more or less stable, see http://openocd.zylin.com/#/c/3366/
-adapter_khz 500
+adapter speed 500
-adapter_nsrst_delay 100
+adapter srst delay 100
if {[using_jtag]} {
jtag_ntrst_delay 100
}
mww 0x40022000 0x00000103 ;# FLASH_ACR = PRFTBE | 3(Latency)
mww 0x40021000 0x00000099 ;# RCC_CR = MSI_ON | MSIRGSEL | MSI Range 9
# Boost JTAG frequency
- adapter_khz 4000
+ adapter speed 4000
}
$_TARGETNAME configure -event reset-start {
# Reset clock is MSI (4 MHz)
- adapter_khz 500
+ adapter speed 500
}
$_TARGETNAME configure -event examine-end {
$_TARGETNAME configure -enable_stm8l
# The khz rate does not apply here, only slow <0> and fast <1>
-adapter_khz 1
+adapter speed 1
reset_config srst_only
#$_TARGETNAME configure -enable_step_irq
# The khz rate does not apply here, only slow <0> and fast <1>
-adapter_khz 1
+adapter speed 1
reset_config srst_only
#start slow, speed up after reset
-adapter_khz 10
+adapter speed 10
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME
-$_TARGETNAME configure -event reset-start { adapter_khz 10 }
+$_TARGETNAME configure -event reset-start { adapter speed 10 }
$_TARGETNAME configure -event reset-init {
- adapter_khz 6000
+ adapter speed 6000
# Because the hardware cannot be interrogated for the protection state
# of sectors, initialize all the sectors to be unprotected. The initial
#STR730 CPU
-adapter_khz 3000
+adapter speed 3000
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0x0f -expected-id $_CPUTAPID
#jtag nTRST and nSRST delay
-adapter_nsrst_delay 500
+adapter srst delay 500
jtag_ntrst_delay 500
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME arm7tdmi -endian little -chain-position 0
-$_TARGETNAME configure -event reset-start { adapter_khz 10 }
+$_TARGETNAME configure -event reset-start { adapter speed 10 }
$_TARGETNAME configure -event reset-init {
- adapter_khz 3000
+ adapter speed 3000
# Because the hardware cannot be interrogated for the protection state
# of sectors, initialize all the sectors to be unprotected. The initial
}
# jtag speed
-adapter_khz 10
+adapter speed 10
#use combined on interfaces or targets that can't set TRST/SRST separately
reset_config trst_and_srst srst_pulls_trst
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0x0f -expected-id $_CPUTAPID
#jtag nTRST and nSRST delay
-adapter_nsrst_delay 500
+adapter srst delay 500
jtag_ntrst_delay 500
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME arm7tdmi -endian little -chain-position 0
-$_TARGETNAME configure -event reset-start { adapter_khz 10 }
+$_TARGETNAME configure -event reset-start { adapter speed 10 }
$_TARGETNAME configure -event reset-init {
- adapter_khz 3000
+ adapter speed 3000
init_smi
# Because the hardware cannot be interrogated for the protection state
}
# jtag speed. We need to stick to 16kHz until we've finished reset.
-adapter_khz 16
+adapter speed 16
-adapter_nsrst_delay 100
+adapter srst delay 100
jtag_ntrst_delay 100
#use combined on interfaces or targets that can't set TRST/SRST separately
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME arm966e -endian $_ENDIAN -chain-position $_TARGETNAME
-$_TARGETNAME configure -event reset-start { adapter_khz 16 }
+$_TARGETNAME configure -event reset-start { adapter speed 16 }
$_TARGETNAME configure -event reset-init {
# We can increase speed now that we know the target is halted.
- #adapter_khz 3000
+ #adapter speed 3000
# -- Enable 96K RAM
# PFQBC enabled / DTCM & AHB wait-states disabled
set _WORKAREASIZE 0x10000
}
-adapter_khz 1000
+adapter speed 1000
reset_config trst_and_srst
flash bank $_FLASHNAME cc26xx 0 0 0 0 $_TARGETNAME
reset_config srst_only
-adapter_nsrst_delay 100
+adapter srst delay 100
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
reset_config srst_only
-adapter_nsrst_delay 1100
+adapter srst delay 1100
# be absolutely certain the JTAG clock will work with the worst-case
# CLKIN = 24 MHz (best case: 36 MHz) even when no bootloader turns
# on the PLL and starts using it. OK to speed up after clock setup.
-adapter_khz 1500
-$_TARGETNAME configure -event "reset-start" { adapter_khz 1500 }
+adapter speed 1500
+$_TARGETNAME configure -event "reset-start" { adapter speed 1500 }
arm7_9 fast_memory_access enable
arm7_9 dcc_downloads enable
# be absolutely certain the JTAG clock will work with the worst-case
# CLKIN = 19.2 MHz (best case: 36 MHz) even when no bootloader turns
# on the PLL and starts using it. OK to speed up after clock setup.
-adapter_khz 1500
-$_TARGETNAME configure -event "reset-start" { adapter_khz 1500 }
+adapter speed 1500
+$_TARGETNAME configure -event "reset-start" { adapter speed 1500 }
arm7_9 fast_memory_access enable
arm7_9 dcc_downloads enable
# be absolutely certain the JTAG clock will work with the worst-case
# CLKIN = 20 MHz (best case: 30 MHz) even when no bootloader turns
# on the PLL and starts using it. OK to speed up after clock setup.
-adapter_khz 1500
-$_TARGETNAME configure -event "reset-start" { adapter_khz 1500 }
+adapter speed 1500
+$_TARGETNAME configure -event "reset-start" { adapter speed 1500 }
arm7_9 fast_memory_access enable
arm7_9 dcc_downloads enable
flash bank $_FLASHNAME msp432 0 0 0 0 $_TARGETNAME
reset_config srst_only
-adapter_nsrst_delay 100
+adapter srst delay 100
-adapter_khz 1500
+adapter speed 1500
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
#use combined on interfaces or targets that can't set TRST/SRST separately
reset_config trst_and_srst
-adapter_nsrst_delay 20
+adapter srst delay 20
jtag_ntrst_delay 20
######################
#use combined on interfaces or targets that can't set TRST/SRST separately
reset_config trst_and_srst
-adapter_nsrst_delay 20
+adapter srst delay 20
jtag_ntrst_delay 20
######################
set _MAXSPEED $MAXSPEED
}
global _MAXSPEED
-adapter_khz $_MAXSPEED
+adapter speed $_MAXSPEED
gdb_breakpoint_override hard
set _TARGETNAME $_CHIPNAME.cpu
target create ${_TARGETNAME}0 cortex_a -dap $_CHIPNAME.dap -dbgbase 0xc0088000
target create ${_TARGETNAME}1 cortex_m -dap $_CHIPNAME.dap -ap-num 3 -defer-examine
-adapter_khz 1000
+adapter speed 1000
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME xmc1xxx 0x10000000 0 0 0 $_TARGETNAME
-adapter_khz 1000
+adapter speed 1000
cortex_m reset_config sysresetreq
}
-adapter_khz 1000
+adapter speed 1000
-coreid 1 -dbgbase 0x80092000
target smp ${_TARGETNAME}0 ${_TARGETNAME}1
-adapter_khz 1000
+adapter speed 1000
${_TARGETNAME}0 configure -event reset-assert-post "cortex_a dbginit"
${_TARGETNAME}1 configure -event reset-assert-post "cortex_a dbginit"
# СБИС К1879ХБ1Я
# http://www.module.ru/catalog/micro/mikroshema_dekodera_cifrovogo_televizionnogo_signala_sbis_k1879hb1ya/
-adapter_khz 1000
+adapter speed 1000
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
-adapter_nsrst_delay 200
+adapter srst delay 200
jtag_ntrst_delay 200
#use combined on interfaces or targets that can't set TRST/SRST separately
erase_part <name> erase the given partition
flash_part <name> <filename> erase, flash and verify the given partition
ram_boot <filename> load binary file to RAM and run it
-adapter_khz <freq> set JTAG clock frequency in kHz
+adapter speed <freq> set JTAG clock frequency in kHz
For example, to clear nvram and reflash CFE on an RT-N16 using TUMPA, run:
openocd -f interface/ftdi/tumpa.cfg -f tools/firmware-recovery.tcl \\
}
# set default, can be overriden later
-adapter_khz 1000
+adapter speed 1000
proc get_partition { name } {
global partition_list
projects / fw / openocd / commitdiff