tcl/board: rename board file ST b-l475e-iot01a

Use the board file name as <company>_<name>.cfg

Add the SPDX tag to workaround an error in checkpatch that fails
to recognize as valid a patch that only changes a file name.

Change-Id: I929cd9e5f9fe2e7386950643487534c9a5a05bc6
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Fixes: e44539d66c89 ("Flash, FRAM and EEPROM driver for STM32 QUAD-/OCTOSPI interface")
Reviewed-on: http://openocd.zylin.com/5931
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Tested-by: jenkins

diff --git a/tcl/board/b-l475e-iot01a.cfg b/tcl/board/b-l475e-iot01a.cfg
deleted file mode 100644 (file)
index be411e4..0000000
--- a/tcl/board/b-l475e-iot01a.cfg
+++ /dev/null
@@ -1,56 +0,0 @@
-# This is an B-L475E-IOT01A Discovery kit for IoT node with a single STM32L475VGT6 chip.
-# http://www.st.com/en/evaluation-tools/b-l475e-iot01a.html
-
-# This is for using the onboard STLINK
-source [find interface/stlink.cfg]
-
-transport select hla_swd
-
-# increase working area to 96KB
-set WORKAREASIZE 0x18000
-
-# enable stmqspi
-set QUADSPI 1
-
-source [find target/stm32l4x.cfg]
-
-# QUADSPI initialization
-proc qspi_init { } {
-       global a
-       mmw 0x4002104C 0x000001FF 0                             ;# RCC_AHB2ENR |= GPIOAEN-GPIOIEN (enable clocks)
-       mmw 0x40021050 0x00000100 0                             ;# RCC_AHB3ENR |= QSPIEN (enable clock)
-       sleep 1                                                                 ;# Wait for clock startup
-
-       # PE11: NCS, PE10: CLK, PE15: BK1_IO3, PE14: BK1_IO2, PE13: BK1_IO1, PE12: BK1_IO0
-
-       # PE15:AF10:V, PE14:AF10:V, PE13:AF10:V, PE12:AF10:V, PE11:AF10:V, PE10:AF10:V
-
-       # Port E: PE15:AF10:V, PE14:AF10:V, PE13:AF10:V, PE12:AF10:V, PE11:AF10:V, PE10:AF10:V
-       mmw 0x48001000 0xAAA00000 0x55500000    ;# MODER
-       mmw 0x48001008 0xFFF00000 0x00000000    ;# OSPEEDR
-       mmw 0x48001024 0xAAAAAA00 0x55555500    ;# AFRH
-
-       mww 0xA0001030 0x00001000                               ;# QUADSPI_LPTR: deactivate CS after 4096 clocks when FIFO is full
-       mww 0xA0001000 0x01500008                               ;# QUADSPI_CR: PRESCALER=1, APMS=1, FTHRES=0, FSEL=0, DFM=0, SSHIFT=0, TCEN=1
-       mww 0xA0001004 0x00160100                               ;# QUADSPI_DCR: FSIZE=0x16, CSHT=0x01, CKMODE=0
-       mmw 0xA0001000 0x00000001 0                             ;# QUADSPI_CR: EN=1
-
-       # memory-mapped read mode with 3-byte addresses
-       mww 0xA0001014 0x0D002503                               ;# QUADSPI_CCR: FMODE=0x3, DMODE=0x1, DCYC=0x0, ADSIZE=0x2, ADMODE=0x1, IMODE=0x1, INSTR=READ
-}
-
-$_TARGETNAME configure -event reset-init {
-       mmw 0x40022000 0x00000004 0x00000003    ;# 4 WS for 72 MHz HCLK
-       sleep 1
-       mmw 0x40021000 0x00000100 0x00000000    ;# HSI on
-       mww 0x4002100C 0x01002432                               ;# 72 MHz: PLLREN=1, PLLM=4, PLLN=36, PLLR=2, HSI
-       mww 0x40021008 0x00008001                               ;# always HSI, APB1: /1, APB2: /1
-       mmw 0x40021000 0x01000000 0x00000000    ;# PLL on
-       sleep 1
-       mmw 0x40021008 0x00000003 0x00000000    ;# switch to PLL
-       sleep 1
-
-       adapter speed 4000
-
-       qspi_init
-}

diff --git a/tcl/board/st_b-l475e-iot01a.cfg b/tcl/board/st_b-l475e-iot01a.cfg
new file mode 100644 (file)
index 0000000..e75c99d
--- /dev/null
+++ b/tcl/board/st_b-l475e-iot01a.cfg
@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is an B-L475E-IOT01A Discovery kit for IoT node with a single STM32L475VGT6 chip.
+# http://www.st.com/en/evaluation-tools/b-l475e-iot01a.html
+
+# This is for using the onboard STLINK
+source [find interface/stlink.cfg]
+
+transport select hla_swd
+
+# increase working area to 96KB
+set WORKAREASIZE 0x18000
+
+# enable stmqspi
+set QUADSPI 1
+
+source [find target/stm32l4x.cfg]
+
+# QUADSPI initialization
+proc qspi_init { } {
+       global a
+       mmw 0x4002104C 0x000001FF 0                             ;# RCC_AHB2ENR |= GPIOAEN-GPIOIEN (enable clocks)
+       mmw 0x40021050 0x00000100 0                             ;# RCC_AHB3ENR |= QSPIEN (enable clock)
+       sleep 1                                                                 ;# Wait for clock startup
+
+       # PE11: NCS, PE10: CLK, PE15: BK1_IO3, PE14: BK1_IO2, PE13: BK1_IO1, PE12: BK1_IO0
+
+       # PE15:AF10:V, PE14:AF10:V, PE13:AF10:V, PE12:AF10:V, PE11:AF10:V, PE10:AF10:V
+
+       # Port E: PE15:AF10:V, PE14:AF10:V, PE13:AF10:V, PE12:AF10:V, PE11:AF10:V, PE10:AF10:V
+       mmw 0x48001000 0xAAA00000 0x55500000    ;# MODER
+       mmw 0x48001008 0xFFF00000 0x00000000    ;# OSPEEDR
+       mmw 0x48001024 0xAAAAAA00 0x55555500    ;# AFRH
+
+       mww 0xA0001030 0x00001000                               ;# QUADSPI_LPTR: deactivate CS after 4096 clocks when FIFO is full
+       mww 0xA0001000 0x01500008                               ;# QUADSPI_CR: PRESCALER=1, APMS=1, FTHRES=0, FSEL=0, DFM=0, SSHIFT=0, TCEN=1
+       mww 0xA0001004 0x00160100                               ;# QUADSPI_DCR: FSIZE=0x16, CSHT=0x01, CKMODE=0
+       mmw 0xA0001000 0x00000001 0                             ;# QUADSPI_CR: EN=1
+
+       # memory-mapped read mode with 3-byte addresses
+       mww 0xA0001014 0x0D002503                               ;# QUADSPI_CCR: FMODE=0x3, DMODE=0x1, DCYC=0x0, ADSIZE=0x2, ADMODE=0x1, IMODE=0x1, INSTR=READ
+}
+
+$_TARGETNAME configure -event reset-init {
+       mmw 0x40022000 0x00000004 0x00000003    ;# 4 WS for 72 MHz HCLK
+       sleep 1
+       mmw 0x40021000 0x00000100 0x00000000    ;# HSI on
+       mww 0x4002100C 0x01002432                               ;# 72 MHz: PLLREN=1, PLLM=4, PLLN=36, PLLR=2, HSI
+       mww 0x40021008 0x00008001                               ;# always HSI, APB1: /1, APB2: /1
+       mmw 0x40021000 0x01000000 0x00000000    ;# PLL on
+       sleep 1
+       mmw 0x40021008 0x00000003 0x00000000    ;# switch to PLL
+       sleep 1
+
+       adapter speed 4000
+
+       qspi_init
+}