add config for Microchip SAMA5D27 SOM1 Kit1

... and related SAMA5D27 SoC.

Change-Id: Ic2584e3005ac691642dc2e5a8ee3fb8a4eacaa00
Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
Reviewed-on: http://openocd.zylin.com/5275
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>

diff --git a/tcl/board/microchip_sama5d27_som1_kit1.cfg b/tcl/board/microchip_sama5d27_som1_kit1.cfg
new file mode 100644 (file)
index 0000000..8e92040
--- /dev/null
+++ b/tcl/board/microchip_sama5d27_som1_kit1.cfg
@@ -0,0 +1,19 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Microchip SAMA5D27-SOM1-EK1
+# https://www.microchip.com/DevelopmentTools/ProductDetails/PartNO/ATSAMA5D27-SOM1-EK1
+# This board provide two jtag interfaces:
+# J11 - 10 pin interface
+# J10 - USB interface connected to the J-Link-OB.
+#       This functionality is implemented with an ATSAM3U4C microcontroller and
+#       provides JTAG functions and a bridge USB/Serial debug port (CDC).
+#
+# Jumper J7 disables the J-Link-OB-ATSAM3U4C JTAG functionality.
+# - Jumper J7 not installed: J-Link-OB-ATSAM3U4C is enabled and fully functional.
+# - Jumper J7 installed: J-Link-OB-ATSAM3U4C is disabled and an external JTAG
+#   controller can be used through the 10-pin JTAG port J11.
+
+source [find interface/jlink.cfg]
+reset_config srst_only
+
+source [find target/at91sama5d2.cfg]

diff --git a/tcl/target/at91sama5d2.cfg b/tcl/target/at91sama5d2.cfg
new file mode 100644 (file)
index 0000000..65e5217
--- /dev/null
+++ b/tcl/target/at91sama5d2.cfg
@@ -0,0 +1,28 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# The JTAG connection is disabled at reset, and during the ROM Code execution.
+# It is re-enabled when the ROM code jumps in the boot file copied from an
+# external Flash memory into the internalSRAM, or when the ROM code launches
+# the SAM-BA monitor, when no boot file has been found in any external Flash
+# memory.
+# For more JTAG related information see, :
+# https://ww1.microchip.com/downloads/en/DeviceDoc/SAMA5D2-Series-Data-sheet-ds60001476G.pdf
+#
+# If JTAGSEL pin:
+# - if enabled, boundary Scan mode is activated. JTAG ID Code value is 0x05B3F03F.
+# - if disabled, ICE mode is activated. Debug Port JTAG IDCODE value is 0x5BA00477
+#
+if { [info exists CHIPNAME] } {
+       set  _CHIPNAME $CHIPNAME
+} else {
+       set  _CHIPNAME at91sama5d2
+}
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f \
+       -expected-id 0x5ba00477
+
+# Cortex-A5 target
+set _TARGETNAME $_CHIPNAME.cpu_a5
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+target create $_TARGETNAME.0 cortex_a -dap $_CHIPNAME.dap