target/icepick.cfg: Add support for Test TAPs in ICEPick C

In addition to the debug TAPs, the ICEPick C also supports
a bank of Test TAPs (limited functionality intended for
non-debuggable targets). Added support for Test TAPs to
the icepick_c_tapenable routine. Port numbers of 0 to 15
will continue to be handled as a debug TAP number. Test
TAPs will be port numbers of 16 to 31.

This functionality will be needed for doing a flash
mass erase on CC26xx/CC13xx targets. It is possible
for user application to block even adding the Cortex M
TAP to the scan chain, so the only way to unbrick the
target and erase the flash is using a component on a
test TAP of the device's ICEPick router.

Change-Id: I0aa52a08d43a00cbd396efdeadd504fc31c98510
Signed-off-by: Edward Fewell <efewell@ti.com>
Reviewed-on: http://openocd.zylin.com/5715
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

diff --git a/tcl/target/icepick.cfg b/tcl/target/icepick.cfg
index 36b0b7033b88ba333d75744546179b9eb245c00b..d1250711bf8a594af5de27b7624b0af778b08a18 100644 (file)
--- a/tcl/target/icepick.cfg
+++ b/tcl/target/icepick.cfg
@@ -75,9 +75,22 @@ proc icepick_c_setup {jrc} {
 }
 
 # jrc  == TAP name for the ICEpick
-# port == a port number, 0..15
+# port == a port number, 0..15 for debug tap, 16..31 for test tap
 proc icepick_c_tapenable {jrc port} {
 
+       if { ($port >= 0) && ($port < 16) } {
+               # Debug tap"
+               set tap $port
+               set block 0x2
+       } elseif { $port < 32 } {
+               # Test tap
+               set tap [expr ($port - 16)]
+               set block 0x1
+       } else {
+               echo "ERROR: Invalid ICEPick C port number: $port"
+               return
+       }
+
        # First CONNECT to the ICEPick
 #      echo "Connecting to ICEPick"
        icepick_c_connect $jrc
@@ -90,18 +103,18 @@ proc icepick_c_tapenable {jrc port} {
        # And never to enter RESET, which will disable the TAPs.
 
        # first enable power and clock for TAP
-       icepick_c_router $jrc 1 0x2 $port 0x110048
+       icepick_c_router $jrc 1 $block $tap 0x110048
 
        # TRM states that the register should be read back here, skipped for now
 
        # enable debug "default" mode
-       icepick_c_router $jrc 1 0x2 $port 0x112048
+       icepick_c_router $jrc 1 $block $tap 0x112048
 
        # TRM states that debug enable and debug mode should be read back and
        # confirmed - skipped for now
 
        # Finally select the tap
-       icepick_c_router $jrc 1 0x2 $port 0x112148
+       icepick_c_router $jrc 1 $block $tap 0x112148
 
        # Enter the bypass state
        irscan $jrc [CONST IR_BYPASS] -endstate RUN/IDLE
@@ -119,6 +132,7 @@ proc icepick_d_set_core_control {jrc coreid value } {
 # Follow the sequence described in
 # http://processors.wiki.ti.com/images/f/f6/Router_Scan_Sequence-ICEpick-D.pdf
 proc icepick_d_tapenable {jrc port coreid { value 0x2008 } } {
+
        # First CONNECT to the ICEPick
        icepick_c_connect $jrc
        icepick_c_setup $jrc