Examples:
0x1f0f0f0f - is an old ARM7TDMI
0x3f0f0f0f - is a newer ARM7TDMI
- 0x3ba00477 - is an ARM cortex M3
+ 0x3ba00477 - is an ARM Cortex-M3
Some chips have multiple JTAG taps - be sure to list
each one individually - ORDER is important!
garabage.
- implement missing functionality (grep FNC_INFO_NOTIMPLEMENTED ...)
- Thumb2 single stepping: ARM1156T2 needs simulator support
-- Cortex A8 support (ML)
+- Cortex-A8 support (ML)
- add target implementation (ML)
-- Cortex M3 support
+- Cortex-M3 support
- when stepping, only write dirtied registers (be faster)
- when connecting to halted core, fetch registers (startup is quirky)
- Generic ARM run_algorithm() interface
/* Written for NRF51822 (src/flash/nor/nrf51.c) however the NRF NVMC is
* very generic (CPU blocks during flash writes), so this is actually
- * just a generic word-oriented copy routine for cortex-m0 (also
- * suitable for cortex m0plus/m3/m4.)
+ * just a generic word-oriented copy routine for Cortex-M0 (also
+ * suitable for Cortex-M0+/M3/M4.)
*
* To assemble:
* arm-none-eabi-gcc -c cortex-m0.S
and target chip, but you need a new board-specific config file
giving access to your particular flash chips.
Or you might need to write another target chip configuration file
-for a new chip built around the Cortex M3 core.
+for a new chip built around the Cortex-M3 core.
@quotation Note
When you write new configuration files, please submit
@deffn {Flash Driver} efm32
All members of the EFM32 microcontroller family from Energy Micro include
-internal flash and use ARM Cortex M3 cores. The driver automatically recognizes
+internal flash and use ARM Cortex-M3 cores. The driver automatically recognizes
a number of these chips using the chip identification register, and
autoconfigures itself.
@example
@deffn {Flash Driver} fm3
All members of the FM3 microcontroller family from Fujitsu
-include internal flash and use ARM Cortex M3 cores.
+include internal flash and use ARM Cortex-M3 cores.
The @var{fm3} driver uses the @var{target} parameter to select the
correct bank config, it can currently be one of the following:
@code{mb9bfxx1.cpu}, @code{mb9bfxx2.cpu}, @code{mb9bfxx3.cpu},
@deffn {Flash Driver} kinetis
@cindex kinetis
Kx and KLx members of the Kinetis microcontroller family from Freescale include
-internal flash and use ARM Cortex M0+ or M4 cores. The driver automatically
+internal flash and use ARM Cortex-M0+ or M4 cores. The driver automatically
recognizes flash size and a number of flash banks (1-4) using the chip
identification register, and autoconfigures itself.
@deffn {Flash Driver} kinetis_ke
@cindex kinetis_ke
KE members of the Kinetis microcontroller family from Freescale include
-internal flash and use ARM Cortex M0+. The driver automatically recognizes
+internal flash and use ARM Cortex-M0+. The driver automatically recognizes
the KE family and sub-family using the chip identification register, and
autoconfigures itself.
@deffn {Flash Driver} psoc4
All members of the PSoC 41xx/42xx microcontroller family from Cypress
-include internal flash and use ARM Cortex M0 cores.
+include internal flash and use ARM Cortex-M0 cores.
The driver automatically recognizes a number of these chips using
the chip identification register, and autoconfigures itself.
@deffn {Flash Driver} sim3x
All members of the SiM3 microcontroller family from Silicon Laboratories
-include internal flash and use ARM Cortex M3 cores. It supports both JTAG
+include internal flash and use ARM Cortex-M3 cores. It supports both JTAG
and SWD interface.
The @var{sim3x} driver tries to probe the device to auto detect the MCU.
If this failes, it will use the @var{size} parameter as the size of flash bank.
_unknown, /* 0 */
"arm946es", /* 1 */
"arm7tdmi", /* 2 */
- "cortex-m3", /* 3 */
+ "Cortex-M3", /* 3 */
"arm920t", /* 4 */
"arm926ejs", /* 5 */
_unknown, /* 6 */
_unknown, /* 0 */
"arm946es", /* 1 */
"arm7tdmi", /* 2 */
- "cortex-m3", /* 3 */
+ "Cortex-M3", /* 3 */
"arm920t", /* 4 */
"arm926ejs", /* 5 */
- "cortex-a5", /* 6 */
- "cortex-m4", /* 7 */
+ "Cortex-A5", /* 6 */
+ "Cortex-M4", /* 7 */
_unknown, /* 8 */
_unknown, /* 9 */
_unknown, /* 10 */
uint8_t eproc = (device_id >> 5) & 0x7;
if (eproc != 0) {
- LOG_ERROR("unexpected eproc code: %d was expecting 0 (cortex-m7)", eproc);
+ LOG_ERROR("unexpected eproc code: %d was expecting 0 (Cortex-M7)", eproc);
return ERROR_FAIL;
}
return ret;
if (((cpuid >> 4) & 0xfff) == 0xc23) {
- /* Cortex M3 device */
+ /* Cortex-M3 device */
} else if (((cpuid >> 4) & 0xfff) == 0xc24) {
- /* Cortex M4 device(WONDER GECKO) */
+ /* Cortex-M4 device (WONDER GECKO) */
} else if (((cpuid >> 4) & 0xfff) == 0xc60) {
- /* Cortex M0plus device */
+ /* Cortex-M0+ device */
} else {
LOG_ERROR("Target is not Cortex-Mx Device");
return ERROR_FAIL;
static int get_niietcm4_info(struct flash_bank *bank, char *buf, int buf_size)
{
struct niietcm4_flash_bank *niietcm4_info = bank->driver_priv;
- LOG_INFO("\nNIIET Cortex M4F %s\n%s", niietcm4_info->chip_name, niietcm4_info->chip_brief);
+ LOG_INFO("\nNIIET Cortex-M4F %s\n%s", niietcm4_info->chip_name, niietcm4_info->chip_brief);
snprintf(buf, buf_size, " ");
return ERROR_OK;
}
if (((cpuid >> 4) & 0xfff) != 0xc23) {
- LOG_ERROR("Target is not CortexM3");
+ LOG_ERROR("Target is not Cortex-M3");
return ERROR_FAIL;
}
return ret;
if ((val & CPUID_CHECK_VALUE_MASK) != CPUID_CHECK_VALUE) {
- LOG_ERROR("Target is not ARM CortexM3 or is already locked");
+ LOG_ERROR("Target is not ARM Cortex-M3 or is already locked");
return ERROR_FAIL;
}
} else {
***************************************************************************/
/***************************************************************************
- * Version 1.0 Tested on a MCBSTM32 board using a Cortex M3 (stm32f103x), *
+ * Version 1.0 Tested on a MCBSTM32 board using a Cortex-M3 (stm32f103x), *
* GDB and Eclipse under Linux (Ubuntu 10.04) *
* *
***************************************************************************/
if (h->jtag_api == STLINK_JTAG_API_V2) {
/* TODO: this emulates the v1 api, it should really use a similar auto mask isr
- * that the cortex-m3 currently does. */
+ * that the Cortex-M3 currently does. */
stlink_usb_write_debug_reg(handle, DCB_DHCSR, DBGKEY|C_HALT|C_MASKINTS|C_DEBUGEN);
stlink_usb_write_debug_reg(handle, DCB_DHCSR, DBGKEY|C_STEP|C_MASKINTS|C_DEBUGEN);
return stlink_usb_write_debug_reg(handle, DCB_DHCSR, DBGKEY|C_HALT|C_DEBUGEN);
/* Sometimes the stacking can not be determined only by looking at the
* target name but only a runtime.
*
- * For example, this is the case for cortex-m4 targets and ChibiOS which
+ * For example, this is the case for Cortex-M4 targets and ChibiOS which
* only stack the FPU registers if it is enabled during ChibiOS build.
*
* Terminating which stacking is used is target depending.
struct ChibiOS_params *param;
param = (struct ChibiOS_params *) rtos->rtos_specific_params;
- /* Check for armv7m with *enabled* FPU, i.e. a Cortex M4 */
+ /* Check for armv7m with *enabled* FPU, i.e. a Cortex-M4 */
struct armv7m_common *armv7m_target = target_to_armv7m(rtos->target);
if (is_armv7m(armv7m_target)) {
if (armv7m_target->fp_feature == FPv4_SP) {
thread_id + param->thread_stack_offset,
stack_ptr);
- /* Check for armv7m with *enabled* FPU, i.e. a Cortex M4F */
+ /* Check for armv7m with *enabled* FPU, i.e. a Cortex-M4F */
int cm4_fpu_enabled = 0;
struct armv7m_common *armv7m_target = target_to_armv7m(rtos->target);
if (is_armv7m(armv7m_target)) {
enum mqx_arch arch_type = ((struct mqx_params *)rtos->rtos_specific_params)->target_arch;
const char * targetname = ((struct mqx_params *)rtos->rtos_specific_params)->target_name;
- /* Cortex M address range */
+ /* Cortex-M address range */
if (arch_type == mqx_arch_cortexm) {
if (
/* code and sram area */
stacking, stack_ptr, 8);
}
-/* The Cortex M3 will indicate that an alignment adjustment
+/* The Cortex-M3 will indicate that an alignment adjustment
* has been done on the stack by setting bit 9 of the stacked xPSR
* register. In this case, we can just add an extra 4 bytes to get
* to the program stack. Note that some places in the ARM documentation
return retval;
}
-/* method adapted to cortex A : reused arm v4 v5 method*/
+/* method adapted to Cortex-A : reused ARM v4 v5 method */
int armv7a_mmu_translate_va(struct target *target, uint32_t va, uint32_t *val)
{
uint32_t first_lvl_descriptor = 0x0;
* michel.jaouen@stericsson.com : smp minimum support *
* *
* Copyright (C) Broadcom 2012 *
- * ehunter@broadcom.com : Cortex R4 support *
+ * ehunter@broadcom.com : Cortex-R4 support *
* *
* Copyright (C) 2013 Kamal Dasu *
* kdasu.kdev@gmail.com *
/*
* Cortex-A Memory access
*
- * This is same Cortex M3 but we must also use the correct
+ * This is same Cortex-M3 but we must also use the correct
* ap number for every access.
*/
}
LOG_DEBUG("cpuid: 0x%8.8" PRIx32 "", cpuid);
- /* test for floating point feature on cortex-m4 */
+ /* test for floating point feature on Cortex-M4 */
if (i == 4) {
target_read_u32(target, MVFR0, &mvfr0);
target_read_u32(target, MVFR1, &mvfr1);
#
-# Cortex A9 target
+# Cortex-A9 target
#
# GDB target: Cortex-A9, using DAP, configuring only one core
#$_TARGETNAME2 configure -event gdb-attach { halt }
proc cycv_dbginit {target} {
- # General Cortex A8/A9 debug initialisation
+ # General Cortex-A8/A9 debug initialisation
cortex_a dbginit
}
}
#
-# Cortex M3 target
+# Cortex-M3 target
#
set _TARGETNAME_2 $_CHIPNAME.m3
target create $_TARGETNAME_2 cortex_m -chain-position $_CHIPNAME.m3_dap
#
-# Cortex A8 target
+# Cortex-A8 target
#
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap -dbgbase 0x80001000
jtag configure $JRC_NAME -event post-reset "runtest 100"
#
-# Cortex A9 target
+# Cortex-A9 target
#
target create $_TARGETNAME cortex_a -chain-position $DEBUGSS_NAME -coreid 0 -dbgbase 0x80000000
# Run this to enable invasive debugging. This is run automatically in the
# reset sequence.
proc amdm37x_dbginit {target} {
- # General Cortex A8 debug initialisation
+ # General Cortex-A8 debug initialisation
cortex_a dbginit
# Enable DBGEN signal. This signal is described in the ARM v7 TRM, but
-# script for ATMEL sam3, a CORTEX-M3 chip
+# script for ATMEL sam3, a Cortex-M3 chip
#
# at91sam3u4e
# at91sam3u2e
-# script for ATMEL sam3, a CORTEX-M3 chip
+# script for ATMEL sam3, a Cortex-M3 chip
#
# at91sam3A4C
# at91sam3A8C
-# script for ATMEL sam3, a CORTEX-M3 chip
+# script for ATMEL sam3, a Cortex-M3 chip
#
# at91sam3s4c
# at91sam3s4b
-# script for ATMEL sam3, a CORTEX-M3 chip
+# script for ATMEL sam3, a Cortex-M3 chip
#
# at91sam3u4e
# at91sam3u2e
#
-# script for ATMEL sam4, a CORTEX-M4 chip
+# script for ATMEL sam4, a Cortex-M4 chip
#
#
-# script for ATMEL sam4l, a CORTEX-M4 chip
+# script for ATMEL sam4l, a Cortex-M4 chip
#
source [find target/at91sam4XXX.cfg]
-# script for ATMEL sam4, a CORTEX-M4 chip
+# script for ATMEL sam4, a Cortex-M4 chip
#
source [find target/at91sam4XXX.cfg]
-# script for ATMEL sam4sd32, a CORTEX-M4 chip
+# script for ATMEL sam4sd32, a Cortex-M4 chip
#
source [find target/at91sam4XXX.cfg]
#
-# script for Atmel SAMD, SAMR, SAML or SAMC, a CORTEX-M0 chip
+# script for Atmel SAMD, SAMR, SAML or SAMC, a Cortex-M0 chip
#
#
-# script for the ATMEL samg5x CORTEX-M4F chip family
+# script for the ATMEL samg5x Cortex-M4F chip family
#
source [find target/at91sam4XXX.cfg]
jtag newtap $_CHIPNAME dap -expected-id $_DAP_TAPID -irlen 4
-# Dual Cortex A9s
+# Dual Cortex-A9
set _TARGETNAME0 $_CHIPNAME.cpu0
set _TARGETNAME1 $_CHIPNAME.cpu1
jtag configure $_CHIPNAME.jrc -event post-reset "ti_cjtag_to_4pin_jtag $_CHIPNAME.jrc"
#
-# Cortex M3 target
+# Cortex-M3 target
#
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -chain-position $_CHIPNAME.dap
}
#
-# Cortex M3 target
+# Cortex-M3 target
#
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -chain-position $_CHIPNAME.dap
jtag_ntrst_delay 100
}
-# Fujitsu cortex-M3 reset configuration
+# Fujitsu Cortex-M3 reset configuration
reset_config trst_only
swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
jtag configure $_CHIPNAME.SJC -event setup "jtag tapenable $_CHIPNAME.DAP"
proc imx51_dbginit {target} {
- # General Cortex A8 debug initialisation
+ # General Cortex-A8 debug initialisation
cortex_a dbginit
}
jtag configure $_CHIPNAME.SJC -event setup "jtag tapenable $_CHIPNAME.DAP"
proc imx53_dbginit {target} {
- # General Cortex A8 debug initialisation
+ # General Cortex-A8 debug initialisation
cortex_a dbginit
}
jtag configure $_CHIPNAME.sjc -event post-reset "runtest 100"
proc imx6_dbginit {target} {
- # General Cortex A8/A9 debug initialisation
+ # General Cortex-A8/A9 debug initialisation
cortex_a dbginit
}
# Allow user override
set _CPUTAPID $CPUTAPID
} else {
- # LPC8xx/LPC11xx/LPC12xx use a Cortex M0/M0+ core, LPC13xx/LPC17xx use a Cortex M3 core,LPC40xx use a Cortex-M4F core.
+ # LPC8xx/LPC11xx/LPC12xx use a Cortex-M0/M0+ core, LPC13xx/LPC17xx use a Cortex-M3 core, LPC40xx use a Cortex-M4F core.
if { $_CHIPSERIES == "lpc800" || $_CHIPSERIES == "lpc1100" || $_CHIPSERIES == "lpc1200" } {
set _CPUTAPID 0x0bb11477
} elseif { $_CHIPSERIES == "lpc1300" || $_CHIPSERIES == "lpc1700" || $_CHIPSERIES == "lpc4000" } {
jtag_ntrst_delay 200
}
-# LPC8xx (Cortex M0+ core) support SYSRESETREQ
-# LPC11xx/LPC12xx (Cortex M0 core) support SYSRESETREQ
-# LPC13xx/LPC17xx (Cortex M3 core) support SYSRESETREQ
-# LPC40xx (Cortex M4F core) support SYSRESETREQ
+# LPC8xx (Cortex-M0+ core) support SYSRESETREQ
+# LPC11xx/LPC12xx (Cortex-M0 core) support SYSRESETREQ
+# LPC13xx/LPC17xx (Cortex-M3 core) support SYSRESETREQ
+# LPC40xx (Cortex-M4F core) support SYSRESETREQ
if {![using_hla]} {
# if srst is not fitted use SYSRESETREQ to
# perform a soft reset
#
-# script for Nordic nRF51 series, a CORTEX-M0 chip
+# script for Nordic nRF51 series, a Cortex-M0 chip
#
source [find target/swj-dp.tcl]
jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.dap"
proc omap3_dbginit {target} {
- # General Cortex A8 debug initialisation
+ # General Cortex-A8 debug initialisation
cortex_a dbginit
# Enable DBGU signal for OMAP353x
$target mww phys 0x5401d030 0x00002000
#
# Target configuration for the ST STM32W108xx chips
#
-# Processor: ARM Cortex M3
+# Processor: ARM Cortex-M3
# Date: 2013-06-09
# Author: Giuseppe Barba <giuseppe.barba@gmail.com>
jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.dap"
jtag configure $_CHIPNAME.jrc -event post-reset "runtest 100"
-# Cortex R4 target
+# Cortex-R4 target
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_r4 -endian $_ENDIAN \
-chain-position $_CHIPNAME.dap -coreid 0 -dbgbase 0x00001003
projects / fw / openocd / commitdiff