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(parent: 27e7f5d) | patch
target/xtensa: invalidate register cache on reset
authorIan Thompson <ianst@cadence.com>
Thu, 15 Sep 2022 21:14:15 +0000 (14:14 -0700)
committerAntonio Borneo <borneo.antonio@gmail.com>
Sun, 18 Sep 2022 08:12:02 +0000 (08:12 +0000)
commit61d0757acf222fdd5669b471cc251e03101db273
treef944aec9c424613a83598195f28d857b44e246detree | snapshot
parent27e7f5df5ff691a78ca7530892ee5dc05820a947commit | diff
target/xtensa: invalidate register cache on reset

Resolves issues where registers are accessed when poll() logic is inactive or has not yet been triggered.

Signed-off-by: Ian Thompson <ianst@cadence.com>
Change-Id: If7a4d00938fb188b008325249627f7773c3484c5
Reviewed-on: https://review.openocd.org/c/openocd/+/7197
Tested-by: jenkins
Reviewed-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
src/target/xtensa/xtensa.c diff | blob | history
openocd with support for Altus Metrum targets