1 # SPDX-License-Identifier: GPL-2.0-or-later
2 # Copyright (C) 2019-2021 Texas Instruments Incorporated - http://www.ti.com/
4 # Texas Instruments K3 devices:
5 # * AM654x: https://www.ti.com/lit/pdf/spruid7
6 # Has 4 ARMV8 Cores and 2 R5 Cores and an M3
7 # * J721E: https://www.ti.com/lit/pdf/spruil1
8 # Has 2 ARMV8 Cores and 6 R5 Cores and an M3
9 # * J7200: https://www.ti.com/lit/pdf/spruiu1
10 # Has 2 ARMV8 Cores and 4 R5 Cores and an M3
11 # * AM642: https://www.ti.com/lit/pdf/spruim2
12 # Has 2 ARMV8 Cores and 4 R5 Cores, M4F and an M3
15 if { [info exists SOC] } {
21 # set V8_SMP_DEBUG to non 0 value in board if you'd like to use SMP debug
22 if { [info exists V8_SMP_DEBUG] } {
23 set _v8_smp_debug $V8_SMP_DEBUG
30 # System Controller is the very first processor - all current SoCs have it.
31 set CM3_CTIBASE {0x3C016000}
33 # sysctrl power-ap unlock offsets
34 set _sysctrl_ap_unlock_offsets {0xf0 0x44}
36 # All the ARMV8s are the next processors.
37 # CL0,CORE0 CL0,CORE1 CL1,CORE0 CL1,CORE1
38 set ARMV8_DBGBASE {0x90410000 0x90510000 0x90810000 0x90910000}
39 set ARMV8_CTIBASE {0x90420000 0x90520000 0x90820000 0x90920000}
41 # And we add up the R5s
42 # (0)MCU 0 (1)MCU 1 (2)MAIN_0_0 (3)MAIN_0_1 (4)MAIN_1_0 (5)MAIN_1_1
43 set R5_DBGBASE {0x9d010000 0x9d012000 0x9d410000 0x9d412000 0x9d510000 0x9d512000}
44 set R5_CTIBASE {0x9d018000 0x9d019000 0x9d418000 0x9d419000 0x9d518000 0x9d519000}
45 set R5_NAMES {mcu_r5.0 mcu_r5.1 main0_r5.0 main0_r5.1 main1_r5.0 main1_r5.1}
47 # Finally an General Purpose(GP) MCU
48 set CM4_CTIBASE {0x20001000}
50 # General Purpose MCU (M4) may be present on some very few SoCs
52 # General Purpose MCU power-ap unlock offsets
53 set _gp_mcu_ap_unlock_offsets {0xf0 0x60}
55 # Set configuration overrides for each SOC
59 set _K3_DAP_TAPID 0x0bb5a02f
61 # AM654 has 2 clusters of 2 A53 cores each.
62 set _armv8_cpu_name a53
65 # AM654 has 1 cluster of 2 R5s cores.
67 set R5_NAMES {mcu_r5.0 mcu_r5.1}
69 # Sysctrl power-ap unlock offsets
70 set _sysctrl_ap_unlock_offsets {0xf0 0x50}
74 set _K3_DAP_TAPID 0x0bb3802f
76 # AM642 has 1 clusters of 2 A53 cores each.
77 set _armv8_cpu_name a53
79 set ARMV8_DBGBASE {0x90010000 0x90110000}
80 set ARMV8_CTIBASE {0x90020000 0x90120000}
82 # AM642 has 2 cluster of 2 R5s cores.
84 set R5_NAMES {main0_r5.0 main0_r5.1 main1_r5.0 main1_r5.1}
85 set R5_DBGBASE {0x9d410000 0x9d412000 0x9d510000 0x9d512000}
86 set R5_CTIBASE {0x9d418000 0x9d419000 0x9d518000 0x9d519000}
93 set _K3_DAP_TAPID 0x0bb6402f
94 # J721E has 1 cluster of 2 A72 cores.
95 set _armv8_cpu_name a72
98 # J721E has 3 clusters of 2 R5 cores each.
103 set _K3_DAP_TAPID 0x0bb6d02f
105 # J7200 has 1 cluster of 2 A72 cores.
106 set _armv8_cpu_name a72
109 # J7200 has 2 clusters of 2 R5 cores each.
111 set R5_DBGBASE {0x9d010000 0x9d012000 0x9d110000 0x9d112000}
112 set R5_CTIBASE {0x9d018000 0x9d019000 0x9d118000 0x9d119000}
115 set CM3_CTIBASE {0x20001000}
119 set _K3_DAP_TAPID 0x0bb7502f
121 # J721s2 has 1 cluster of 2 A72 cores.
122 set _armv8_cpu_name a72
125 # J721s2 has 3 clusters of 2 R5 cores each.
129 set CM3_CTIBASE {0x20001000}
130 # Sysctrl power-ap unlock offsets
131 set _sysctrl_ap_unlock_offsets {0xf0 0x78}
135 set _gp_mcu_ap_unlock_offsets {0xf0 0x7c}
138 echo "'$_soc' is invalid!"
142 jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_K3_DAP_TAPID -ignore-version
143 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
145 set _TARGETNAME $_CHIPNAME.cpu
147 set _CTINAME $_CHIPNAME.cti
149 # sysctrl is always present
150 cti create $_CTINAME.sysctrl -dap $_CHIPNAME.dap -ap-num 7 -baseaddr [lindex $CM3_CTIBASE 0]
151 target create $_TARGETNAME.sysctrl cortex_m -dap $_CHIPNAME.dap -ap-num 7 -defer-examine
152 $_TARGETNAME.sysctrl configure -event reset-assert { }
155 # To access sysctrl, we need to enable the JTAG access for the same.
156 # Ensure Power-AP unlocked
157 $::_CHIPNAME.dap apreg 3 [lindex $::_sysctrl_ap_unlock_offsets 0] 0x00190000
158 $::_CHIPNAME.dap apreg 3 [lindex $::_sysctrl_ap_unlock_offsets 1] 0x00102098
160 $::_TARGETNAME.sysctrl arp_examine
163 $_TARGETNAME.sysctrl configure -event gdb-attach {
165 # gdb-attach default rule
169 proc _cpu_no_smp_up {} {
170 set _current_target [target current]
171 set _current_type [$_current_target cget -type]
173 $_current_target arp_examine
174 $_current_target $_current_type dbginit
177 proc _armv8_smp_up {} {
178 for { set _core 0 } { $_core < $::_armv8_cores } { incr _core } {
179 $::_TARGETNAME.$::_armv8_cpu_name.$_core arp_examine
180 $::_TARGETNAME.$::_armv8_cpu_name.$_core aarch64 dbginit
181 $::_TARGETNAME.$::_armv8_cpu_name.$_core aarch64 smp on
183 # Set Default target as core 0
184 targets $::_TARGETNAME.$::_armv8_cpu_name.0
187 set _v8_smp_targets ""
189 for { set _core 0 } { $_core < $_armv8_cores } { incr _core } {
191 cti create $_CTINAME.$_armv8_cpu_name.$_core -dap $_CHIPNAME.dap -ap-num 1 \
192 -baseaddr [lindex $ARMV8_CTIBASE $_core]
194 target create $_TARGETNAME.$_armv8_cpu_name.$_core aarch64 -dap $_CHIPNAME.dap \
195 -dbgbase [lindex $ARMV8_DBGBASE $_core] -cti $_CTINAME.$_armv8_cpu_name.$_core -defer-examine
197 set _v8_smp_targets "$_v8_smp_targets $_TARGETNAME.$_armv8_cpu_name.$_core"
199 if { $_v8_smp_debug == 0 } {
200 $_TARGETNAME.$_armv8_cpu_name.$_core configure -event gdb-attach {
202 # gdb-attach default rule
206 $_TARGETNAME.$_armv8_cpu_name.$_core configure -event gdb-attach {
208 # gdb-attach default rule
214 # Setup ARMV8 proc commands based on CPU to prevent people confusing SoCs
215 set _armv8_up_cmd "$_armv8_cpu_name"_up
216 # Available if V8_SMP_DEBUG is set to non-zero value
217 set _armv8_smp_cmd "$_armv8_cpu_name"_smp
219 if { $_v8_smp_debug == 0 } {
220 proc $_armv8_up_cmd { args } {
221 foreach _core $args {
227 proc $_armv8_smp_cmd { args } {
231 target smp $:::_v8_smp_targets
234 for { set _core 0 } { $_core < $_r5_cores } { incr _core } {
235 set _r5_name [lindex $R5_NAMES $_core]
236 cti create $_CTINAME.$_r5_name -dap $_CHIPNAME.dap -ap-num 1 \
237 -baseaddr [lindex $R5_CTIBASE $_core]
239 # inactive core examination will fail - wait till startup of additional core
240 target create $_TARGETNAME.$_r5_name cortex_r4 -dap $_CHIPNAME.dap \
241 -dbgbase [lindex $R5_DBGBASE $_core] -ap-num 1 -defer-examine
243 $_TARGETNAME.$_r5_name configure -event gdb-attach {
245 # gdb-attach default rule
250 proc r5_up { args } {
251 foreach _core $args {
257 if { $_gp_mcu_cores != 0 } {
258 cti create $_CTINAME.gp_mcu -dap $_CHIPNAME.dap -ap-num 8 -baseaddr [lindex $CM4_CTIBASE 0]
259 target create $_TARGETNAME.gp_mcu cortex_m -dap $_CHIPNAME.dap -ap-num 8 -defer-examine
260 $_TARGETNAME.gp_mcu configure -event reset-assert { }
263 # To access GP MCU, we need to enable the JTAG access for the same.
264 # Ensure Power-AP unlocked
265 $::_CHIPNAME.dap apreg 3 [lindex $::_gp_mcu_ap_unlock_offsets 0] 0x00190000
266 $::_CHIPNAME.dap apreg 3 [lindex $::_gp_mcu_ap_unlock_offsets 1] 0x00102098
268 $::_TARGETNAME.gp_mcu arp_examine
271 $_TARGETNAME.gp_mcu configure -event gdb-attach {
273 # gdb-attach default rule